Commit | Line | Data |
---|---|---|
b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 LT |
2 | /* smp.c: Sparc64 SMP support. |
3 | * | |
cf3d7c1e | 4 | * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
5 | */ |
6 | ||
066bcaca | 7 | #include <linux/export.h> |
1da177e4 | 8 | #include <linux/kernel.h> |
68e21be2 | 9 | #include <linux/sched/mm.h> |
ef8bd77f | 10 | #include <linux/sched/hotplug.h> |
1da177e4 LT |
11 | #include <linux/mm.h> |
12 | #include <linux/pagemap.h> | |
13 | #include <linux/threads.h> | |
14 | #include <linux/smp.h> | |
1da177e4 LT |
15 | #include <linux/interrupt.h> |
16 | #include <linux/kernel_stat.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/spinlock.h> | |
20 | #include <linux/fs.h> | |
21 | #include <linux/seq_file.h> | |
22 | #include <linux/cache.h> | |
23 | #include <linux/jiffies.h> | |
24 | #include <linux/profile.h> | |
73fffc03 | 25 | #include <linux/bootmem.h> |
4fd78a5f | 26 | #include <linux/vmalloc.h> |
9960e9e8 | 27 | #include <linux/ftrace.h> |
82960b85 | 28 | #include <linux/cpu.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
d3091298 | 30 | #include <linux/kgdb.h> |
1da177e4 LT |
31 | |
32 | #include <asm/head.h> | |
33 | #include <asm/ptrace.h> | |
60063497 | 34 | #include <linux/atomic.h> |
1da177e4 LT |
35 | #include <asm/tlbflush.h> |
36 | #include <asm/mmu_context.h> | |
37 | #include <asm/cpudata.h> | |
27a2ef38 DM |
38 | #include <asm/hvtramp.h> |
39 | #include <asm/io.h> | |
cf3d7c1e | 40 | #include <asm/timer.h> |
59dec13b | 41 | #include <asm/setup.h> |
1da177e4 LT |
42 | |
43 | #include <asm/irq.h> | |
6d24c8dc | 44 | #include <asm/irq_regs.h> |
1da177e4 LT |
45 | #include <asm/page.h> |
46 | #include <asm/pgtable.h> | |
47 | #include <asm/oplib.h> | |
7c0f6ba6 | 48 | #include <linux/uaccess.h> |
1da177e4 LT |
49 | #include <asm/starfire.h> |
50 | #include <asm/tlb.h> | |
56fb4df6 | 51 | #include <asm/sections.h> |
07f8e5f3 | 52 | #include <asm/prom.h> |
5cbc3073 | 53 | #include <asm/mdesc.h> |
4f0234f4 | 54 | #include <asm/ldc.h> |
e0204409 | 55 | #include <asm/hypervisor.h> |
b62818e5 | 56 | #include <asm/pcr.h> |
1da177e4 | 57 | |
280ff974 | 58 | #include "cpumap.h" |
a0c54a21 | 59 | #include "kernel.h" |
280ff974 | 60 | |
d5a7430d | 61 | DEFINE_PER_CPU(cpumask_t, cpu_sibling_map) = CPU_MASK_NONE; |
f78eae2e DM |
62 | cpumask_t cpu_core_map[NR_CPUS] __read_mostly = |
63 | { [0 ... NR_CPUS-1] = CPU_MASK_NONE }; | |
4f0234f4 | 64 | |
acc455cf | 65 | cpumask_t cpu_core_sib_map[NR_CPUS] __read_mostly = { |
66 | [0 ... NR_CPUS-1] = CPU_MASK_NONE }; | |
67 | ||
d624716b AP |
68 | cpumask_t cpu_core_sib_cache_map[NR_CPUS] __read_mostly = { |
69 | [0 ... NR_CPUS - 1] = CPU_MASK_NONE }; | |
70 | ||
d5a7430d | 71 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
4f0234f4 | 72 | EXPORT_SYMBOL(cpu_core_map); |
acc455cf | 73 | EXPORT_SYMBOL(cpu_core_sib_map); |
d624716b | 74 | EXPORT_SYMBOL(cpu_core_sib_cache_map); |
4f0234f4 | 75 | |
1da177e4 | 76 | static cpumask_t smp_commenced_mask; |
1da177e4 | 77 | |
8536e02e VK |
78 | static DEFINE_PER_CPU(bool, poke); |
79 | static bool cpu_poke; | |
80 | ||
1da177e4 LT |
81 | void smp_info(struct seq_file *m) |
82 | { | |
83 | int i; | |
84 | ||
85 | seq_printf(m, "State:\n"); | |
394e3902 AM |
86 | for_each_online_cpu(i) |
87 | seq_printf(m, "CPU%d:\t\tonline\n", i); | |
1da177e4 LT |
88 | } |
89 | ||
90 | void smp_bogo(struct seq_file *m) | |
91 | { | |
92 | int i; | |
93 | ||
394e3902 AM |
94 | for_each_online_cpu(i) |
95 | seq_printf(m, | |
394e3902 | 96 | "Cpu%dClkTck\t: %016lx\n", |
394e3902 | 97 | i, cpu_data(i).clock_tick); |
1da177e4 LT |
98 | } |
99 | ||
112f4871 | 100 | extern void setup_sparc64_timer(void); |
1da177e4 LT |
101 | |
102 | static volatile unsigned long callin_flag = 0; | |
103 | ||
2066aadd | 104 | void smp_callin(void) |
1da177e4 LT |
105 | { |
106 | int cpuid = hard_smp_processor_id(); | |
107 | ||
56fb4df6 | 108 | __local_per_cpu_offset = __per_cpu_offset(cpuid); |
1da177e4 | 109 | |
4a07e646 | 110 | if (tlb_type == hypervisor) |
490384e7 | 111 | sun4v_ktsb_register(); |
481295f9 | 112 | |
56fb4df6 | 113 | __flush_tlb_all(); |
1da177e4 | 114 | |
112f4871 | 115 | setup_sparc64_timer(); |
1da177e4 | 116 | |
816242da DM |
117 | if (cheetah_pcache_forced_on) |
118 | cheetah_enable_pcache(); | |
119 | ||
1da177e4 LT |
120 | callin_flag = 1; |
121 | __asm__ __volatile__("membar #Sync\n\t" | |
122 | "flush %%g6" : : : "memory"); | |
123 | ||
124 | /* Clear this or we will die instantly when we | |
125 | * schedule back to this idler... | |
126 | */ | |
db7d9a4e | 127 | current_thread_info()->new_child = 0; |
1da177e4 LT |
128 | |
129 | /* Attach to the address space of init_task. */ | |
f1f10076 | 130 | mmgrab(&init_mm); |
1da177e4 LT |
131 | current->active_mm = &init_mm; |
132 | ||
82960b85 DM |
133 | /* inform the notifiers about the new cpu */ |
134 | notify_cpu_starting(cpuid); | |
135 | ||
fb1fece5 | 136 | while (!cpumask_test_cpu(cpuid, &smp_commenced_mask)) |
4f07118f | 137 | rmb(); |
1da177e4 | 138 | |
fb1fece5 | 139 | set_cpu_online(cpuid, true); |
5bfb5d69 NP |
140 | |
141 | /* idle thread is expected to have preempt disabled */ | |
142 | preempt_disable(); | |
87fa05ae | 143 | |
ce2521bf KT |
144 | local_irq_enable(); |
145 | ||
fc6d73d6 | 146 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
1da177e4 LT |
147 | } |
148 | ||
149 | void cpu_panic(void) | |
150 | { | |
151 | printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id()); | |
152 | panic("SMP bolixed\n"); | |
153 | } | |
154 | ||
1da177e4 LT |
155 | /* This tick register synchronization scheme is taken entirely from |
156 | * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit. | |
157 | * | |
158 | * The only change I've made is to rework it so that the master | |
159 | * initiates the synchonization instead of the slave. -DaveM | |
160 | */ | |
161 | ||
162 | #define MASTER 0 | |
163 | #define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long)) | |
164 | ||
165 | #define NUM_ROUNDS 64 /* magic value */ | |
166 | #define NUM_ITERS 5 /* likewise */ | |
167 | ||
49b6c01f | 168 | static DEFINE_RAW_SPINLOCK(itc_sync_lock); |
1da177e4 LT |
169 | static unsigned long go[SLAVE + 1]; |
170 | ||
171 | #define DEBUG_TICK_SYNC 0 | |
172 | ||
173 | static inline long get_delta (long *rt, long *master) | |
174 | { | |
175 | unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0; | |
176 | unsigned long tcenter, t0, t1, tm; | |
177 | unsigned long i; | |
178 | ||
179 | for (i = 0; i < NUM_ITERS; i++) { | |
180 | t0 = tick_ops->get_tick(); | |
181 | go[MASTER] = 1; | |
293666b7 | 182 | membar_safe("#StoreLoad"); |
1da177e4 | 183 | while (!(tm = go[SLAVE])) |
4f07118f | 184 | rmb(); |
1da177e4 | 185 | go[SLAVE] = 0; |
4f07118f | 186 | wmb(); |
1da177e4 LT |
187 | t1 = tick_ops->get_tick(); |
188 | ||
189 | if (t1 - t0 < best_t1 - best_t0) | |
190 | best_t0 = t0, best_t1 = t1, best_tm = tm; | |
191 | } | |
192 | ||
193 | *rt = best_t1 - best_t0; | |
194 | *master = best_tm - best_t0; | |
195 | ||
196 | /* average best_t0 and best_t1 without overflow: */ | |
197 | tcenter = (best_t0/2 + best_t1/2); | |
198 | if (best_t0 % 2 + best_t1 % 2 == 2) | |
199 | tcenter++; | |
200 | return tcenter - best_tm; | |
201 | } | |
202 | ||
203 | void smp_synchronize_tick_client(void) | |
204 | { | |
205 | long i, delta, adj, adjust_latency = 0, done = 0; | |
c6fee081 | 206 | unsigned long flags, rt, master_time_stamp; |
1da177e4 LT |
207 | #if DEBUG_TICK_SYNC |
208 | struct { | |
209 | long rt; /* roundtrip time */ | |
210 | long master; /* master's timestamp */ | |
211 | long diff; /* difference between midpoint and master's timestamp */ | |
212 | long lat; /* estimate of itc adjustment latency */ | |
213 | } t[NUM_ROUNDS]; | |
214 | #endif | |
215 | ||
216 | go[MASTER] = 1; | |
217 | ||
218 | while (go[MASTER]) | |
4f07118f | 219 | rmb(); |
1da177e4 LT |
220 | |
221 | local_irq_save(flags); | |
222 | { | |
223 | for (i = 0; i < NUM_ROUNDS; i++) { | |
224 | delta = get_delta(&rt, &master_time_stamp); | |
c6fee081 | 225 | if (delta == 0) |
1da177e4 | 226 | done = 1; /* let's lock on to this... */ |
1da177e4 LT |
227 | |
228 | if (!done) { | |
229 | if (i > 0) { | |
230 | adjust_latency += -delta; | |
231 | adj = -delta + adjust_latency/4; | |
232 | } else | |
233 | adj = -delta; | |
234 | ||
112f4871 | 235 | tick_ops->add_tick(adj); |
1da177e4 LT |
236 | } |
237 | #if DEBUG_TICK_SYNC | |
238 | t[i].rt = rt; | |
239 | t[i].master = master_time_stamp; | |
240 | t[i].diff = delta; | |
241 | t[i].lat = adjust_latency/4; | |
242 | #endif | |
243 | } | |
244 | } | |
245 | local_irq_restore(flags); | |
246 | ||
247 | #if DEBUG_TICK_SYNC | |
248 | for (i = 0; i < NUM_ROUNDS; i++) | |
249 | printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n", | |
250 | t[i].rt, t[i].master, t[i].diff, t[i].lat); | |
251 | #endif | |
252 | ||
519c4d2d JP |
253 | printk(KERN_INFO "CPU %d: synchronized TICK with master CPU " |
254 | "(last diff %ld cycles, maxerr %lu cycles)\n", | |
255 | smp_processor_id(), delta, rt); | |
1da177e4 LT |
256 | } |
257 | ||
258 | static void smp_start_sync_tick_client(int cpu); | |
259 | ||
260 | static void smp_synchronize_one_tick(int cpu) | |
261 | { | |
262 | unsigned long flags, i; | |
263 | ||
264 | go[MASTER] = 0; | |
265 | ||
266 | smp_start_sync_tick_client(cpu); | |
267 | ||
268 | /* wait for client to be ready */ | |
269 | while (!go[MASTER]) | |
4f07118f | 270 | rmb(); |
1da177e4 LT |
271 | |
272 | /* now let the client proceed into his loop */ | |
273 | go[MASTER] = 0; | |
293666b7 | 274 | membar_safe("#StoreLoad"); |
1da177e4 | 275 | |
49b6c01f | 276 | raw_spin_lock_irqsave(&itc_sync_lock, flags); |
1da177e4 LT |
277 | { |
278 | for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) { | |
279 | while (!go[MASTER]) | |
4f07118f | 280 | rmb(); |
1da177e4 | 281 | go[MASTER] = 0; |
4f07118f | 282 | wmb(); |
1da177e4 | 283 | go[SLAVE] = tick_ops->get_tick(); |
293666b7 | 284 | membar_safe("#StoreLoad"); |
1da177e4 LT |
285 | } |
286 | } | |
49b6c01f | 287 | raw_spin_unlock_irqrestore(&itc_sync_lock, flags); |
1da177e4 LT |
288 | } |
289 | ||
b14f5c10 | 290 | #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU) |
2066aadd PG |
291 | static void ldom_startcpu_cpuid(unsigned int cpu, unsigned long thread_reg, |
292 | void **descrp) | |
b14f5c10 DM |
293 | { |
294 | extern unsigned long sparc64_ttable_tl0; | |
295 | extern unsigned long kern_locked_tte_data; | |
b14f5c10 DM |
296 | struct hvtramp_descr *hdesc; |
297 | unsigned long trampoline_ra; | |
298 | struct trap_per_cpu *tb; | |
299 | u64 tte_vaddr, tte_data; | |
300 | unsigned long hv_err; | |
64658743 | 301 | int i; |
b14f5c10 | 302 | |
64658743 DM |
303 | hdesc = kzalloc(sizeof(*hdesc) + |
304 | (sizeof(struct hvtramp_mapping) * | |
305 | num_kernel_image_mappings - 1), | |
306 | GFP_KERNEL); | |
b14f5c10 | 307 | if (!hdesc) { |
27a2ef38 | 308 | printk(KERN_ERR "ldom_startcpu_cpuid: Cannot allocate " |
b14f5c10 DM |
309 | "hvtramp_descr.\n"); |
310 | return; | |
311 | } | |
557fe0e8 | 312 | *descrp = hdesc; |
b14f5c10 DM |
313 | |
314 | hdesc->cpu = cpu; | |
64658743 | 315 | hdesc->num_mappings = num_kernel_image_mappings; |
b14f5c10 DM |
316 | |
317 | tb = &trap_block[cpu]; | |
b14f5c10 DM |
318 | |
319 | hdesc->fault_info_va = (unsigned long) &tb->fault_info; | |
320 | hdesc->fault_info_pa = kimage_addr_to_ra(&tb->fault_info); | |
321 | ||
322 | hdesc->thread_reg = thread_reg; | |
323 | ||
324 | tte_vaddr = (unsigned long) KERNBASE; | |
325 | tte_data = kern_locked_tte_data; | |
326 | ||
64658743 DM |
327 | for (i = 0; i < hdesc->num_mappings; i++) { |
328 | hdesc->maps[i].vaddr = tte_vaddr; | |
329 | hdesc->maps[i].tte = tte_data; | |
b14f5c10 DM |
330 | tte_vaddr += 0x400000; |
331 | tte_data += 0x400000; | |
b14f5c10 DM |
332 | } |
333 | ||
334 | trampoline_ra = kimage_addr_to_ra(hv_cpu_startup); | |
335 | ||
336 | hv_err = sun4v_cpu_start(cpu, trampoline_ra, | |
337 | kimage_addr_to_ra(&sparc64_ttable_tl0), | |
338 | __pa(hdesc)); | |
e0204409 DM |
339 | if (hv_err) |
340 | printk(KERN_ERR "ldom_startcpu_cpuid: sun4v_cpu_start() " | |
341 | "gives error %lu\n", hv_err); | |
b14f5c10 DM |
342 | } |
343 | #endif | |
344 | ||
1da177e4 LT |
345 | extern unsigned long sparc64_cpu_startup; |
346 | ||
347 | /* The OBP cpu startup callback truncates the 3rd arg cookie to | |
348 | * 32-bits (I think) so to be safe we have it read the pointer | |
349 | * contained here so we work on >4GB machines. -DaveM | |
350 | */ | |
351 | static struct thread_info *cpu_new_thread = NULL; | |
352 | ||
2066aadd | 353 | static int smp_boot_one_cpu(unsigned int cpu, struct task_struct *idle) |
1da177e4 LT |
354 | { |
355 | unsigned long entry = | |
356 | (unsigned long)(&sparc64_cpu_startup); | |
357 | unsigned long cookie = | |
358 | (unsigned long)(&cpu_new_thread); | |
557fe0e8 | 359 | void *descr = NULL; |
7890f794 | 360 | int timeout, ret; |
1da177e4 | 361 | |
1da177e4 | 362 | callin_flag = 0; |
f0a2bc7e | 363 | cpu_new_thread = task_thread_info(idle); |
1da177e4 | 364 | |
7890f794 | 365 | if (tlb_type == hypervisor) { |
b14f5c10 | 366 | #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU) |
4f0234f4 DM |
367 | if (ldom_domaining_enabled) |
368 | ldom_startcpu_cpuid(cpu, | |
557fe0e8 DM |
369 | (unsigned long) cpu_new_thread, |
370 | &descr); | |
4f0234f4 DM |
371 | else |
372 | #endif | |
373 | prom_startcpu_cpuid(cpu, entry, cookie); | |
7890f794 | 374 | } else { |
5cbc3073 | 375 | struct device_node *dp = of_find_node_by_cpuid(cpu); |
7890f794 | 376 | |
6016a363 | 377 | prom_startcpu(dp->phandle, entry, cookie); |
7890f794 | 378 | } |
1da177e4 | 379 | |
4f0234f4 | 380 | for (timeout = 0; timeout < 50000; timeout++) { |
1da177e4 LT |
381 | if (callin_flag) |
382 | break; | |
383 | udelay(100); | |
384 | } | |
72aff53f | 385 | |
1da177e4 LT |
386 | if (callin_flag) { |
387 | ret = 0; | |
388 | } else { | |
389 | printk("Processor %d is stuck.\n", cpu); | |
1da177e4 LT |
390 | ret = -ENODEV; |
391 | } | |
392 | cpu_new_thread = NULL; | |
393 | ||
557fe0e8 | 394 | kfree(descr); |
b37d40d1 | 395 | |
1da177e4 LT |
396 | return ret; |
397 | } | |
398 | ||
399 | static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu) | |
400 | { | |
401 | u64 result, target; | |
402 | int stuck, tmp; | |
403 | ||
404 | if (this_is_starfire) { | |
405 | /* map to real upaid */ | |
406 | cpu = (((cpu & 0x3c) << 1) | | |
407 | ((cpu & 0x40) >> 4) | | |
408 | (cpu & 0x3)); | |
409 | } | |
410 | ||
411 | target = (cpu << 14) | 0x70; | |
412 | again: | |
413 | /* Ok, this is the real Spitfire Errata #54. | |
414 | * One must read back from a UDB internal register | |
415 | * after writes to the UDB interrupt dispatch, but | |
416 | * before the membar Sync for that write. | |
417 | * So we use the high UDB control register (ASI 0x7f, | |
418 | * ADDR 0x20) for the dummy read. -DaveM | |
419 | */ | |
420 | tmp = 0x40; | |
421 | __asm__ __volatile__( | |
422 | "wrpr %1, %2, %%pstate\n\t" | |
423 | "stxa %4, [%0] %3\n\t" | |
424 | "stxa %5, [%0+%8] %3\n\t" | |
425 | "add %0, %8, %0\n\t" | |
426 | "stxa %6, [%0+%8] %3\n\t" | |
427 | "membar #Sync\n\t" | |
428 | "stxa %%g0, [%7] %3\n\t" | |
429 | "membar #Sync\n\t" | |
430 | "mov 0x20, %%g1\n\t" | |
431 | "ldxa [%%g1] 0x7f, %%g0\n\t" | |
432 | "membar #Sync" | |
433 | : "=r" (tmp) | |
434 | : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W), | |
435 | "r" (data0), "r" (data1), "r" (data2), "r" (target), | |
436 | "r" (0x10), "0" (tmp) | |
437 | : "g1"); | |
438 | ||
439 | /* NOTE: PSTATE_IE is still clear. */ | |
440 | stuck = 100000; | |
441 | do { | |
442 | __asm__ __volatile__("ldxa [%%g0] %1, %0" | |
443 | : "=r" (result) | |
444 | : "i" (ASI_INTR_DISPATCH_STAT)); | |
445 | if (result == 0) { | |
446 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
447 | : : "r" (pstate)); | |
448 | return; | |
449 | } | |
450 | stuck -= 1; | |
451 | if (stuck == 0) | |
452 | break; | |
453 | } while (result & 0x1); | |
454 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
455 | : : "r" (pstate)); | |
456 | if (stuck == 0) { | |
90181136 | 457 | printk("CPU[%d]: mondo stuckage result[%016llx]\n", |
1da177e4 LT |
458 | smp_processor_id(), result); |
459 | } else { | |
460 | udelay(2); | |
461 | goto again; | |
462 | } | |
463 | } | |
464 | ||
90f7ae8a | 465 | static void spitfire_xcall_deliver(struct trap_per_cpu *tb, int cnt) |
1da177e4 | 466 | { |
90f7ae8a DM |
467 | u64 *mondo, data0, data1, data2; |
468 | u16 *cpu_list; | |
1da177e4 LT |
469 | u64 pstate; |
470 | int i; | |
471 | ||
472 | __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate)); | |
90f7ae8a DM |
473 | cpu_list = __va(tb->cpu_list_pa); |
474 | mondo = __va(tb->cpu_mondo_block_pa); | |
475 | data0 = mondo[0]; | |
476 | data1 = mondo[1]; | |
477 | data2 = mondo[2]; | |
478 | for (i = 0; i < cnt; i++) | |
479 | spitfire_xcall_helper(data0, data1, data2, pstate, cpu_list[i]); | |
1da177e4 LT |
480 | } |
481 | ||
482 | /* Cheetah now allows to send the whole 64-bytes of data in the interrupt | |
483 | * packet, but we have no use for that. However we do take advantage of | |
484 | * the new pipelining feature (ie. dispatch to multiple cpus simultaneously). | |
485 | */ | |
90f7ae8a | 486 | static void cheetah_xcall_deliver(struct trap_per_cpu *tb, int cnt) |
1da177e4 | 487 | { |
22adb358 | 488 | int nack_busy_id, is_jbus, need_more; |
90f7ae8a DM |
489 | u64 *mondo, pstate, ver, busy_mask; |
490 | u16 *cpu_list; | |
1da177e4 | 491 | |
90f7ae8a DM |
492 | cpu_list = __va(tb->cpu_list_pa); |
493 | mondo = __va(tb->cpu_mondo_block_pa); | |
cd5bc89d | 494 | |
1da177e4 LT |
495 | /* Unfortunately, someone at Sun had the brilliant idea to make the |
496 | * busy/nack fields hard-coded by ITID number for this Ultra-III | |
497 | * derivative processor. | |
498 | */ | |
499 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
92704a1c DM |
500 | is_jbus = ((ver >> 32) == __JALAPENO_ID || |
501 | (ver >> 32) == __SERRANO_ID); | |
1da177e4 LT |
502 | |
503 | __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate)); | |
504 | ||
505 | retry: | |
22adb358 | 506 | need_more = 0; |
1da177e4 LT |
507 | __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t" |
508 | : : "r" (pstate), "i" (PSTATE_IE)); | |
509 | ||
510 | /* Setup the dispatch data registers. */ | |
511 | __asm__ __volatile__("stxa %0, [%3] %6\n\t" | |
512 | "stxa %1, [%4] %6\n\t" | |
513 | "stxa %2, [%5] %6\n\t" | |
514 | "membar #Sync\n\t" | |
515 | : /* no outputs */ | |
90f7ae8a | 516 | : "r" (mondo[0]), "r" (mondo[1]), "r" (mondo[2]), |
1da177e4 LT |
517 | "r" (0x40), "r" (0x50), "r" (0x60), |
518 | "i" (ASI_INTR_W)); | |
519 | ||
520 | nack_busy_id = 0; | |
0de56d1a | 521 | busy_mask = 0; |
1da177e4 LT |
522 | { |
523 | int i; | |
524 | ||
90f7ae8a DM |
525 | for (i = 0; i < cnt; i++) { |
526 | u64 target, nr; | |
527 | ||
528 | nr = cpu_list[i]; | |
529 | if (nr == 0xffff) | |
530 | continue; | |
1da177e4 | 531 | |
90f7ae8a | 532 | target = (nr << 14) | 0x70; |
0de56d1a | 533 | if (is_jbus) { |
90f7ae8a | 534 | busy_mask |= (0x1UL << (nr * 2)); |
0de56d1a | 535 | } else { |
1da177e4 | 536 | target |= (nack_busy_id << 24); |
0de56d1a DM |
537 | busy_mask |= (0x1UL << |
538 | (nack_busy_id * 2)); | |
539 | } | |
1da177e4 LT |
540 | __asm__ __volatile__( |
541 | "stxa %%g0, [%0] %1\n\t" | |
542 | "membar #Sync\n\t" | |
543 | : /* no outputs */ | |
544 | : "r" (target), "i" (ASI_INTR_W)); | |
545 | nack_busy_id++; | |
22adb358 DM |
546 | if (nack_busy_id == 32) { |
547 | need_more = 1; | |
548 | break; | |
549 | } | |
1da177e4 LT |
550 | } |
551 | } | |
552 | ||
553 | /* Now, poll for completion. */ | |
554 | { | |
0de56d1a | 555 | u64 dispatch_stat, nack_mask; |
1da177e4 LT |
556 | long stuck; |
557 | ||
558 | stuck = 100000 * nack_busy_id; | |
0de56d1a | 559 | nack_mask = busy_mask << 1; |
1da177e4 LT |
560 | do { |
561 | __asm__ __volatile__("ldxa [%%g0] %1, %0" | |
562 | : "=r" (dispatch_stat) | |
563 | : "i" (ASI_INTR_DISPATCH_STAT)); | |
0de56d1a | 564 | if (!(dispatch_stat & (busy_mask | nack_mask))) { |
1da177e4 LT |
565 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" |
566 | : : "r" (pstate)); | |
22adb358 | 567 | if (unlikely(need_more)) { |
90f7ae8a DM |
568 | int i, this_cnt = 0; |
569 | for (i = 0; i < cnt; i++) { | |
570 | if (cpu_list[i] == 0xffff) | |
571 | continue; | |
572 | cpu_list[i] = 0xffff; | |
573 | this_cnt++; | |
574 | if (this_cnt == 32) | |
22adb358 DM |
575 | break; |
576 | } | |
577 | goto retry; | |
578 | } | |
1da177e4 LT |
579 | return; |
580 | } | |
581 | if (!--stuck) | |
582 | break; | |
0de56d1a | 583 | } while (dispatch_stat & busy_mask); |
1da177e4 LT |
584 | |
585 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
586 | : : "r" (pstate)); | |
587 | ||
0de56d1a | 588 | if (dispatch_stat & busy_mask) { |
1da177e4 LT |
589 | /* Busy bits will not clear, continue instead |
590 | * of freezing up on this cpu. | |
591 | */ | |
90181136 | 592 | printk("CPU[%d]: mondo stuckage result[%016llx]\n", |
1da177e4 LT |
593 | smp_processor_id(), dispatch_stat); |
594 | } else { | |
595 | int i, this_busy_nack = 0; | |
596 | ||
597 | /* Delay some random time with interrupts enabled | |
598 | * to prevent deadlock. | |
599 | */ | |
600 | udelay(2 * nack_busy_id); | |
601 | ||
602 | /* Clear out the mask bits for cpus which did not | |
603 | * NACK us. | |
604 | */ | |
90f7ae8a DM |
605 | for (i = 0; i < cnt; i++) { |
606 | u64 check_mask, nr; | |
607 | ||
608 | nr = cpu_list[i]; | |
609 | if (nr == 0xffff) | |
610 | continue; | |
1da177e4 | 611 | |
92704a1c | 612 | if (is_jbus) |
90f7ae8a | 613 | check_mask = (0x2UL << (2*nr)); |
1da177e4 LT |
614 | else |
615 | check_mask = (0x2UL << | |
616 | this_busy_nack); | |
617 | if ((dispatch_stat & check_mask) == 0) | |
90f7ae8a | 618 | cpu_list[i] = 0xffff; |
1da177e4 | 619 | this_busy_nack += 2; |
22adb358 DM |
620 | if (this_busy_nack == 64) |
621 | break; | |
1da177e4 LT |
622 | } |
623 | ||
624 | goto retry; | |
625 | } | |
626 | } | |
627 | } | |
628 | ||
9d53caec JC |
629 | #define CPU_MONDO_COUNTER(cpuid) (cpu_mondo_counter[cpuid]) |
630 | #define MONDO_USEC_WAIT_MIN 2 | |
631 | #define MONDO_USEC_WAIT_MAX 100 | |
632 | #define MONDO_RETRY_LIMIT 500000 | |
633 | ||
634 | /* Multi-cpu list version. | |
635 | * | |
636 | * Deliver xcalls to 'cnt' number of cpus in 'cpu_list'. | |
637 | * Sometimes not all cpus receive the mondo, requiring us to re-send | |
638 | * the mondo until all cpus have received, or cpus are truly stuck | |
639 | * unable to receive mondo, and we timeout. | |
640 | * Occasionally a target cpu strand is borrowed briefly by hypervisor to | |
641 | * perform guest service, such as PCIe error handling. Consider the | |
642 | * service time, 1 second overall wait is reasonable for 1 cpu. | |
643 | * Here two in-between mondo check wait time are defined: 2 usec for | |
644 | * single cpu quick turn around and up to 100usec for large cpu count. | |
645 | * Deliver mondo to large number of cpus could take longer, we adjusts | |
646 | * the retry count as long as target cpus are making forward progress. | |
647 | */ | |
90f7ae8a | 648 | static void hypervisor_xcall_deliver(struct trap_per_cpu *tb, int cnt) |
a43fe0e7 | 649 | { |
9d53caec JC |
650 | int this_cpu, tot_cpus, prev_sent, i, rem; |
651 | int usec_wait, retries, tot_retries; | |
652 | u16 first_cpu = 0xffff; | |
653 | unsigned long xc_rcvd = 0; | |
c02a5119 | 654 | unsigned long status; |
9d53caec JC |
655 | int ecpuerror_id = 0; |
656 | int enocpu_id = 0; | |
b830ab66 | 657 | u16 *cpu_list; |
9d53caec | 658 | u16 cpu; |
17f34f0e | 659 | |
b830ab66 | 660 | this_cpu = smp_processor_id(); |
b830ab66 | 661 | cpu_list = __va(tb->cpu_list_pa); |
9d53caec JC |
662 | usec_wait = cnt * MONDO_USEC_WAIT_MIN; |
663 | if (usec_wait > MONDO_USEC_WAIT_MAX) | |
664 | usec_wait = MONDO_USEC_WAIT_MAX; | |
665 | retries = tot_retries = 0; | |
666 | tot_cpus = cnt; | |
3cab0c3e | 667 | prev_sent = 0; |
9d53caec | 668 | |
1d2f1f90 | 669 | do { |
9d53caec | 670 | int n_sent, mondo_delivered, target_cpu_busy; |
1d2f1f90 | 671 | |
b830ab66 DM |
672 | status = sun4v_cpu_mondo_send(cnt, |
673 | tb->cpu_list_pa, | |
674 | tb->cpu_mondo_block_pa); | |
675 | ||
676 | /* HV_EOK means all cpus received the xcall, we're done. */ | |
677 | if (likely(status == HV_EOK)) | |
9d53caec JC |
678 | goto xcall_done; |
679 | ||
680 | /* If not these non-fatal errors, panic */ | |
681 | if (unlikely((status != HV_EWOULDBLOCK) && | |
682 | (status != HV_ECPUERROR) && | |
683 | (status != HV_ENOCPU))) | |
684 | goto fatal_errors; | |
b830ab66 | 685 | |
3cab0c3e | 686 | /* First, see if we made any forward progress. |
9d53caec JC |
687 | * |
688 | * Go through the cpu_list, count the target cpus that have | |
689 | * received our mondo (n_sent), and those that did not (rem). | |
690 | * Re-pack cpu_list with the cpus remain to be retried in the | |
691 | * front - this simplifies tracking the truly stalled cpus. | |
3cab0c3e DM |
692 | * |
693 | * The hypervisor indicates successful sends by setting | |
694 | * cpu list entries to the value 0xffff. | |
9d53caec JC |
695 | * |
696 | * EWOULDBLOCK means some target cpus did not receive the | |
697 | * mondo and retry usually helps. | |
698 | * | |
699 | * ECPUERROR means at least one target cpu is in error state, | |
700 | * it's usually safe to skip the faulty cpu and retry. | |
701 | * | |
702 | * ENOCPU means one of the target cpu doesn't belong to the | |
703 | * domain, perhaps offlined which is unexpected, but not | |
704 | * fatal and it's okay to skip the offlined cpu. | |
b830ab66 | 705 | */ |
9d53caec | 706 | rem = 0; |
3cab0c3e | 707 | n_sent = 0; |
b830ab66 | 708 | for (i = 0; i < cnt; i++) { |
9d53caec JC |
709 | cpu = cpu_list[i]; |
710 | if (likely(cpu == 0xffff)) { | |
3cab0c3e | 711 | n_sent++; |
9d53caec JC |
712 | } else if ((status == HV_ECPUERROR) && |
713 | (sun4v_cpu_state(cpu) == HV_CPU_STATE_ERROR)) { | |
714 | ecpuerror_id = cpu + 1; | |
715 | } else if (status == HV_ENOCPU && !cpu_online(cpu)) { | |
716 | enocpu_id = cpu + 1; | |
717 | } else { | |
718 | cpu_list[rem++] = cpu; | |
719 | } | |
1d2f1f90 DM |
720 | } |
721 | ||
9d53caec JC |
722 | /* No cpu remained, we're done. */ |
723 | if (rem == 0) | |
724 | break; | |
3cab0c3e | 725 | |
9d53caec JC |
726 | /* Otherwise, update the cpu count for retry. */ |
727 | cnt = rem; | |
3cab0c3e | 728 | |
9d53caec JC |
729 | /* Record the overall number of mondos received by the |
730 | * first of the remaining cpus. | |
b830ab66 | 731 | */ |
9d53caec JC |
732 | if (first_cpu != cpu_list[0]) { |
733 | first_cpu = cpu_list[0]; | |
734 | xc_rcvd = CPU_MONDO_COUNTER(first_cpu); | |
735 | } | |
b830ab66 | 736 | |
9d53caec JC |
737 | /* Was any mondo delivered successfully? */ |
738 | mondo_delivered = (n_sent > prev_sent); | |
739 | prev_sent = n_sent; | |
b830ab66 | 740 | |
9d53caec JC |
741 | /* or, was any target cpu busy processing other mondos? */ |
742 | target_cpu_busy = (xc_rcvd < CPU_MONDO_COUNTER(first_cpu)); | |
743 | xc_rcvd = CPU_MONDO_COUNTER(first_cpu); | |
b830ab66 | 744 | |
9d53caec JC |
745 | /* Retry count is for no progress. If we're making progress, |
746 | * reset the retry count. | |
3cab0c3e | 747 | */ |
9d53caec JC |
748 | if (likely(mondo_delivered || target_cpu_busy)) { |
749 | tot_retries += retries; | |
750 | retries = 0; | |
751 | } else if (unlikely(retries > MONDO_RETRY_LIMIT)) { | |
752 | goto fatal_mondo_timeout; | |
b830ab66 | 753 | } |
1d2f1f90 | 754 | |
9d53caec JC |
755 | /* Delay a little bit to let other cpus catch up on |
756 | * their cpu mondo queue work. | |
757 | */ | |
758 | if (!mondo_delivered) | |
759 | udelay(usec_wait); | |
b830ab66 | 760 | |
9d53caec JC |
761 | retries++; |
762 | } while (1); | |
b830ab66 | 763 | |
9d53caec JC |
764 | xcall_done: |
765 | if (unlikely(ecpuerror_id > 0)) { | |
766 | pr_crit("CPU[%d]: SUN4V mondo cpu error, target cpu(%d) was in error state\n", | |
767 | this_cpu, ecpuerror_id - 1); | |
768 | } else if (unlikely(enocpu_id > 0)) { | |
769 | pr_crit("CPU[%d]: SUN4V mondo cpu error, target cpu(%d) does not belong to the domain\n", | |
770 | this_cpu, enocpu_id - 1); | |
771 | } | |
b830ab66 DM |
772 | return; |
773 | ||
9d53caec JC |
774 | fatal_errors: |
775 | /* fatal errors include bad alignment, etc */ | |
776 | pr_crit("CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) mondo_block_pa(%lx)\n", | |
777 | this_cpu, tot_cpus, tb->cpu_list_pa, tb->cpu_mondo_block_pa); | |
778 | panic("Unexpected SUN4V mondo error %lu\n", status); | |
779 | ||
b830ab66 | 780 | fatal_mondo_timeout: |
9d53caec JC |
781 | /* some cpus being non-responsive to the cpu mondo */ |
782 | pr_crit("CPU[%d]: SUN4V mondo timeout, cpu(%d) made no forward progress after %d retries. Total target cpus(%d).\n", | |
783 | this_cpu, first_cpu, (tot_retries + retries), tot_cpus); | |
784 | panic("SUN4V mondo timeout panic\n"); | |
1d2f1f90 | 785 | } |
a43fe0e7 | 786 | |
90f7ae8a | 787 | static void (*xcall_deliver_impl)(struct trap_per_cpu *, int); |
deb16999 DM |
788 | |
789 | static void xcall_deliver(u64 data0, u64 data1, u64 data2, const cpumask_t *mask) | |
790 | { | |
90f7ae8a DM |
791 | struct trap_per_cpu *tb; |
792 | int this_cpu, i, cnt; | |
c02a5119 | 793 | unsigned long flags; |
90f7ae8a DM |
794 | u16 *cpu_list; |
795 | u64 *mondo; | |
c02a5119 DM |
796 | |
797 | /* We have to do this whole thing with interrupts fully disabled. | |
798 | * Otherwise if we send an xcall from interrupt context it will | |
799 | * corrupt both our mondo block and cpu list state. | |
800 | * | |
801 | * One consequence of this is that we cannot use timeout mechanisms | |
802 | * that depend upon interrupts being delivered locally. So, for | |
803 | * example, we cannot sample jiffies and expect it to advance. | |
804 | * | |
805 | * Fortunately, udelay() uses %stick/%tick so we can use that. | |
806 | */ | |
807 | local_irq_save(flags); | |
90f7ae8a DM |
808 | |
809 | this_cpu = smp_processor_id(); | |
810 | tb = &trap_block[this_cpu]; | |
811 | ||
812 | mondo = __va(tb->cpu_mondo_block_pa); | |
813 | mondo[0] = data0; | |
814 | mondo[1] = data1; | |
815 | mondo[2] = data2; | |
816 | wmb(); | |
817 | ||
818 | cpu_list = __va(tb->cpu_list_pa); | |
819 | ||
820 | /* Setup the initial cpu list. */ | |
821 | cnt = 0; | |
8e757281 | 822 | for_each_cpu(i, mask) { |
90f7ae8a DM |
823 | if (i == this_cpu || !cpu_online(i)) |
824 | continue; | |
825 | cpu_list[cnt++] = i; | |
826 | } | |
827 | ||
828 | if (cnt) | |
829 | xcall_deliver_impl(tb, cnt); | |
830 | ||
c02a5119 | 831 | local_irq_restore(flags); |
deb16999 | 832 | } |
5e0797e5 | 833 | |
91a4231c DM |
834 | /* Send cross call to all processors mentioned in MASK_P |
835 | * except self. Really, there are only two cases currently, | |
fb1fece5 | 836 | * "cpu_online_mask" and "mm_cpumask(mm)". |
1da177e4 | 837 | */ |
ae583885 | 838 | static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, const cpumask_t *mask) |
1da177e4 LT |
839 | { |
840 | u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff)); | |
1da177e4 | 841 | |
ae583885 DM |
842 | xcall_deliver(data0, data1, data2, mask); |
843 | } | |
1da177e4 | 844 | |
ae583885 DM |
845 | /* Send cross call to all processors except self. */ |
846 | static void smp_cross_call(unsigned long *func, u32 ctx, u64 data1, u64 data2) | |
847 | { | |
fb1fece5 | 848 | smp_cross_call_masked(func, ctx, data1, data2, cpu_online_mask); |
1da177e4 LT |
849 | } |
850 | ||
851 | extern unsigned long xcall_sync_tick; | |
852 | ||
853 | static void smp_start_sync_tick_client(int cpu) | |
854 | { | |
24445a4a | 855 | xcall_deliver((u64) &xcall_sync_tick, 0, 0, |
fb1fece5 | 856 | cpumask_of(cpu)); |
1da177e4 LT |
857 | } |
858 | ||
1da177e4 LT |
859 | extern unsigned long xcall_call_function; |
860 | ||
f46df02a | 861 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
1da177e4 | 862 | { |
f46df02a | 863 | xcall_deliver((u64) &xcall_call_function, 0, 0, mask); |
d172ad18 | 864 | } |
1da177e4 | 865 | |
d172ad18 | 866 | extern unsigned long xcall_call_function_single; |
1da177e4 | 867 | |
d172ad18 DM |
868 | void arch_send_call_function_single_ipi(int cpu) |
869 | { | |
19926630 | 870 | xcall_deliver((u64) &xcall_call_function_single, 0, 0, |
fb1fece5 | 871 | cpumask_of(cpu)); |
1da177e4 LT |
872 | } |
873 | ||
9960e9e8 | 874 | void __irq_entry smp_call_function_client(int irq, struct pt_regs *regs) |
1da177e4 | 875 | { |
d172ad18 | 876 | clear_softint(1 << irq); |
ab5c7809 | 877 | irq_enter(); |
d172ad18 | 878 | generic_smp_call_function_interrupt(); |
ab5c7809 | 879 | irq_exit(); |
d172ad18 | 880 | } |
1da177e4 | 881 | |
9960e9e8 | 882 | void __irq_entry smp_call_function_single_client(int irq, struct pt_regs *regs) |
d172ad18 | 883 | { |
1da177e4 | 884 | clear_softint(1 << irq); |
ab5c7809 | 885 | irq_enter(); |
d172ad18 | 886 | generic_smp_call_function_single_interrupt(); |
ab5c7809 | 887 | irq_exit(); |
1da177e4 LT |
888 | } |
889 | ||
bd40791e DM |
890 | static void tsb_sync(void *info) |
891 | { | |
6f25f398 | 892 | struct trap_per_cpu *tp = &trap_block[raw_smp_processor_id()]; |
bd40791e DM |
893 | struct mm_struct *mm = info; |
894 | ||
42b2aa86 | 895 | /* It is not valid to test "current->active_mm == mm" here. |
6f25f398 DM |
896 | * |
897 | * The value of "current" is not changed atomically with | |
898 | * switch_mm(). But that's OK, we just need to check the | |
899 | * current cpu's trap block PGD physical address. | |
900 | */ | |
901 | if (tp->pgd_paddr == __pa(mm->pgd)) | |
bd40791e DM |
902 | tsb_context_switch(mm); |
903 | } | |
904 | ||
905 | void smp_tsb_sync(struct mm_struct *mm) | |
906 | { | |
81f1adf0 | 907 | smp_call_function_many(mm_cpumask(mm), tsb_sync, mm, 1); |
bd40791e DM |
908 | } |
909 | ||
1da177e4 | 910 | extern unsigned long xcall_flush_tlb_mm; |
f36391d2 | 911 | extern unsigned long xcall_flush_tlb_page; |
1da177e4 | 912 | extern unsigned long xcall_flush_tlb_kernel_range; |
93dae5b7 | 913 | extern unsigned long xcall_fetch_glob_regs; |
916ca14a DM |
914 | extern unsigned long xcall_fetch_glob_pmu; |
915 | extern unsigned long xcall_fetch_glob_pmu_n4; | |
1da177e4 | 916 | extern unsigned long xcall_receive_signal; |
ee29074d | 917 | extern unsigned long xcall_new_mmu_context_version; |
e2fdd7fd DM |
918 | #ifdef CONFIG_KGDB |
919 | extern unsigned long xcall_kgdb_capture; | |
920 | #endif | |
1da177e4 LT |
921 | |
922 | #ifdef DCACHE_ALIASING_POSSIBLE | |
923 | extern unsigned long xcall_flush_dcache_page_cheetah; | |
924 | #endif | |
925 | extern unsigned long xcall_flush_dcache_page_spitfire; | |
926 | ||
d979f179 | 927 | static inline void __local_flush_dcache_page(struct page *page) |
1da177e4 LT |
928 | { |
929 | #ifdef DCACHE_ALIASING_POSSIBLE | |
930 | __flush_dcache_page(page_address(page), | |
931 | ((tlb_type == spitfire) && | |
932 | page_mapping(page) != NULL)); | |
933 | #else | |
934 | if (page_mapping(page) != NULL && | |
935 | tlb_type == spitfire) | |
936 | __flush_icache_page(__pa(page_address(page))); | |
937 | #endif | |
938 | } | |
939 | ||
940 | void smp_flush_dcache_page_impl(struct page *page, int cpu) | |
941 | { | |
a43fe0e7 DM |
942 | int this_cpu; |
943 | ||
944 | if (tlb_type == hypervisor) | |
945 | return; | |
1da177e4 LT |
946 | |
947 | #ifdef CONFIG_DEBUG_DCFLUSH | |
948 | atomic_inc(&dcpage_flushes); | |
949 | #endif | |
a43fe0e7 DM |
950 | |
951 | this_cpu = get_cpu(); | |
952 | ||
1da177e4 LT |
953 | if (cpu == this_cpu) { |
954 | __local_flush_dcache_page(page); | |
955 | } else if (cpu_online(cpu)) { | |
956 | void *pg_addr = page_address(page); | |
622824db | 957 | u64 data0 = 0; |
1da177e4 LT |
958 | |
959 | if (tlb_type == spitfire) { | |
622824db | 960 | data0 = ((u64)&xcall_flush_dcache_page_spitfire); |
1da177e4 LT |
961 | if (page_mapping(page) != NULL) |
962 | data0 |= ((u64)1 << 32); | |
a43fe0e7 | 963 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
1da177e4 | 964 | #ifdef DCACHE_ALIASING_POSSIBLE |
622824db | 965 | data0 = ((u64)&xcall_flush_dcache_page_cheetah); |
1da177e4 LT |
966 | #endif |
967 | } | |
622824db DM |
968 | if (data0) { |
969 | xcall_deliver(data0, __pa(pg_addr), | |
fb1fece5 | 970 | (u64) pg_addr, cpumask_of(cpu)); |
1da177e4 | 971 | #ifdef CONFIG_DEBUG_DCFLUSH |
622824db | 972 | atomic_inc(&dcpage_flushes_xcall); |
1da177e4 | 973 | #endif |
622824db | 974 | } |
1da177e4 LT |
975 | } |
976 | ||
977 | put_cpu(); | |
978 | } | |
979 | ||
980 | void flush_dcache_page_all(struct mm_struct *mm, struct page *page) | |
981 | { | |
622824db | 982 | void *pg_addr; |
622824db | 983 | u64 data0; |
a43fe0e7 DM |
984 | |
985 | if (tlb_type == hypervisor) | |
986 | return; | |
987 | ||
c6fee081 | 988 | preempt_disable(); |
1da177e4 | 989 | |
1da177e4 LT |
990 | #ifdef CONFIG_DEBUG_DCFLUSH |
991 | atomic_inc(&dcpage_flushes); | |
992 | #endif | |
622824db DM |
993 | data0 = 0; |
994 | pg_addr = page_address(page); | |
1da177e4 LT |
995 | if (tlb_type == spitfire) { |
996 | data0 = ((u64)&xcall_flush_dcache_page_spitfire); | |
997 | if (page_mapping(page) != NULL) | |
998 | data0 |= ((u64)1 << 32); | |
a43fe0e7 | 999 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
1da177e4 LT |
1000 | #ifdef DCACHE_ALIASING_POSSIBLE |
1001 | data0 = ((u64)&xcall_flush_dcache_page_cheetah); | |
1da177e4 LT |
1002 | #endif |
1003 | } | |
622824db DM |
1004 | if (data0) { |
1005 | xcall_deliver(data0, __pa(pg_addr), | |
fb1fece5 | 1006 | (u64) pg_addr, cpu_online_mask); |
1da177e4 | 1007 | #ifdef CONFIG_DEBUG_DCFLUSH |
622824db | 1008 | atomic_inc(&dcpage_flushes_xcall); |
1da177e4 | 1009 | #endif |
622824db | 1010 | } |
1da177e4 LT |
1011 | __local_flush_dcache_page(page); |
1012 | ||
c6fee081 | 1013 | preempt_enable(); |
1da177e4 LT |
1014 | } |
1015 | ||
e2fdd7fd DM |
1016 | #ifdef CONFIG_KGDB |
1017 | void kgdb_roundup_cpus(unsigned long flags) | |
1018 | { | |
1019 | smp_cross_call(&xcall_kgdb_capture, 0, 0, 0); | |
1020 | } | |
1021 | #endif | |
1022 | ||
93dae5b7 DM |
1023 | void smp_fetch_global_regs(void) |
1024 | { | |
1025 | smp_cross_call(&xcall_fetch_glob_regs, 0, 0, 0); | |
1026 | } | |
93dae5b7 | 1027 | |
916ca14a DM |
1028 | void smp_fetch_global_pmu(void) |
1029 | { | |
1030 | if (tlb_type == hypervisor && | |
1031 | sun4v_chip_type >= SUN4V_CHIP_NIAGARA4) | |
1032 | smp_cross_call(&xcall_fetch_glob_pmu_n4, 0, 0, 0); | |
1033 | else | |
1034 | smp_cross_call(&xcall_fetch_glob_pmu, 0, 0, 0); | |
1035 | } | |
1036 | ||
1da177e4 LT |
1037 | /* We know that the window frames of the user have been flushed |
1038 | * to the stack before we get here because all callers of us | |
1039 | * are flush_tlb_*() routines, and these run after flush_cache_*() | |
1040 | * which performs the flushw. | |
1041 | * | |
1042 | * The SMP TLB coherency scheme we use works as follows: | |
1043 | * | |
1044 | * 1) mm->cpu_vm_mask is a bit mask of which cpus an address | |
1045 | * space has (potentially) executed on, this is the heuristic | |
1046 | * we use to avoid doing cross calls. | |
1047 | * | |
1048 | * Also, for flushing from kswapd and also for clones, we | |
1049 | * use cpu_vm_mask as the list of cpus to make run the TLB. | |
1050 | * | |
1051 | * 2) TLB context numbers are shared globally across all processors | |
1052 | * in the system, this allows us to play several games to avoid | |
1053 | * cross calls. | |
1054 | * | |
1055 | * One invariant is that when a cpu switches to a process, and | |
1056 | * that processes tsk->active_mm->cpu_vm_mask does not have the | |
1057 | * current cpu's bit set, that tlb context is flushed locally. | |
1058 | * | |
1059 | * If the address space is non-shared (ie. mm->count == 1) we avoid | |
1060 | * cross calls when we want to flush the currently running process's | |
1061 | * tlb state. This is done by clearing all cpu bits except the current | |
f9384d41 | 1062 | * processor's in current->mm->cpu_vm_mask and performing the |
1da177e4 LT |
1063 | * flush locally only. This will force any subsequent cpus which run |
1064 | * this task to flush the context from the local tlb if the process | |
1065 | * migrates to another cpu (again). | |
1066 | * | |
1067 | * 3) For shared address spaces (threads) and swapping we bite the | |
1068 | * bullet for most cases and perform the cross call (but only to | |
1069 | * the cpus listed in cpu_vm_mask). | |
1070 | * | |
1071 | * The performance gain from "optimizing" away the cross call for threads is | |
1072 | * questionable (in theory the big win for threads is the massive sharing of | |
1073 | * address space state across processors). | |
1074 | */ | |
62dbec78 DM |
1075 | |
1076 | /* This currently is only used by the hugetlb arch pre-fault | |
1077 | * hook on UltraSPARC-III+ and later when changing the pagesize | |
1078 | * bits of the context register for an address space. | |
1079 | */ | |
1da177e4 LT |
1080 | void smp_flush_tlb_mm(struct mm_struct *mm) |
1081 | { | |
62dbec78 DM |
1082 | u32 ctx = CTX_HWBITS(mm->context); |
1083 | int cpu = get_cpu(); | |
1da177e4 | 1084 | |
62dbec78 | 1085 | if (atomic_read(&mm->mm_users) == 1) { |
81f1adf0 | 1086 | cpumask_copy(mm_cpumask(mm), cpumask_of(cpu)); |
62dbec78 DM |
1087 | goto local_flush_and_out; |
1088 | } | |
1da177e4 | 1089 | |
62dbec78 DM |
1090 | smp_cross_call_masked(&xcall_flush_tlb_mm, |
1091 | ctx, 0, 0, | |
81f1adf0 | 1092 | mm_cpumask(mm)); |
1da177e4 | 1093 | |
62dbec78 DM |
1094 | local_flush_and_out: |
1095 | __flush_tlb_mm(ctx, SECONDARY_CONTEXT); | |
1da177e4 | 1096 | |
62dbec78 | 1097 | put_cpu(); |
1da177e4 LT |
1098 | } |
1099 | ||
f36391d2 DM |
1100 | struct tlb_pending_info { |
1101 | unsigned long ctx; | |
1102 | unsigned long nr; | |
1103 | unsigned long *vaddrs; | |
1104 | }; | |
1105 | ||
1106 | static void tlb_pending_func(void *info) | |
1107 | { | |
1108 | struct tlb_pending_info *t = info; | |
1109 | ||
1110 | __flush_tlb_pending(t->ctx, t->nr, t->vaddrs); | |
1111 | } | |
1112 | ||
1da177e4 LT |
1113 | void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs) |
1114 | { | |
1115 | u32 ctx = CTX_HWBITS(mm->context); | |
f36391d2 | 1116 | struct tlb_pending_info info; |
1da177e4 LT |
1117 | int cpu = get_cpu(); |
1118 | ||
f36391d2 DM |
1119 | info.ctx = ctx; |
1120 | info.nr = nr; | |
1121 | info.vaddrs = vaddrs; | |
1122 | ||
f9384d41 | 1123 | if (mm == current->mm && atomic_read(&mm->mm_users) == 1) |
81f1adf0 | 1124 | cpumask_copy(mm_cpumask(mm), cpumask_of(cpu)); |
dedeb002 | 1125 | else |
f36391d2 DM |
1126 | smp_call_function_many(mm_cpumask(mm), tlb_pending_func, |
1127 | &info, 1); | |
1da177e4 | 1128 | |
1da177e4 LT |
1129 | __flush_tlb_pending(ctx, nr, vaddrs); |
1130 | ||
1131 | put_cpu(); | |
1132 | } | |
1133 | ||
f36391d2 DM |
1134 | void smp_flush_tlb_page(struct mm_struct *mm, unsigned long vaddr) |
1135 | { | |
1136 | unsigned long context = CTX_HWBITS(mm->context); | |
1137 | int cpu = get_cpu(); | |
1138 | ||
1139 | if (mm == current->mm && atomic_read(&mm->mm_users) == 1) | |
1140 | cpumask_copy(mm_cpumask(mm), cpumask_of(cpu)); | |
1141 | else | |
1142 | smp_cross_call_masked(&xcall_flush_tlb_page, | |
1143 | context, vaddr, 0, | |
1144 | mm_cpumask(mm)); | |
1145 | __flush_tlb_page(context, vaddr); | |
1146 | ||
1147 | put_cpu(); | |
1148 | } | |
1149 | ||
1da177e4 LT |
1150 | void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end) |
1151 | { | |
1152 | start &= PAGE_MASK; | |
1153 | end = PAGE_ALIGN(end); | |
1154 | if (start != end) { | |
1155 | smp_cross_call(&xcall_flush_tlb_kernel_range, | |
1156 | 0, start, end); | |
1157 | ||
1158 | __flush_tlb_kernel_range(start, end); | |
1159 | } | |
1160 | } | |
1161 | ||
1162 | /* CPU capture. */ | |
1163 | /* #define CAPTURE_DEBUG */ | |
1164 | extern unsigned long xcall_capture; | |
1165 | ||
1166 | static atomic_t smp_capture_depth = ATOMIC_INIT(0); | |
1167 | static atomic_t smp_capture_registry = ATOMIC_INIT(0); | |
1168 | static unsigned long penguins_are_doing_time; | |
1169 | ||
1170 | void smp_capture(void) | |
1171 | { | |
4f3316c2 | 1172 | int result = atomic_add_return(1, &smp_capture_depth); |
1da177e4 LT |
1173 | |
1174 | if (result == 1) { | |
1175 | int ncpus = num_online_cpus(); | |
1176 | ||
1177 | #ifdef CAPTURE_DEBUG | |
1178 | printk("CPU[%d]: Sending penguins to jail...", | |
1179 | smp_processor_id()); | |
1180 | #endif | |
1181 | penguins_are_doing_time = 1; | |
1da177e4 LT |
1182 | atomic_inc(&smp_capture_registry); |
1183 | smp_cross_call(&xcall_capture, 0, 0, 0); | |
1184 | while (atomic_read(&smp_capture_registry) != ncpus) | |
4f07118f | 1185 | rmb(); |
1da177e4 LT |
1186 | #ifdef CAPTURE_DEBUG |
1187 | printk("done\n"); | |
1188 | #endif | |
1189 | } | |
1190 | } | |
1191 | ||
1192 | void smp_release(void) | |
1193 | { | |
1194 | if (atomic_dec_and_test(&smp_capture_depth)) { | |
1195 | #ifdef CAPTURE_DEBUG | |
1196 | printk("CPU[%d]: Giving pardon to " | |
1197 | "imprisoned penguins\n", | |
1198 | smp_processor_id()); | |
1199 | #endif | |
1200 | penguins_are_doing_time = 0; | |
293666b7 | 1201 | membar_safe("#StoreLoad"); |
1da177e4 LT |
1202 | atomic_dec(&smp_capture_registry); |
1203 | } | |
1204 | } | |
1205 | ||
b4f4372f DM |
1206 | /* Imprisoned penguins run with %pil == PIL_NORMAL_MAX, but PSTATE_IE |
1207 | * set, so they can service tlb flush xcalls... | |
1da177e4 LT |
1208 | */ |
1209 | extern void prom_world(int); | |
96c6e0d8 | 1210 | |
9960e9e8 | 1211 | void __irq_entry smp_penguin_jailcell(int irq, struct pt_regs *regs) |
1da177e4 | 1212 | { |
1da177e4 LT |
1213 | clear_softint(1 << irq); |
1214 | ||
1215 | preempt_disable(); | |
1216 | ||
1217 | __asm__ __volatile__("flushw"); | |
1da177e4 LT |
1218 | prom_world(1); |
1219 | atomic_inc(&smp_capture_registry); | |
293666b7 | 1220 | membar_safe("#StoreLoad"); |
1da177e4 | 1221 | while (penguins_are_doing_time) |
4f07118f | 1222 | rmb(); |
1da177e4 LT |
1223 | atomic_dec(&smp_capture_registry); |
1224 | prom_world(0); | |
1225 | ||
1226 | preempt_enable(); | |
1227 | } | |
1228 | ||
1da177e4 | 1229 | /* /proc/profile writes can call this, don't __init it please. */ |
1da177e4 LT |
1230 | int setup_profiling_timer(unsigned int multiplier) |
1231 | { | |
777a4475 | 1232 | return -EINVAL; |
1da177e4 LT |
1233 | } |
1234 | ||
1235 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
1236 | { | |
1da177e4 LT |
1237 | } |
1238 | ||
7c9503b8 | 1239 | void smp_prepare_boot_cpu(void) |
7abea921 | 1240 | { |
7abea921 DM |
1241 | } |
1242 | ||
5e0797e5 DM |
1243 | void __init smp_setup_processor_id(void) |
1244 | { | |
1245 | if (tlb_type == spitfire) | |
deb16999 | 1246 | xcall_deliver_impl = spitfire_xcall_deliver; |
5e0797e5 | 1247 | else if (tlb_type == cheetah || tlb_type == cheetah_plus) |
deb16999 | 1248 | xcall_deliver_impl = cheetah_xcall_deliver; |
5e0797e5 | 1249 | else |
deb16999 | 1250 | xcall_deliver_impl = hypervisor_xcall_deliver; |
5e0797e5 DM |
1251 | } |
1252 | ||
9b2f753e AP |
1253 | void __init smp_fill_in_cpu_possible_map(void) |
1254 | { | |
1255 | int possible_cpus = num_possible_cpus(); | |
1256 | int i; | |
1257 | ||
1258 | if (possible_cpus > nr_cpu_ids) | |
1259 | possible_cpus = nr_cpu_ids; | |
1260 | ||
1261 | for (i = 0; i < possible_cpus; i++) | |
1262 | set_cpu_possible(i, true); | |
1263 | for (; i < NR_CPUS; i++) | |
1264 | set_cpu_possible(i, false); | |
1265 | } | |
1266 | ||
7c9503b8 | 1267 | void smp_fill_in_sib_core_maps(void) |
1da177e4 | 1268 | { |
5cbc3073 DM |
1269 | unsigned int i; |
1270 | ||
e0204409 | 1271 | for_each_present_cpu(i) { |
5cbc3073 DM |
1272 | unsigned int j; |
1273 | ||
fb1fece5 | 1274 | cpumask_clear(&cpu_core_map[i]); |
5cbc3073 | 1275 | if (cpu_data(i).core_id == 0) { |
fb1fece5 | 1276 | cpumask_set_cpu(i, &cpu_core_map[i]); |
5cbc3073 DM |
1277 | continue; |
1278 | } | |
1279 | ||
e0204409 | 1280 | for_each_present_cpu(j) { |
5cbc3073 DM |
1281 | if (cpu_data(i).core_id == |
1282 | cpu_data(j).core_id) | |
fb1fece5 | 1283 | cpumask_set_cpu(j, &cpu_core_map[i]); |
f78eae2e DM |
1284 | } |
1285 | } | |
1286 | ||
acc455cf | 1287 | for_each_present_cpu(i) { |
1288 | unsigned int j; | |
1289 | ||
1290 | for_each_present_cpu(j) { | |
d624716b AP |
1291 | if (cpu_data(i).max_cache_id == |
1292 | cpu_data(j).max_cache_id) | |
1293 | cpumask_set_cpu(j, &cpu_core_sib_cache_map[i]); | |
1294 | ||
acc455cf | 1295 | if (cpu_data(i).sock_id == cpu_data(j).sock_id) |
1296 | cpumask_set_cpu(j, &cpu_core_sib_map[i]); | |
1297 | } | |
1298 | } | |
1299 | ||
e0204409 | 1300 | for_each_present_cpu(i) { |
f78eae2e DM |
1301 | unsigned int j; |
1302 | ||
fb1fece5 | 1303 | cpumask_clear(&per_cpu(cpu_sibling_map, i)); |
f78eae2e | 1304 | if (cpu_data(i).proc_id == -1) { |
fb1fece5 | 1305 | cpumask_set_cpu(i, &per_cpu(cpu_sibling_map, i)); |
f78eae2e DM |
1306 | continue; |
1307 | } | |
1308 | ||
e0204409 | 1309 | for_each_present_cpu(j) { |
f78eae2e DM |
1310 | if (cpu_data(i).proc_id == |
1311 | cpu_data(j).proc_id) | |
fb1fece5 | 1312 | cpumask_set_cpu(j, &per_cpu(cpu_sibling_map, i)); |
5cbc3073 DM |
1313 | } |
1314 | } | |
1da177e4 LT |
1315 | } |
1316 | ||
2066aadd | 1317 | int __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 1318 | { |
f0a2bc7e | 1319 | int ret = smp_boot_one_cpu(cpu, tidle); |
1da177e4 LT |
1320 | |
1321 | if (!ret) { | |
fb1fece5 KM |
1322 | cpumask_set_cpu(cpu, &smp_commenced_mask); |
1323 | while (!cpu_online(cpu)) | |
1da177e4 | 1324 | mb(); |
fb1fece5 | 1325 | if (!cpu_online(cpu)) { |
1da177e4 LT |
1326 | ret = -ENODEV; |
1327 | } else { | |
02fead75 DM |
1328 | /* On SUN4V, writes to %tick and %stick are |
1329 | * not allowed. | |
1330 | */ | |
1331 | if (tlb_type != hypervisor) | |
1332 | smp_synchronize_one_tick(cpu); | |
1da177e4 LT |
1333 | } |
1334 | } | |
1335 | return ret; | |
1336 | } | |
1337 | ||
4f0234f4 | 1338 | #ifdef CONFIG_HOTPLUG_CPU |
e0204409 DM |
1339 | void cpu_play_dead(void) |
1340 | { | |
1341 | int cpu = smp_processor_id(); | |
1342 | unsigned long pstate; | |
1343 | ||
1344 | idle_task_exit(); | |
1345 | ||
1346 | if (tlb_type == hypervisor) { | |
1347 | struct trap_per_cpu *tb = &trap_block[cpu]; | |
1348 | ||
1349 | sun4v_cpu_qconf(HV_CPU_QUEUE_CPU_MONDO, | |
1350 | tb->cpu_mondo_pa, 0); | |
1351 | sun4v_cpu_qconf(HV_CPU_QUEUE_DEVICE_MONDO, | |
1352 | tb->dev_mondo_pa, 0); | |
1353 | sun4v_cpu_qconf(HV_CPU_QUEUE_RES_ERROR, | |
1354 | tb->resum_mondo_pa, 0); | |
1355 | sun4v_cpu_qconf(HV_CPU_QUEUE_NONRES_ERROR, | |
1356 | tb->nonresum_mondo_pa, 0); | |
1357 | } | |
1358 | ||
fb1fece5 | 1359 | cpumask_clear_cpu(cpu, &smp_commenced_mask); |
e0204409 DM |
1360 | membar_safe("#Sync"); |
1361 | ||
1362 | local_irq_disable(); | |
1363 | ||
1364 | __asm__ __volatile__( | |
1365 | "rdpr %%pstate, %0\n\t" | |
1366 | "wrpr %0, %1, %%pstate" | |
1367 | : "=r" (pstate) | |
1368 | : "i" (PSTATE_IE)); | |
1369 | ||
1370 | while (1) | |
1371 | barrier(); | |
1372 | } | |
1373 | ||
4f0234f4 DM |
1374 | int __cpu_disable(void) |
1375 | { | |
e0204409 DM |
1376 | int cpu = smp_processor_id(); |
1377 | cpuinfo_sparc *c; | |
1378 | int i; | |
1379 | ||
fb1fece5 KM |
1380 | for_each_cpu(i, &cpu_core_map[cpu]) |
1381 | cpumask_clear_cpu(cpu, &cpu_core_map[i]); | |
1382 | cpumask_clear(&cpu_core_map[cpu]); | |
e0204409 | 1383 | |
fb1fece5 KM |
1384 | for_each_cpu(i, &per_cpu(cpu_sibling_map, cpu)) |
1385 | cpumask_clear_cpu(cpu, &per_cpu(cpu_sibling_map, i)); | |
1386 | cpumask_clear(&per_cpu(cpu_sibling_map, cpu)); | |
e0204409 DM |
1387 | |
1388 | c = &cpu_data(cpu); | |
1389 | ||
1390 | c->core_id = 0; | |
1391 | c->proc_id = -1; | |
1392 | ||
e0204409 DM |
1393 | smp_wmb(); |
1394 | ||
1395 | /* Make sure no interrupts point to this cpu. */ | |
1396 | fixup_irqs(); | |
1397 | ||
1398 | local_irq_enable(); | |
1399 | mdelay(1); | |
1400 | local_irq_disable(); | |
1401 | ||
fb1fece5 | 1402 | set_cpu_online(cpu, false); |
4d084617 | 1403 | |
280ff974 HP |
1404 | cpu_map_rebuild(); |
1405 | ||
e0204409 | 1406 | return 0; |
4f0234f4 DM |
1407 | } |
1408 | ||
1409 | void __cpu_die(unsigned int cpu) | |
1410 | { | |
e0204409 DM |
1411 | int i; |
1412 | ||
1413 | for (i = 0; i < 100; i++) { | |
1414 | smp_rmb(); | |
fb1fece5 | 1415 | if (!cpumask_test_cpu(cpu, &smp_commenced_mask)) |
e0204409 DM |
1416 | break; |
1417 | msleep(100); | |
1418 | } | |
fb1fece5 | 1419 | if (cpumask_test_cpu(cpu, &smp_commenced_mask)) { |
e0204409 DM |
1420 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); |
1421 | } else { | |
1422 | #if defined(CONFIG_SUN_LDOMS) | |
1423 | unsigned long hv_err; | |
1424 | int limit = 100; | |
1425 | ||
1426 | do { | |
1427 | hv_err = sun4v_cpu_stop(cpu); | |
1428 | if (hv_err == HV_EOK) { | |
fb1fece5 | 1429 | set_cpu_present(cpu, false); |
e0204409 DM |
1430 | break; |
1431 | } | |
1432 | } while (--limit > 0); | |
1433 | if (limit <= 0) { | |
1434 | printk(KERN_ERR "sun4v_cpu_stop() fails err=%lu\n", | |
1435 | hv_err); | |
1436 | } | |
1437 | #endif | |
1438 | } | |
4f0234f4 DM |
1439 | } |
1440 | #endif | |
1441 | ||
1da177e4 LT |
1442 | void __init smp_cpus_done(unsigned int max_cpus) |
1443 | { | |
1da177e4 LT |
1444 | } |
1445 | ||
8536e02e VK |
1446 | static void send_cpu_ipi(int cpu) |
1447 | { | |
1448 | xcall_deliver((u64) &xcall_receive_signal, | |
1449 | 0, 0, cpumask_of(cpu)); | |
1450 | } | |
1451 | ||
1452 | void scheduler_poke(void) | |
1453 | { | |
1454 | if (!cpu_poke) | |
1455 | return; | |
1456 | ||
1457 | if (!__this_cpu_read(poke)) | |
1458 | return; | |
1459 | ||
1460 | __this_cpu_write(poke, false); | |
1461 | set_softint(1 << PIL_SMP_RECEIVE_SIGNAL); | |
1462 | } | |
1463 | ||
1464 | static unsigned long send_cpu_poke(int cpu) | |
1465 | { | |
1466 | unsigned long hv_err; | |
1467 | ||
1468 | per_cpu(poke, cpu) = true; | |
1469 | hv_err = sun4v_cpu_poke(cpu); | |
1470 | if (hv_err != HV_EOK) { | |
1471 | per_cpu(poke, cpu) = false; | |
1472 | pr_err_ratelimited("%s: sun4v_cpu_poke() fails err=%lu\n", | |
1473 | __func__, hv_err); | |
1474 | } | |
1475 | ||
1476 | return hv_err; | |
1477 | } | |
1478 | ||
1da177e4 LT |
1479 | void smp_send_reschedule(int cpu) |
1480 | { | |
1a36265b KT |
1481 | if (cpu == smp_processor_id()) { |
1482 | WARN_ON_ONCE(preemptible()); | |
1483 | set_softint(1 << PIL_SMP_RECEIVE_SIGNAL); | |
8536e02e VK |
1484 | return; |
1485 | } | |
1486 | ||
1487 | /* Use cpu poke to resume idle cpu if supported. */ | |
1488 | if (cpu_poke && idle_cpu(cpu)) { | |
1489 | unsigned long ret; | |
1490 | ||
1491 | ret = send_cpu_poke(cpu); | |
1492 | if (ret == HV_EOK) | |
1493 | return; | |
1a36265b | 1494 | } |
8536e02e VK |
1495 | |
1496 | /* Use IPI in following cases: | |
1497 | * - cpu poke not supported | |
1498 | * - cpu not idle | |
1499 | * - send_cpu_poke() returns with error | |
1500 | */ | |
1501 | send_cpu_ipi(cpu); | |
1502 | } | |
1503 | ||
1504 | void smp_init_cpu_poke(void) | |
1505 | { | |
1506 | unsigned long major; | |
1507 | unsigned long minor; | |
1508 | int ret; | |
1509 | ||
1510 | if (tlb_type != hypervisor) | |
1511 | return; | |
1512 | ||
1513 | ret = sun4v_hvapi_get(HV_GRP_CORE, &major, &minor); | |
1514 | if (ret) { | |
1515 | pr_debug("HV_GRP_CORE is not registered\n"); | |
1516 | return; | |
1517 | } | |
1518 | ||
1519 | if (major == 1 && minor >= 6) { | |
1520 | /* CPU POKE is registered. */ | |
1521 | cpu_poke = true; | |
1522 | return; | |
1523 | } | |
1524 | ||
1525 | pr_debug("CPU_POKE not supported\n"); | |
19926630 DM |
1526 | } |
1527 | ||
9960e9e8 | 1528 | void __irq_entry smp_receive_signal_client(int irq, struct pt_regs *regs) |
19926630 DM |
1529 | { |
1530 | clear_softint(1 << irq); | |
184748cc | 1531 | scheduler_ipi(); |
1da177e4 LT |
1532 | } |
1533 | ||
94ab5990 DK |
1534 | static void stop_this_cpu(void *dummy) |
1535 | { | |
cffb3e76 | 1536 | set_cpu_online(smp_processor_id(), false); |
94ab5990 DK |
1537 | prom_stopself(); |
1538 | } | |
1539 | ||
1da177e4 LT |
1540 | void smp_send_stop(void) |
1541 | { | |
94ab5990 DK |
1542 | int cpu; |
1543 | ||
1544 | if (tlb_type == hypervisor) { | |
7dd4fcf5 VK |
1545 | int this_cpu = smp_processor_id(); |
1546 | #ifdef CONFIG_SERIAL_SUNHV | |
1547 | sunhv_migrate_hvcons_irq(this_cpu); | |
1548 | #endif | |
94ab5990 | 1549 | for_each_online_cpu(cpu) { |
7dd4fcf5 | 1550 | if (cpu == this_cpu) |
94ab5990 | 1551 | continue; |
cffb3e76 VK |
1552 | |
1553 | set_cpu_online(cpu, false); | |
94ab5990 DK |
1554 | #ifdef CONFIG_SUN_LDOMS |
1555 | if (ldom_domaining_enabled) { | |
1556 | unsigned long hv_err; | |
1557 | hv_err = sun4v_cpu_stop(cpu); | |
1558 | if (hv_err) | |
1559 | printk(KERN_ERR "sun4v_cpu_stop() " | |
1560 | "failed err=%lu\n", hv_err); | |
1561 | } else | |
1562 | #endif | |
1563 | prom_stopcpu_cpuid(cpu); | |
1564 | } | |
1565 | } else | |
1566 | smp_call_function(stop_this_cpu, NULL, 0); | |
1da177e4 LT |
1567 | } |
1568 | ||
4fd78a5f DM |
1569 | /** |
1570 | * pcpu_alloc_bootmem - NUMA friendly alloc_bootmem wrapper for percpu | |
1571 | * @cpu: cpu to allocate for | |
1572 | * @size: size allocation in bytes | |
1573 | * @align: alignment | |
1574 | * | |
1575 | * Allocate @size bytes aligned at @align for cpu @cpu. This wrapper | |
1576 | * does the right thing for NUMA regardless of the current | |
1577 | * configuration. | |
1578 | * | |
1579 | * RETURNS: | |
1580 | * Pointer to the allocated area on success, NULL on failure. | |
1581 | */ | |
bcb2107f TH |
1582 | static void * __init pcpu_alloc_bootmem(unsigned int cpu, size_t size, |
1583 | size_t align) | |
4fd78a5f DM |
1584 | { |
1585 | const unsigned long goal = __pa(MAX_DMA_ADDRESS); | |
1586 | #ifdef CONFIG_NEED_MULTIPLE_NODES | |
1587 | int node = cpu_to_node(cpu); | |
1588 | void *ptr; | |
1589 | ||
1590 | if (!node_online(node) || !NODE_DATA(node)) { | |
1591 | ptr = __alloc_bootmem(size, align, goal); | |
1592 | pr_info("cpu %d has no node %d or node-local memory\n", | |
1593 | cpu, node); | |
1594 | pr_debug("per cpu data for cpu%d %lu bytes at %016lx\n", | |
1595 | cpu, size, __pa(ptr)); | |
1596 | } else { | |
1597 | ptr = __alloc_bootmem_node(NODE_DATA(node), | |
1598 | size, align, goal); | |
1599 | pr_debug("per cpu data for cpu%d %lu bytes on node%d at " | |
1600 | "%016lx\n", cpu, size, node, __pa(ptr)); | |
1601 | } | |
1602 | return ptr; | |
1603 | #else | |
1604 | return __alloc_bootmem(size, align, goal); | |
1605 | #endif | |
1606 | } | |
1607 | ||
bcb2107f | 1608 | static void __init pcpu_free_bootmem(void *ptr, size_t size) |
4fd78a5f | 1609 | { |
bcb2107f TH |
1610 | free_bootmem(__pa(ptr), size); |
1611 | } | |
4fd78a5f | 1612 | |
a70c6913 | 1613 | static int __init pcpu_cpu_distance(unsigned int from, unsigned int to) |
bcb2107f TH |
1614 | { |
1615 | if (cpu_to_node(from) == cpu_to_node(to)) | |
1616 | return LOCAL_DISTANCE; | |
1617 | else | |
1618 | return REMOTE_DISTANCE; | |
4fd78a5f DM |
1619 | } |
1620 | ||
a70c6913 TH |
1621 | static void __init pcpu_populate_pte(unsigned long addr) |
1622 | { | |
1623 | pgd_t *pgd = pgd_offset_k(addr); | |
1624 | pud_t *pud; | |
1625 | pmd_t *pmd; | |
1626 | ||
ac55c768 DM |
1627 | if (pgd_none(*pgd)) { |
1628 | pud_t *new; | |
1629 | ||
1630 | new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); | |
1631 | pgd_populate(&init_mm, pgd, new); | |
1632 | } | |
1633 | ||
a70c6913 TH |
1634 | pud = pud_offset(pgd, addr); |
1635 | if (pud_none(*pud)) { | |
1636 | pmd_t *new; | |
1637 | ||
1638 | new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); | |
1639 | pud_populate(&init_mm, pud, new); | |
1640 | } | |
1641 | ||
1642 | pmd = pmd_offset(pud, addr); | |
1643 | if (!pmd_present(*pmd)) { | |
1644 | pte_t *new; | |
1645 | ||
1646 | new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); | |
1647 | pmd_populate_kernel(&init_mm, pmd, new); | |
1648 | } | |
1649 | } | |
1650 | ||
73fffc03 | 1651 | void __init setup_per_cpu_areas(void) |
1da177e4 | 1652 | { |
bcb2107f TH |
1653 | unsigned long delta; |
1654 | unsigned int cpu; | |
a70c6913 TH |
1655 | int rc = -EINVAL; |
1656 | ||
1657 | if (pcpu_chosen_fc != PCPU_FC_PAGE) { | |
1658 | rc = pcpu_embed_first_chunk(PERCPU_MODULE_RESERVE, | |
1659 | PERCPU_DYNAMIC_RESERVE, 4 << 20, | |
1660 | pcpu_cpu_distance, | |
1661 | pcpu_alloc_bootmem, | |
1662 | pcpu_free_bootmem); | |
1663 | if (rc) | |
1664 | pr_warning("PERCPU: %s allocator failed (%d), " | |
1665 | "falling back to page size\n", | |
1666 | pcpu_fc_names[pcpu_chosen_fc], rc); | |
1667 | } | |
1668 | if (rc < 0) | |
1669 | rc = pcpu_page_first_chunk(PERCPU_MODULE_RESERVE, | |
1670 | pcpu_alloc_bootmem, | |
1671 | pcpu_free_bootmem, | |
1672 | pcpu_populate_pte); | |
1673 | if (rc < 0) | |
1674 | panic("cannot initialize percpu area (err=%d)", rc); | |
5a089006 | 1675 | |
4fd78a5f | 1676 | delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; |
fb435d52 TH |
1677 | for_each_possible_cpu(cpu) |
1678 | __per_cpu_offset(cpu) = delta + pcpu_unit_offsets[cpu]; | |
951bc82c DM |
1679 | |
1680 | /* Setup %g5 for the boot cpu. */ | |
1681 | __local_per_cpu_offset = __per_cpu_offset(smp_processor_id()); | |
b696fdc2 DM |
1682 | |
1683 | of_fill_in_cpu_data(); | |
1684 | if (tlb_type == hypervisor) | |
6ac5c610 | 1685 | mdesc_fill_in_cpu_data(cpu_all_mask); |
1da177e4 | 1686 | } |