[linux-block.git] / arch / sparc / kernel / setup_64.c

// SPDX-License-Identifier: GPL-2.0
/*
 *  linux/arch/sparc64/kernel/setup.c
 *
 *  Copyright (C) 1995,1996  David S. Miller (davem@caip.rutgers.edu)
 *  Copyright (C) 1997       Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 */

#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/stddef.h>
#include <linux/unistd.h>
#include <linux/ptrace.h>
#include <asm/smp.h>
#include <linux/user.h>
#include <linux/screen_info.h>
#include <linux/delay.h>
#include <linux/fs.h>
#include <linux/seq_file.h>
#include <linux/syscalls.h>
#include <linux/kdev_t.h>
#include <linux/major.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/inet.h>
#include <linux/console.h>
#include <linux/root_dev.h>
#include <linux/interrupt.h>
#include <linux/cpu.h>
#include <linux/initrd.h>
#include <linux/module.h>
#include <linux/start_kernel.h>
#include <linux/memblock.h>
#include <uapi/linux/mount.h>

#include <asm/io.h>
#include <asm/processor.h>
#include <asm/oplib.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/idprom.h>
#include <asm/head.h>
#include <asm/starfire.h>
#include <asm/mmu_context.h>
#include <asm/timer.h>
#include <asm/sections.h>
#include <asm/setup.h>
#include <asm/mmu.h>
#include <asm/ns87303.h>
#include <asm/btext.h>
#include <asm/elf.h>
#include <asm/mdesc.h>
#include <asm/cacheflush.h>
#include <asm/dma.h>
#include <asm/irq.h>

#ifdef CONFIG_IP_PNP
#include <net/ipconfig.h>
#endif

#include "entry.h"
#include "kernel.h"

/* Used to synchronize accesses to NatSemi SUPER I/O chip configure
 * operations in asm/ns87303.h
 */
DEFINE_SPINLOCK(ns87303_lock);
EXPORT_SYMBOL(ns87303_lock);

struct screen_info screen_info = {
	0, 0,			/* orig-x, orig-y */
	0,			/* unused */
	0,			/* orig-video-page */
	0,			/* orig-video-mode */
	128,			/* orig-video-cols */
	0, 0, 0,		/* unused, ega_bx, unused */
	54,			/* orig-video-lines */
	0,                      /* orig-video-isVGA */
	16                      /* orig-video-points */
};

static void
prom_console_write(struct console *con, const char *s, unsigned int n)
{
	prom_write(s, n);
}

/* Exported for mm/init.c:paging_init. */
unsigned long cmdline_memory_size = 0;

static struct console prom_early_console = {
	.name =		"earlyprom",
	.write =	prom_console_write,
	.flags =	CON_PRINTBUFFER | CON_BOOT | CON_ANYTIME,
	.index =	-1,
};

/*
 * Process kernel command line switches that are specific to the
 * SPARC or that require special low-level processing.
 */
static void __init process_switch(char c)
{
	switch (c) {
	case 'd':
	case 's':
		break;
	case 'h':
		prom_printf("boot_flags_init: Halt!\n");
		prom_halt();
		break;
	case 'p':
		prom_early_console.flags &= ~CON_BOOT;
		break;
	case 'P':
		/* Force UltraSPARC-III P-Cache on. */
		if (tlb_type != cheetah) {
			printk("BOOT: Ignoring P-Cache force option.\n");
			break;
		}
		cheetah_pcache_forced_on = 1;
		add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
		cheetah_enable_pcache();
		break;

	default:
		printk("Unknown boot switch (-%c)\n", c);
		break;
	}
}

static void __init boot_flags_init(char *commands)
{
	while (*commands) {
		/* Move to the start of the next "argument". */
		while (*commands == ' ')
			commands++;

		/* Process any command switches, otherwise skip it. */
		if (*commands == '\0')
			break;
		if (*commands == '-') {
			commands++;
			while (*commands && *commands != ' ')
				process_switch(*commands++);
			continue;
		}
		if (!strncmp(commands, "mem=", 4))
			cmdline_memory_size = memparse(commands + 4, &commands);

		while (*commands && *commands != ' ')
			commands++;
	}
}

extern unsigned short root_flags;
extern unsigned short root_dev;
extern unsigned short ram_flags;
#define RAMDISK_IMAGE_START_MASK	0x07FF
#define RAMDISK_PROMPT_FLAG		0x8000
#define RAMDISK_LOAD_FLAG		0x4000

extern int root_mountflags;

char reboot_command[COMMAND_LINE_SIZE];

static struct pt_regs fake_swapper_regs = { { 0, }, 0, 0, 0, 0 };

static void __init per_cpu_patch(void)
{
	struct cpuid_patch_entry *p;
	unsigned long ver;
	int is_jbus;

	if (tlb_type == spitfire && !this_is_starfire)
		return;

	is_jbus = 0;
	if (tlb_type != hypervisor) {
		__asm__ ("rdpr %%ver, %0" : "=r" (ver));
		is_jbus = ((ver >> 32UL) == __JALAPENO_ID ||
			   (ver >> 32UL) == __SERRANO_ID);
	}

	p = &__cpuid_patch;
	while (p < &__cpuid_patch_end) {
		unsigned long addr = p->addr;
		unsigned int *insns;

		switch (tlb_type) {
		case spitfire:
			insns = &p->starfire[0];
			break;
		case cheetah:
		case cheetah_plus:
			if (is_jbus)
				insns = &p->cheetah_jbus[0];
			else
				insns = &p->cheetah_safari[0];
			break;
		case hypervisor:
			insns = &p->sun4v[0];
			break;
		default:
			prom_printf("Unknown cpu type, halting.\n");
			prom_halt();
		}

		*(unsigned int *) (addr +  0) = insns[0];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  0));

		*(unsigned int *) (addr +  4) = insns[1];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  4));

		*(unsigned int *) (addr +  8) = insns[2];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  8));

		*(unsigned int *) (addr + 12) = insns[3];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr + 12));

		p++;
	}
}

void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *start,
			     struct sun4v_1insn_patch_entry *end)
{
	while (start < end) {
		unsigned long addr = start->addr;

		*(unsigned int *) (addr +  0) = start->insn;
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  0));

		start++;
	}
}

void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
			     struct sun4v_2insn_patch_entry *end)
{
	while (start < end) {
		unsigned long addr = start->addr;

		*(unsigned int *) (addr +  0) = start->insns[0];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  0));

		*(unsigned int *) (addr +  4) = start->insns[1];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  4));

		start++;
	}
}

void sun_m7_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
			     struct sun4v_2insn_patch_entry *end)
{
	while (start < end) {
		unsigned long addr = start->addr;

		*(unsigned int *) (addr +  0) = start->insns[0];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  0));

		*(unsigned int *) (addr +  4) = start->insns[1];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  4));

		start++;
	}
}

static void __init sun4v_patch(void)
{
	extern void sun4v_hvapi_init(void);

	if (tlb_type != hypervisor)
		return;

	sun4v_patch_1insn_range(&__sun4v_1insn_patch,
				&__sun4v_1insn_patch_end);

	sun4v_patch_2insn_range(&__sun4v_2insn_patch,
				&__sun4v_2insn_patch_end);

	switch (sun4v_chip_type) {
	case SUN4V_CHIP_SPARC_M7:
	case SUN4V_CHIP_SPARC_M8:
	case SUN4V_CHIP_SPARC_SN:
		sun4v_patch_1insn_range(&__sun_m7_1insn_patch,
					&__sun_m7_1insn_patch_end);
		sun_m7_patch_2insn_range(&__sun_m7_2insn_patch,
					 &__sun_m7_2insn_patch_end);
		break;
	default:
		break;
	}

	if (sun4v_chip_type != SUN4V_CHIP_NIAGARA1) {
		sun4v_patch_1insn_range(&__fast_win_ctrl_1insn_patch,
					&__fast_win_ctrl_1insn_patch_end);
	}

	sun4v_hvapi_init();
}

static void __init popc_patch(void)
{
	struct popc_3insn_patch_entry *p3;
	struct popc_6insn_patch_entry *p6;

	p3 = &__popc_3insn_patch;
	while (p3 < &__popc_3insn_patch_end) {
		unsigned long i, addr = p3->addr;

		for (i = 0; i < 3; i++) {
			*(unsigned int *) (addr +  (i * 4)) = p3->insns[i];
			wmb();
			__asm__ __volatile__("flush	%0"
					     : : "r" (addr +  (i * 4)));
		}

		p3++;
	}

	p6 = &__popc_6insn_patch;
	while (p6 < &__popc_6insn_patch_end) {
		unsigned long i, addr = p6->addr;

		for (i = 0; i < 6; i++) {
			*(unsigned int *) (addr +  (i * 4)) = p6->insns[i];
			wmb();
			__asm__ __volatile__("flush	%0"
					     : : "r" (addr +  (i * 4)));
		}

		p6++;
	}
}

static void __init pause_patch(void)
{
	struct pause_patch_entry *p;

	p = &__pause_3insn_patch;
	while (p < &__pause_3insn_patch_end) {
		unsigned long i, addr = p->addr;

		for (i = 0; i < 3; i++) {
			*(unsigned int *) (addr +  (i * 4)) = p->insns[i];
			wmb();
			__asm__ __volatile__("flush	%0"
					     : : "r" (addr +  (i * 4)));
		}

		p++;
	}
}

void __init start_early_boot(void)
{
	int cpu;

	check_if_starfire();
	per_cpu_patch();
	sun4v_patch();
	smp_init_cpu_poke();

	cpu = hard_smp_processor_id();
	if (cpu >= NR_CPUS) {
		prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n",
			    cpu, NR_CPUS);
		prom_halt();
	}
	current_thread_info()->cpu = cpu;

	time_init_early();
	prom_init_report();
	start_kernel();
}

/* On Ultra, we support all of the v8 capabilities. */
unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR |
				   HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV |
				   HWCAP_SPARC_V9);
EXPORT_SYMBOL(sparc64_elf_hwcap);

static const char *hwcaps[] = {
	"flush", "stbar", "swap", "muldiv", "v9",
	"ultra3", "blkinit", "n2",

	/* These strings are as they appear in the machine description
	 * 'hwcap-list' property for cpu nodes.
	 */
	"mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2",
	"ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau",
	"ima", "cspare", "pause", "cbcond", NULL /*reserved for crypto */,
	"adp",
};

static const char *crypto_hwcaps[] = {
	"aes", "des", "kasumi", "camellia", "md5", "sha1", "sha256",
	"sha512", "mpmul", "montmul", "montsqr", "crc32c",
};

void cpucap_info(struct seq_file *m)
{
	unsigned long caps = sparc64_elf_hwcap;
	int i, printed = 0;

	seq_puts(m, "cpucaps\t\t: ");
	for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
		unsigned long bit = 1UL << i;
		if (hwcaps[i] && (caps & bit)) {
			seq_printf(m, "%s%s",
				   printed ? "," : "", hwcaps[i]);
			printed++;
		}
	}
	if (caps & HWCAP_SPARC_CRYPTO) {
		unsigned long cfr;

		__asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
		for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
			unsigned long bit = 1UL << i;
			if (cfr & bit) {
				seq_printf(m, "%s%s",
					   printed ? "," : "", crypto_hwcaps[i]);
				printed++;
			}
		}
	}
	seq_putc(m, '\n');
}

static void __init report_one_hwcap(int *printed, const char *name)
{
	if ((*printed) == 0)
		printk(KERN_INFO "CPU CAPS: [");
	printk(KERN_CONT "%s%s",
	       (*printed) ? "," : "", name);
	if (++(*printed) == 8) {
		printk(KERN_CONT "]\n");
		*printed = 0;
	}
}

static void __init report_crypto_hwcaps(int *printed)
{
	unsigned long cfr;
	int i;

	__asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));

	for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
		unsigned long bit = 1UL << i;
		if (cfr & bit)
			report_one_hwcap(printed, crypto_hwcaps[i]);
	}
}

static void __init report_hwcaps(unsigned long caps)
{
	int i, printed = 0;

	for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
		unsigned long bit = 1UL << i;
		if (hwcaps[i] && (caps & bit))
			report_one_hwcap(&printed, hwcaps[i]);
	}
	if (caps & HWCAP_SPARC_CRYPTO)
		report_crypto_hwcaps(&printed);
	if (printed != 0)
		printk(KERN_CONT "]\n");
}

static unsigned long __init mdesc_cpu_hwcap_list(void)
{
	struct mdesc_handle *hp;
	unsigned long caps = 0;
	const char *prop;
	int len;
	u64 pn;

	hp = mdesc_grab();
	if (!hp)
		return 0;

	pn = mdesc_node_by_name(hp, MDESC_NODE_NULL, "cpu");
	if (pn == MDESC_NODE_NULL)
		goto out;

	prop = mdesc_get_property(hp, pn, "hwcap-list", &len);
	if (!prop)
		goto out;

	while (len) {
		int i, plen;

		for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
			unsigned long bit = 1UL << i;

			if (hwcaps[i] && !strcmp(prop, hwcaps[i])) {
				caps |= bit;
				break;
			}
		}
		for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
			if (!strcmp(prop, crypto_hwcaps[i]))
				caps |= HWCAP_SPARC_CRYPTO;
		}

		plen = strlen(prop) + 1;
		prop += plen;
		len -= plen;
	}

out:
	mdesc_release(hp);
	return caps;
}

/* This yields a mask that user programs can use to figure out what
 * instruction set this cpu supports.
 */
static void __init init_sparc64_elf_hwcap(void)
{
	unsigned long cap = sparc64_elf_hwcap;
	unsigned long mdesc_caps;

	if (tlb_type == cheetah || tlb_type == cheetah_plus)
		cap |= HWCAP_SPARC_ULTRA3;
	else if (tlb_type == hypervisor) {
		if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC64X)
			cap |= HWCAP_SPARC_BLKINIT;
		if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC64X)
			cap |= HWCAP_SPARC_N2;
	}

	cap |= (AV_SPARC_MUL32 | AV_SPARC_DIV32 | AV_SPARC_V8PLUS);

	mdesc_caps = mdesc_cpu_hwcap_list();
	if (!mdesc_caps) {
		if (tlb_type == spitfire)
			cap |= AV_SPARC_VIS;
		if (tlb_type == cheetah || tlb_type == cheetah_plus)
			cap |= AV_SPARC_VIS | AV_SPARC_VIS2;
		if (tlb_type == cheetah_plus) {
			unsigned long impl, ver;

			__asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
			impl = ((ver >> 32) & 0xffff);
			if (impl == PANTHER_IMPL)
				cap |= AV_SPARC_POPC;
		}
		if (tlb_type == hypervisor) {
			if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1)
				cap |= AV_SPARC_ASI_BLK_INIT;
			if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
			    sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
			    sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
			    sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC64X)
				cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
					AV_SPARC_ASI_BLK_INIT |
					AV_SPARC_POPC);
			if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
			    sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
			    sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC64X)
				cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
					AV_SPARC_FMAF);
		}
	}
	sparc64_elf_hwcap = cap | mdesc_caps;

	report_hwcaps(sparc64_elf_hwcap);

	if (sparc64_elf_hwcap & AV_SPARC_POPC)
		popc_patch();
	if (sparc64_elf_hwcap & AV_SPARC_PAUSE)
		pause_patch();
}

void __init alloc_irqstack_bootmem(void)
{
	unsigned int i, node;

	for_each_possible_cpu(i) {
		node = cpu_to_node(i);

		softirq_stack[i] = memblock_alloc_node(THREAD_SIZE,
						       THREAD_SIZE, node);
		hardirq_stack[i] = memblock_alloc_node(THREAD_SIZE,
						       THREAD_SIZE, node);
	}
}

void __init setup_arch(char **cmdline_p)
{
	/* Initialize PROM console and command line. */
	*cmdline_p = prom_getbootargs();
	strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
	parse_early_param();

	boot_flags_init(*cmdline_p);
#ifdef CONFIG_EARLYFB
	if (btext_find_display())
#endif
		register_console(&prom_early_console);

	if (tlb_type == hypervisor)
		printk("ARCH: SUN4V\n");
	else
		printk("ARCH: SUN4U\n");

#ifdef CONFIG_DUMMY_CONSOLE
	conswitchp = &dummy_con;
#endif

	idprom_init();

	if (!root_flags)
		root_mountflags &= ~MS_RDONLY;
	ROOT_DEV = old_decode_dev(root_dev);
#ifdef CONFIG_BLK_DEV_RAM
	rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK;
	rd_prompt = ((ram_flags & RAMDISK_PROMPT_FLAG) != 0);
	rd_doload = ((ram_flags & RAMDISK_LOAD_FLAG) != 0);
#endif

	task_thread_info(&init_task)->kregs = &fake_swapper_regs;

#ifdef CONFIG_IP_PNP
	if (!ic_set_manually) {
		phandle chosen = prom_finddevice("/chosen");
		u32 cl, sv, gw;

		cl = prom_getintdefault (chosen, "client-ip", 0);
		sv = prom_getintdefault (chosen, "server-ip", 0);
		gw = prom_getintdefault (chosen, "gateway-ip", 0);
		if (cl && sv) {
			ic_myaddr = cl;
			ic_servaddr = sv;
			if (gw)
				ic_gateway = gw;
#if defined(CONFIG_IP_PNP_BOOTP) || defined(CONFIG_IP_PNP_RARP)
			ic_proto_enabled = 0;
#endif
		}
	}
#endif

	/* Get boot processor trap_block[] setup.  */
	init_cur_cpu_trap(current_thread_info());

	paging_init();
	init_sparc64_elf_hwcap();
	smp_fill_in_cpu_possible_map();
	/*
	 * Once the OF device tree and MDESC have been setup and nr_cpus has
	 * been parsed, we know the list of possible cpus.  Therefore we can
	 * allocate the IRQ stacks.
	 */
	alloc_irqstack_bootmem();
}

extern int stop_a_enabled;

void sun_do_break(void)
{
	if (!stop_a_enabled)
		return;

	prom_printf("\n");
	flush_user_windows();

	prom_cmdline();
}
EXPORT_SYMBOL(sun_do_break);

int stop_a_enabled = 1;
EXPORT_SYMBOL(stop_a_enabled);
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
b00dc837	2	/*
1da177e4 LT	3	* linux/arch/sparc64/kernel/setup.c
	4	*
	5	* Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
	6	* Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
	7	*/
	8
	9	#include <linux/errno.h>
	10	#include <linux/sched.h>
	11	#include <linux/kernel.h>
	12	#include <linux/mm.h>
	13	#include <linux/stddef.h>
	14	#include <linux/unistd.h>
	15	#include <linux/ptrace.h>
1da177e4 LT	16	#include <asm/smp.h>
1da177e4 LT	17	#include <linux/user.h>
894673ee	18	#include <linux/screen_info.h>
1da177e4	19	#include <linux/delay.h>
1da177e4 LT	20	#include <linux/fs.h>
	21	#include <linux/seq_file.h>
	22	#include <linux/syscalls.h>
	23	#include <linux/kdev_t.h>
	24	#include <linux/major.h>
	25	#include <linux/string.h>
	26	#include <linux/init.h>
	27	#include <linux/inet.h>
	28	#include <linux/console.h>
	29	#include <linux/root_dev.h>
	30	#include <linux/interrupt.h>
	31	#include <linux/cpu.h>
	32	#include <linux/initrd.h>
ac85fe8b	33	#include <linux/module.h>
ef3e035c	34	#include <linux/start_kernel.h>
57c8a661	35	#include <linux/memblock.h>
e262e32d	36	#include <uapi/linux/mount.h>
1da177e4	37
1da177e4 LT	38	#include <asm/io.h>
	39	#include <asm/processor.h>
	40	#include <asm/oplib.h>
	41	#include <asm/page.h>
	42	#include <asm/pgtable.h>
	43	#include <asm/idprom.h>
	44	#include <asm/head.h>
	45	#include <asm/starfire.h>
	46	#include <asm/mmu_context.h>
	47	#include <asm/timer.h>
	48	#include <asm/sections.h>
	49	#include <asm/setup.h>
	50	#include <asm/mmu.h>
5cbc3073	51	#include <asm/ns87303.h>
c57ec52f	52	#include <asm/btext.h>
ac85fe8b DM	53	#include <asm/elf.h>
ac85fe8b DM	54	#include <asm/mdesc.h>
d550bbd4	55	#include <asm/cacheflush.h>
ebb99a4c AP	56	#include <asm/dma.h>
ebb99a4c AP	57	#include <asm/irq.h>
1da177e4 LT	58
	59	#ifdef CONFIG_IP_PNP
	60	#include <net/ipconfig.h>
	61	#endif
	62
3d5ae6b6	63	#include "entry.h"
53ae3419	64	#include "kernel.h"
3d5ae6b6	65
5cbc3073 DM	66	/* Used to synchronize accesses to NatSemi SUPER I/O chip configure
	67	* operations in asm/ns87303.h
	68	*/
	69	DEFINE_SPINLOCK(ns87303_lock);
917c3660	70	EXPORT_SYMBOL(ns87303_lock);
5cbc3073	71
1da177e4 LT	72	struct screen_info screen_info = {
	73	0, 0, /* orig-x, orig-y */
	74	0, /* unused */
	75	0, /* orig-video-page */
	76	0, /* orig-video-mode */
	77	128, /* orig-video-cols */
	78	0, 0, 0, /* unused, ega_bx, unused */
	79	54, /* orig-video-lines */
	80	0, /* orig-video-isVGA */
	81	16 /* orig-video-points */
	82	};
	83
1da177e4	84	static void
9ef595d8	85	prom_console_write(struct console con, const char s, unsigned int n)
1da177e4 LT	86	{
	87	prom_write(s, n);
	88	}
	89
1da177e4 LT	90	/* Exported for mm/init.c:paging_init. */
	91	unsigned long cmdline_memory_size = 0;
	92
3c62a2d3 DM	93	static struct console prom_early_console = {
3c62a2d3 DM	94	.name = "earlyprom",
1da177e4	95	.write = prom_console_write,
db9a7fb1	96	.flags = CON_PRINTBUFFER \| CON_BOOT \| CON_ANYTIME,
1da177e4 LT	97	.index = -1,
	98	};
	99
68a79217	100	/*
1da177e4 LT	101	* Process kernel command line switches that are specific to the
	102	* SPARC or that require special low-level processing.
	103	*/
	104	static void __init process_switch(char c)
	105	{
	106	switch (c) {
	107	case 'd':
1da177e4	108	case 's':
1da177e4 LT	109	break;
	110	case 'h':
	111	prom_printf("boot_flags_init: Halt!\n");
	112	prom_halt();
	113	break;
	114	case 'p':
11032c17	115	prom_early_console.flags &= ~CON_BOOT;
1da177e4	116	break;
816242da DM	117	case 'P':
	118	/* Force UltraSPARC-III P-Cache on. */
	119	if (tlb_type != cheetah) {
	120	printk("BOOT: Ignoring P-Cache force option.\n");
	121	break;
	122	}
	123	cheetah_pcache_forced_on = 1;
373d4d09	124	add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
816242da DM	125	cheetah_enable_pcache();
	126	break;
	127
1da177e4 LT	128	default:
	129	printk("Unknown boot switch (-%c)\n", c);
	130	break;
	131	}
	132	}
	133
1da177e4 LT	134	static void __init boot_flags_init(char *commands)
	135	{
	136	while (*commands) {
	137	/* Move to the start of the next "argument". */
8c64415c	138	while (*commands == ' ')
1da177e4 LT	139	commands++;
	140
	141	/* Process any command switches, otherwise skip it. */
	142	if (*commands == '\0')
	143	break;
	144	if (*commands == '-') {
	145	commands++;
	146	while (commands && commands != ' ')
	147	process_switch(*commands++);
	148	continue;
	149	}
7c21d533	150	if (!strncmp(commands, "mem=", 4))
	151	cmdline_memory_size = memparse(commands + 4, &commands);
	152
1da177e4 LT	153	while (commands && commands != ' ')
	154	commands++;
	155	}
	156	}
	157
1da177e4 LT	158	extern unsigned short root_flags;
	159	extern unsigned short root_dev;
	160	extern unsigned short ram_flags;
	161	#define RAMDISK_IMAGE_START_MASK 0x07FF
	162	#define RAMDISK_PROMPT_FLAG 0x8000
	163	#define RAMDISK_LOAD_FLAG 0x4000
	164
	165	extern int root_mountflags;
	166
	167	char reboot_command[COMMAND_LINE_SIZE];
	168
	169	static struct pt_regs fake_swapper_regs = { { 0, }, 0, 0, 0, 0 };
	170
ef3e035c	171	static void __init per_cpu_patch(void)
92704a1c	172	{
92704a1c DM	173	struct cpuid_patch_entry *p;
	174	unsigned long ver;
	175	int is_jbus;
	176
	177	if (tlb_type == spitfire && !this_is_starfire)
	178	return;
	179
d82ace7d DM	180	is_jbus = 0;
	181	if (tlb_type != hypervisor) {
	182	__asm__ ("rdpr %%ver, %0" : "=r" (ver));
ebd8c56c DM	183	is_jbus = ((ver >> 32UL) == __JALAPENO_ID \|\|
ebd8c56c DM	184	(ver >> 32UL) == __SERRANO_ID);
d82ace7d	185	}
92704a1c DM	186
	187	p = &__cpuid_patch;
	188	while (p < &__cpuid_patch_end) {
	189	unsigned long addr = p->addr;
	190	unsigned int *insns;
	191
	192	switch (tlb_type) {
	193	case spitfire:
	194	insns = &p->starfire[0];
	195	break;
	196	case cheetah:
	197	case cheetah_plus:
	198	if (is_jbus)
	199	insns = &p->cheetah_jbus[0];
	200	else
	201	insns = &p->cheetah_safari[0];
	202	break;
d96b8153 DM	203	case hypervisor:
	204	insns = &p->sun4v[0];
	205	break;
92704a1c DM	206	default:
	207	prom_printf("Unknown cpu type, halting.\n");
	208	prom_halt();
6cb79b3f	209	}
92704a1c DM	210
92704a1c DM	211	(unsigned int ) (addr + 0) = insns[0];
840aaef8	212	wmb();
92704a1c DM	213	__asm__ __volatile__("flush %0" : : "r" (addr + 0));
	214
	215	(unsigned int ) (addr + 4) = insns[1];
840aaef8	216	wmb();
92704a1c DM	217	__asm__ __volatile__("flush %0" : : "r" (addr + 4));
	218
	219	(unsigned int ) (addr + 8) = insns[2];
840aaef8	220	wmb();
92704a1c DM	221	__asm__ __volatile__("flush %0" : : "r" (addr + 8));
	222
	223	(unsigned int ) (addr + 12) = insns[3];
840aaef8	224	wmb();
92704a1c DM	225	__asm__ __volatile__("flush %0" : : "r" (addr + 12));
	226
	227	p++;
	228	}
92704a1c DM	229	}
92704a1c DM	230
0b64120c DM	231	void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *start,
0b64120c DM	232	struct sun4v_1insn_patch_entry *end)
936f482a	233	{
0b64120c DM	234	while (start < end) {
0b64120c DM	235	unsigned long addr = start->addr;
936f482a	236
0b64120c	237	(unsigned int ) (addr + 0) = start->insn;
840aaef8	238	wmb();
936f482a DM	239	__asm__ __volatile__("flush %0" : : "r" (addr + 0));
936f482a DM	240
0b64120c	241	start++;
45fec05f	242	}
0b64120c	243	}
45fec05f	244
0b64120c DM	245	void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
	246	struct sun4v_2insn_patch_entry *end)
	247	{
	248	while (start < end) {
	249	unsigned long addr = start->addr;
45fec05f	250
0b64120c	251	(unsigned int ) (addr + 0) = start->insns[0];
840aaef8	252	wmb();
45fec05f DM	253	__asm__ __volatile__("flush %0" : : "r" (addr + 0));
45fec05f DM	254
0b64120c	255	(unsigned int ) (addr + 4) = start->insns[1];
840aaef8	256	wmb();
45fec05f DM	257	__asm__ __volatile__("flush %0" : : "r" (addr + 4));
45fec05f DM	258
0b64120c	259	start++;
936f482a	260	}
0b64120c DM	261	}
0b64120c DM	262
494e5b6f KA	263	void sun_m7_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
	264	struct sun4v_2insn_patch_entry *end)
	265	{
	266	while (start < end) {
	267	unsigned long addr = start->addr;
	268
	269	(unsigned int ) (addr + 0) = start->insns[0];
	270	wmb();
	271	__asm__ __volatile__("flush %0" : : "r" (addr + 0));
	272
	273	(unsigned int ) (addr + 4) = start->insns[1];
	274	wmb();
	275	__asm__ __volatile__("flush %0" : : "r" (addr + 4));
	276
	277	start++;
	278	}
	279	}
	280
ef3e035c	281	static void __init sun4v_patch(void)
0b64120c DM	282	{
	283	extern void sun4v_hvapi_init(void);
	284
	285	if (tlb_type != hypervisor)
	286	return;
	287
	288	sun4v_patch_1insn_range(&__sun4v_1insn_patch,
	289	&__sun4v_1insn_patch_end);
	290
	291	sun4v_patch_2insn_range(&__sun4v_2insn_patch,
	292	&__sun4v_2insn_patch_end);
7d484acb AP	293
	294	switch (sun4v_chip_type) {
	295	case SUN4V_CHIP_SPARC_M7:
	296	case SUN4V_CHIP_SPARC_M8:
	297	case SUN4V_CHIP_SPARC_SN:
74a04967 KA	298	sun4v_patch_1insn_range(&__sun_m7_1insn_patch,
74a04967 KA	299	&__sun_m7_1insn_patch_end);
494e5b6f KA	300	sun_m7_patch_2insn_range(&__sun_m7_2insn_patch,
494e5b6f KA	301	&__sun_m7_2insn_patch_end);
7d484acb AP	302	break;
	303	default:
	304	break;
	305	}
c7754d46	306
a7159a87 AY	307	if (sun4v_chip_type != SUN4V_CHIP_NIAGARA1) {
	308	sun4v_patch_1insn_range(&__fast_win_ctrl_1insn_patch,
	309	&__fast_win_ctrl_1insn_patch_end);
	310	}
	311
c7754d46	312	sun4v_hvapi_init();
936f482a DM	313	}
936f482a DM	314
ef7c4d46 DM	315	static void __init popc_patch(void)
	316	{
	317	struct popc_3insn_patch_entry *p3;
56d205cc	318	struct popc_6insn_patch_entry *p6;
ef7c4d46 DM	319
	320	p3 = &__popc_3insn_patch;
	321	while (p3 < &__popc_3insn_patch_end) {
56d205cc	322	unsigned long i, addr = p3->addr;
ef7c4d46	323
56d205cc DM	324	for (i = 0; i < 3; i++) {
	325	(unsigned int ) (addr + (i * 4)) = p3->insns[i];
	326	wmb();
	327	__asm__ __volatile__("flush %0"
	328	: : "r" (addr + (i * 4)));
	329	}
ef7c4d46	330
56d205cc DM	331	p3++;
56d205cc DM	332	}
ef7c4d46	333
56d205cc DM	334	p6 = &__popc_6insn_patch;
	335	while (p6 < &__popc_6insn_patch_end) {
	336	unsigned long i, addr = p6->addr;
ef7c4d46	337
56d205cc DM	338	for (i = 0; i < 6; i++) {
	339	(unsigned int ) (addr + (i * 4)) = p6->insns[i];
	340	wmb();
	341	__asm__ __volatile__("flush %0"
	342	: : "r" (addr + (i * 4)));
	343	}
	344
	345	p6++;
ef7c4d46 DM	346	}
	347	}
	348
e9b9eb59 DM	349	static void __init pause_patch(void)
	350	{
	351	struct pause_patch_entry *p;
	352
187818cd DM	353	p = &__pause_3insn_patch;
187818cd DM	354	while (p < &__pause_3insn_patch_end) {
e9b9eb59 DM	355	unsigned long i, addr = p->addr;
	356
	357	for (i = 0; i < 3; i++) {
	358	(unsigned int ) (addr + (i * 4)) = p->insns[i];
	359	wmb();
	360	__asm__ __volatile__("flush %0"
	361	: : "r" (addr + (i * 4)));
	362	}
	363
	364	p++;
	365	}
	366	}
	367
ef3e035c	368	void __init start_early_boot(void)
951bc82c	369	{
ef3e035c DM	370	int cpu;
	371
	372	check_if_starfire();
	373	per_cpu_patch();
	374	sun4v_patch();
8536e02e	375	smp_init_cpu_poke();
ef3e035c DM	376
	377	cpu = hard_smp_processor_id();
	378	if (cpu >= NR_CPUS) {
	379	prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n",
	380	cpu, NR_CPUS);
	381	prom_halt();
	382	}
	383	current_thread_info()->cpu = cpu;
	384
83e8eb99	385	time_init_early();
ef3e035c DM	386	prom_init_report();
ef3e035c DM	387	start_kernel();
951bc82c	388	}
951bc82c	389
ac85fe8b DM	390	/* On Ultra, we support all of the v8 capabilities. */
	391	unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH \| HWCAP_SPARC_STBAR \|
	392	HWCAP_SPARC_SWAP \| HWCAP_SPARC_MULDIV \|
	393	HWCAP_SPARC_V9);
	394	EXPORT_SYMBOL(sparc64_elf_hwcap);
	395
	396	static const char *hwcaps[] = {
	397	"flush", "stbar", "swap", "muldiv", "v9",
	398	"ultra3", "blkinit", "n2",
	399
	400	/* These strings are as they appear in the machine description
	401	* 'hwcap-list' property for cpu nodes.
	402	*/
	403	"mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2",
	404	"ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau",
82924e54 KA	405	"ima", "cspare", "pause", "cbcond", NULL /reserved for crypto /,
82924e54 KA	406	"adp",
6f859c0e DM	407	};
	408
	409	static const char *crypto_hwcaps[] = {
	410	"aes", "des", "kasumi", "camellia", "md5", "sha1", "sha256",
	411	"sha512", "mpmul", "montmul", "montsqr", "crc32c",
ac85fe8b DM	412	};
	413
	414	void cpucap_info(struct seq_file *m)
	415	{
	416	unsigned long caps = sparc64_elf_hwcap;
	417	int i, printed = 0;
	418
	419	seq_puts(m, "cpucaps\t\t: ");
	420	for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
	421	unsigned long bit = 1UL << i;
82924e54	422	if (hwcaps[i] && (caps & bit)) {
ac85fe8b DM	423	seq_printf(m, "%s%s",
	424	printed ? "," : "", hwcaps[i]);
	425	printed++;
	426	}
	427	}
6f859c0e DM	428	if (caps & HWCAP_SPARC_CRYPTO) {
	429	unsigned long cfr;
	430
	431	__asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
	432	for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
	433	unsigned long bit = 1UL << i;
	434	if (cfr & bit) {
	435	seq_printf(m, "%s%s",
	436	printed ? "," : "", crypto_hwcaps[i]);
	437	printed++;
	438	}
	439	}
	440	}
ac85fe8b DM	441	seq_putc(m, '\n');
	442	}
	443
6f859c0e DM	444	static void __init report_one_hwcap(int printed, const char name)
	445	{
	446	if ((*printed) == 0)
	447	printk(KERN_INFO "CPU CAPS: [");
	448	printk(KERN_CONT "%s%s",
	449	(*printed) ? "," : "", name);
	450	if (++(*printed) == 8) {
	451	printk(KERN_CONT "]\n");
	452	*printed = 0;
	453	}
	454	}
	455
	456	static void __init report_crypto_hwcaps(int *printed)
	457	{
	458	unsigned long cfr;
	459	int i;
	460
	461	__asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
	462
	463	for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
	464	unsigned long bit = 1UL << i;
	465	if (cfr & bit)
	466	report_one_hwcap(printed, crypto_hwcaps[i]);
	467	}
	468	}
	469
ac85fe8b DM	470	static void __init report_hwcaps(unsigned long caps)
	471	{
	472	int i, printed = 0;
	473
ac85fe8b DM	474	for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
ac85fe8b DM	475	unsigned long bit = 1UL << i;
82924e54	476	if (hwcaps[i] && (caps & bit))
6f859c0e	477	report_one_hwcap(&printed, hwcaps[i]);
ac85fe8b	478	}
6f859c0e DM	479	if (caps & HWCAP_SPARC_CRYPTO)
	480	report_crypto_hwcaps(&printed);
	481	if (printed != 0)
	482	printk(KERN_CONT "]\n");
ac85fe8b DM	483	}
	484
	485	static unsigned long __init mdesc_cpu_hwcap_list(void)
	486	{
	487	struct mdesc_handle *hp;
	488	unsigned long caps = 0;
	489	const char *prop;
	490	int len;
	491	u64 pn;
	492
	493	hp = mdesc_grab();
	494	if (!hp)
	495	return 0;
	496
	497	pn = mdesc_node_by_name(hp, MDESC_NODE_NULL, "cpu");
	498	if (pn == MDESC_NODE_NULL)
	499	goto out;
	500
	501	prop = mdesc_get_property(hp, pn, "hwcap-list", &len);
	502	if (!prop)
	503	goto out;
	504
	505	while (len) {
	506	int i, plen;
	507
	508	for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
	509	unsigned long bit = 1UL << i;
	510
82924e54	511	if (hwcaps[i] && !strcmp(prop, hwcaps[i])) {
ac85fe8b DM	512	caps \|= bit;
	513	break;
	514	}
	515	}
6f859c0e DM	516	for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
	517	if (!strcmp(prop, crypto_hwcaps[i]))
	518	caps \|= HWCAP_SPARC_CRYPTO;
	519	}
ac85fe8b DM	520
	521	plen = strlen(prop) + 1;
	522	prop += plen;
	523	len -= plen;
	524	}
	525
	526	out:
	527	mdesc_release(hp);
	528	return caps;
	529	}
	530
	531	/* This yields a mask that user programs can use to figure out what
	532	* instruction set this cpu supports.
	533	*/
	534	static void __init init_sparc64_elf_hwcap(void)
	535	{
	536	unsigned long cap = sparc64_elf_hwcap;
	537	unsigned long mdesc_caps;
	538
	539	if (tlb_type == cheetah \|\| tlb_type == cheetah_plus)
	540	cap \|= HWCAP_SPARC_ULTRA3;
	541	else if (tlb_type == hypervisor) {
	542	if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 \|\|
	543	sun4v_chip_type == SUN4V_CHIP_NIAGARA2 \|\|
08cefa9f DM	544	sun4v_chip_type == SUN4V_CHIP_NIAGARA3 \|\|
08cefa9f DM	545	sun4v_chip_type == SUN4V_CHIP_NIAGARA4 \|\|
4e963779	546	sun4v_chip_type == SUN4V_CHIP_NIAGARA5 \|\|
40831625 AP	547	sun4v_chip_type == SUN4V_CHIP_SPARC_M6 \|\|
40831625 AP	548	sun4v_chip_type == SUN4V_CHIP_SPARC_M7 \|\|
7d484acb	549	sun4v_chip_type == SUN4V_CHIP_SPARC_M8 \|\|
c5b8b5be	550	sun4v_chip_type == SUN4V_CHIP_SPARC_SN \|\|
4e963779	551	sun4v_chip_type == SUN4V_CHIP_SPARC64X)
ac85fe8b DM	552	cap \|= HWCAP_SPARC_BLKINIT;
ac85fe8b DM	553	if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 \|\|
08cefa9f DM	554	sun4v_chip_type == SUN4V_CHIP_NIAGARA3 \|\|
08cefa9f DM	555	sun4v_chip_type == SUN4V_CHIP_NIAGARA4 \|\|
4e963779	556	sun4v_chip_type == SUN4V_CHIP_NIAGARA5 \|\|
40831625 AP	557	sun4v_chip_type == SUN4V_CHIP_SPARC_M6 \|\|
40831625 AP	558	sun4v_chip_type == SUN4V_CHIP_SPARC_M7 \|\|
7d484acb	559	sun4v_chip_type == SUN4V_CHIP_SPARC_M8 \|\|
c5b8b5be	560	sun4v_chip_type == SUN4V_CHIP_SPARC_SN \|\|
4e963779	561	sun4v_chip_type == SUN4V_CHIP_SPARC64X)
ac85fe8b DM	562	cap \|= HWCAP_SPARC_N2;
	563	}
	564
	565	cap \|= (AV_SPARC_MUL32 \| AV_SPARC_DIV32 \| AV_SPARC_V8PLUS);
	566
	567	mdesc_caps = mdesc_cpu_hwcap_list();
	568	if (!mdesc_caps) {
	569	if (tlb_type == spitfire)
	570	cap \|= AV_SPARC_VIS;
	571	if (tlb_type == cheetah \|\| tlb_type == cheetah_plus)
	572	cap \|= AV_SPARC_VIS \| AV_SPARC_VIS2;
1a8e0da5 DM	573	if (tlb_type == cheetah_plus) {
	574	unsigned long impl, ver;
	575
	576	__asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
	577	impl = ((ver >> 32) & 0xffff);
	578	if (impl == PANTHER_IMPL)
	579	cap \|= AV_SPARC_POPC;
	580	}
ac85fe8b DM	581	if (tlb_type == hypervisor) {
	582	if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1)
	583	cap \|= AV_SPARC_ASI_BLK_INIT;
	584	if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 \|\|
08cefa9f DM	585	sun4v_chip_type == SUN4V_CHIP_NIAGARA3 \|\|
08cefa9f DM	586	sun4v_chip_type == SUN4V_CHIP_NIAGARA4 \|\|
4e963779	587	sun4v_chip_type == SUN4V_CHIP_NIAGARA5 \|\|
40831625 AP	588	sun4v_chip_type == SUN4V_CHIP_SPARC_M6 \|\|
40831625 AP	589	sun4v_chip_type == SUN4V_CHIP_SPARC_M7 \|\|
7d484acb	590	sun4v_chip_type == SUN4V_CHIP_SPARC_M8 \|\|
c5b8b5be	591	sun4v_chip_type == SUN4V_CHIP_SPARC_SN \|\|
4e963779	592	sun4v_chip_type == SUN4V_CHIP_SPARC64X)
ac85fe8b DM	593	cap \|= (AV_SPARC_VIS \| AV_SPARC_VIS2 \|
	594	AV_SPARC_ASI_BLK_INIT \|
	595	AV_SPARC_POPC);
08cefa9f DM	596	if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 \|\|
08cefa9f DM	597	sun4v_chip_type == SUN4V_CHIP_NIAGARA4 \|\|
4e963779	598	sun4v_chip_type == SUN4V_CHIP_NIAGARA5 \|\|
40831625 AP	599	sun4v_chip_type == SUN4V_CHIP_SPARC_M6 \|\|
40831625 AP	600	sun4v_chip_type == SUN4V_CHIP_SPARC_M7 \|\|
7d484acb	601	sun4v_chip_type == SUN4V_CHIP_SPARC_M8 \|\|
c5b8b5be	602	sun4v_chip_type == SUN4V_CHIP_SPARC_SN \|\|
4e963779	603	sun4v_chip_type == SUN4V_CHIP_SPARC64X)
ac85fe8b DM	604	cap \|= (AV_SPARC_VIS3 \| AV_SPARC_HPC \|
	605	AV_SPARC_FMAF);
	606	}
	607	}
	608	sparc64_elf_hwcap = cap \| mdesc_caps;
	609
	610	report_hwcaps(sparc64_elf_hwcap);
ef7c4d46 DM	611
	612	if (sparc64_elf_hwcap & AV_SPARC_POPC)
	613	popc_patch();
e9b9eb59 DM	614	if (sparc64_elf_hwcap & AV_SPARC_PAUSE)
e9b9eb59 DM	615	pause_patch();
ac85fe8b DM	616	}
ac85fe8b DM	617
ebb99a4c AP	618	void __init alloc_irqstack_bootmem(void)
	619	{
	620	unsigned int i, node;
	621
	622	for_each_possible_cpu(i) {
	623	node = cpu_to_node(i);
	624
ccfa2a0f MR	625	softirq_stack[i] = memblock_alloc_node(THREAD_SIZE,
	626	THREAD_SIZE, node);
	627	hardirq_stack[i] = memblock_alloc_node(THREAD_SIZE,
	628	THREAD_SIZE, node);
ebb99a4c AP	629	}
	630	}
	631
1da177e4 LT	632	void __init setup_arch(char **cmdline_p)
1da177e4 LT	633	{
1da177e4 LT	634	/* Initialize PROM console and command line. */
1da177e4 LT	635	*cmdline_p = prom_getbootargs();
117a0c5f	636	strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
ce3b1d47	637	parse_early_param();
1da177e4	638
3c62a2d3	639	boot_flags_init(*cmdline_p);
c57ec52f DM	640	#ifdef CONFIG_EARLYFB
	641	if (btext_find_display())
	642	#endif
	643	register_console(&prom_early_console);
3c62a2d3	644
3a8c069d DM	645	if (tlb_type == hypervisor)
	646	printk("ARCH: SUN4V\n");
	647	else
	648	printk("ARCH: SUN4U\n");
1da177e4 LT	649
	650	#ifdef CONFIG_DUMMY_CONSOLE
	651	conswitchp = &dummy_con;
1da177e4 LT	652	#endif
1da177e4 LT	653
1da177e4	654	idprom_init();
1da177e4 LT	655
	656	if (!root_flags)
	657	root_mountflags &= ~MS_RDONLY;
	658	ROOT_DEV = old_decode_dev(root_dev);
467418f3	659	#ifdef CONFIG_BLK_DEV_RAM
1da177e4 LT	660	rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK;
1da177e4 LT	661	rd_prompt = ((ram_flags & RAMDISK_PROMPT_FLAG) != 0);
68a79217	662	rd_doload = ((ram_flags & RAMDISK_LOAD_FLAG) != 0);
1da177e4 LT	663	#endif
1da177e4 LT	664
f3169641	665	task_thread_info(&init_task)->kregs = &fake_swapper_regs;
1da177e4 LT	666
	667	#ifdef CONFIG_IP_PNP
	668	if (!ic_set_manually) {
8d125562	669	phandle chosen = prom_finddevice("/chosen");
1da177e4	670	u32 cl, sv, gw;
68a79217	671
1da177e4 LT	672	cl = prom_getintdefault (chosen, "client-ip", 0);
	673	sv = prom_getintdefault (chosen, "server-ip", 0);
	674	gw = prom_getintdefault (chosen, "gateway-ip", 0);
	675	if (cl && sv) {
	676	ic_myaddr = cl;
	677	ic_servaddr = sv;
	678	if (gw)
	679	ic_gateway = gw;
	680	#if defined(CONFIG_IP_PNP_BOOTP) \|\| defined(CONFIG_IP_PNP_RARP)
	681	ic_proto_enabled = 0;
	682	#endif
	683	}
	684	}
	685	#endif
	686
56fb4df6	687	/* Get boot processor trap_block[] setup. */
72aff53f	688	init_cur_cpu_trap(current_thread_info());
52845cdb DM	689
52845cdb DM	690	paging_init();
ac85fe8b	691	init_sparc64_elf_hwcap();
9b2f753e	692	smp_fill_in_cpu_possible_map();
ebb99a4c AP	693	/*
	694	* Once the OF device tree and MDESC have been setup and nr_cpus has
	695	* been parsed, we know the list of possible cpus. Therefore we can
	696	* allocate the IRQ stacks.
	697	*/
	698	alloc_irqstack_bootmem();
1da177e4 LT	699	}
1da177e4 LT	700
1da177e4 LT	701	extern int stop_a_enabled;
	702
	703	void sun_do_break(void)
	704	{
	705	if (!stop_a_enabled)
	706	return;
	707
	708	prom_printf("\n");
	709	flush_user_windows();
	710
	711	prom_cmdline();
	712	}
917c3660	713	EXPORT_SYMBOL(sun_do_break);
1da177e4	714
1da177e4	715	int stop_a_enabled = 1;
917c3660	716	EXPORT_SYMBOL(stop_a_enabled);