Commit | Line | Data |
---|---|---|
b00dc837 | 1 | /* |
1da177e4 LT |
2 | * linux/arch/sparc64/kernel/setup.c |
3 | * | |
4 | * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu) | |
5 | * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz) | |
6 | */ | |
7 | ||
8 | #include <linux/errno.h> | |
9 | #include <linux/sched.h> | |
10 | #include <linux/kernel.h> | |
11 | #include <linux/mm.h> | |
12 | #include <linux/stddef.h> | |
13 | #include <linux/unistd.h> | |
14 | #include <linux/ptrace.h> | |
1da177e4 LT |
15 | #include <asm/smp.h> |
16 | #include <linux/user.h> | |
894673ee | 17 | #include <linux/screen_info.h> |
1da177e4 | 18 | #include <linux/delay.h> |
1da177e4 LT |
19 | #include <linux/fs.h> |
20 | #include <linux/seq_file.h> | |
21 | #include <linux/syscalls.h> | |
22 | #include <linux/kdev_t.h> | |
23 | #include <linux/major.h> | |
24 | #include <linux/string.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/inet.h> | |
27 | #include <linux/console.h> | |
28 | #include <linux/root_dev.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/cpu.h> | |
31 | #include <linux/initrd.h> | |
ac85fe8b | 32 | #include <linux/module.h> |
ef3e035c | 33 | #include <linux/start_kernel.h> |
1da177e4 | 34 | |
1da177e4 LT |
35 | #include <asm/io.h> |
36 | #include <asm/processor.h> | |
37 | #include <asm/oplib.h> | |
38 | #include <asm/page.h> | |
39 | #include <asm/pgtable.h> | |
40 | #include <asm/idprom.h> | |
41 | #include <asm/head.h> | |
42 | #include <asm/starfire.h> | |
43 | #include <asm/mmu_context.h> | |
44 | #include <asm/timer.h> | |
45 | #include <asm/sections.h> | |
46 | #include <asm/setup.h> | |
47 | #include <asm/mmu.h> | |
5cbc3073 | 48 | #include <asm/ns87303.h> |
c57ec52f | 49 | #include <asm/btext.h> |
ac85fe8b DM |
50 | #include <asm/elf.h> |
51 | #include <asm/mdesc.h> | |
d550bbd4 | 52 | #include <asm/cacheflush.h> |
1da177e4 LT |
53 | |
54 | #ifdef CONFIG_IP_PNP | |
55 | #include <net/ipconfig.h> | |
56 | #endif | |
57 | ||
3d5ae6b6 | 58 | #include "entry.h" |
53ae3419 | 59 | #include "kernel.h" |
3d5ae6b6 | 60 | |
5cbc3073 DM |
61 | /* Used to synchronize accesses to NatSemi SUPER I/O chip configure |
62 | * operations in asm/ns87303.h | |
63 | */ | |
64 | DEFINE_SPINLOCK(ns87303_lock); | |
917c3660 | 65 | EXPORT_SYMBOL(ns87303_lock); |
5cbc3073 | 66 | |
1da177e4 LT |
67 | struct screen_info screen_info = { |
68 | 0, 0, /* orig-x, orig-y */ | |
69 | 0, /* unused */ | |
70 | 0, /* orig-video-page */ | |
71 | 0, /* orig-video-mode */ | |
72 | 128, /* orig-video-cols */ | |
73 | 0, 0, 0, /* unused, ega_bx, unused */ | |
74 | 54, /* orig-video-lines */ | |
75 | 0, /* orig-video-isVGA */ | |
76 | 16 /* orig-video-points */ | |
77 | }; | |
78 | ||
1da177e4 | 79 | static void |
9ef595d8 | 80 | prom_console_write(struct console *con, const char *s, unsigned int n) |
1da177e4 LT |
81 | { |
82 | prom_write(s, n); | |
83 | } | |
84 | ||
1da177e4 LT |
85 | /* Exported for mm/init.c:paging_init. */ |
86 | unsigned long cmdline_memory_size = 0; | |
87 | ||
3c62a2d3 DM |
88 | static struct console prom_early_console = { |
89 | .name = "earlyprom", | |
1da177e4 | 90 | .write = prom_console_write, |
db9a7fb1 | 91 | .flags = CON_PRINTBUFFER | CON_BOOT | CON_ANYTIME, |
1da177e4 LT |
92 | .index = -1, |
93 | }; | |
94 | ||
1da177e4 LT |
95 | /* |
96 | * Process kernel command line switches that are specific to the | |
97 | * SPARC or that require special low-level processing. | |
98 | */ | |
99 | static void __init process_switch(char c) | |
100 | { | |
101 | switch (c) { | |
102 | case 'd': | |
1da177e4 | 103 | case 's': |
1da177e4 LT |
104 | break; |
105 | case 'h': | |
106 | prom_printf("boot_flags_init: Halt!\n"); | |
107 | prom_halt(); | |
108 | break; | |
109 | case 'p': | |
11032c17 | 110 | prom_early_console.flags &= ~CON_BOOT; |
1da177e4 | 111 | break; |
816242da DM |
112 | case 'P': |
113 | /* Force UltraSPARC-III P-Cache on. */ | |
114 | if (tlb_type != cheetah) { | |
115 | printk("BOOT: Ignoring P-Cache force option.\n"); | |
116 | break; | |
117 | } | |
118 | cheetah_pcache_forced_on = 1; | |
373d4d09 | 119 | add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); |
816242da DM |
120 | cheetah_enable_pcache(); |
121 | break; | |
122 | ||
1da177e4 LT |
123 | default: |
124 | printk("Unknown boot switch (-%c)\n", c); | |
125 | break; | |
126 | } | |
127 | } | |
128 | ||
1da177e4 LT |
129 | static void __init boot_flags_init(char *commands) |
130 | { | |
131 | while (*commands) { | |
132 | /* Move to the start of the next "argument". */ | |
133 | while (*commands && *commands == ' ') | |
134 | commands++; | |
135 | ||
136 | /* Process any command switches, otherwise skip it. */ | |
137 | if (*commands == '\0') | |
138 | break; | |
139 | if (*commands == '-') { | |
140 | commands++; | |
141 | while (*commands && *commands != ' ') | |
142 | process_switch(*commands++); | |
143 | continue; | |
144 | } | |
7c21d533 | 145 | if (!strncmp(commands, "mem=", 4)) |
146 | cmdline_memory_size = memparse(commands + 4, &commands); | |
147 | ||
1da177e4 LT |
148 | while (*commands && *commands != ' ') |
149 | commands++; | |
150 | } | |
151 | } | |
152 | ||
1da177e4 LT |
153 | extern unsigned short root_flags; |
154 | extern unsigned short root_dev; | |
155 | extern unsigned short ram_flags; | |
156 | #define RAMDISK_IMAGE_START_MASK 0x07FF | |
157 | #define RAMDISK_PROMPT_FLAG 0x8000 | |
158 | #define RAMDISK_LOAD_FLAG 0x4000 | |
159 | ||
160 | extern int root_mountflags; | |
161 | ||
162 | char reboot_command[COMMAND_LINE_SIZE]; | |
163 | ||
164 | static struct pt_regs fake_swapper_regs = { { 0, }, 0, 0, 0, 0 }; | |
165 | ||
ef3e035c | 166 | static void __init per_cpu_patch(void) |
92704a1c | 167 | { |
92704a1c DM |
168 | struct cpuid_patch_entry *p; |
169 | unsigned long ver; | |
170 | int is_jbus; | |
171 | ||
172 | if (tlb_type == spitfire && !this_is_starfire) | |
173 | return; | |
174 | ||
d82ace7d DM |
175 | is_jbus = 0; |
176 | if (tlb_type != hypervisor) { | |
177 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
ebd8c56c DM |
178 | is_jbus = ((ver >> 32UL) == __JALAPENO_ID || |
179 | (ver >> 32UL) == __SERRANO_ID); | |
d82ace7d | 180 | } |
92704a1c DM |
181 | |
182 | p = &__cpuid_patch; | |
183 | while (p < &__cpuid_patch_end) { | |
184 | unsigned long addr = p->addr; | |
185 | unsigned int *insns; | |
186 | ||
187 | switch (tlb_type) { | |
188 | case spitfire: | |
189 | insns = &p->starfire[0]; | |
190 | break; | |
191 | case cheetah: | |
192 | case cheetah_plus: | |
193 | if (is_jbus) | |
194 | insns = &p->cheetah_jbus[0]; | |
195 | else | |
196 | insns = &p->cheetah_safari[0]; | |
197 | break; | |
d96b8153 DM |
198 | case hypervisor: |
199 | insns = &p->sun4v[0]; | |
200 | break; | |
92704a1c DM |
201 | default: |
202 | prom_printf("Unknown cpu type, halting.\n"); | |
203 | prom_halt(); | |
6cb79b3f | 204 | } |
92704a1c DM |
205 | |
206 | *(unsigned int *) (addr + 0) = insns[0]; | |
840aaef8 | 207 | wmb(); |
92704a1c DM |
208 | __asm__ __volatile__("flush %0" : : "r" (addr + 0)); |
209 | ||
210 | *(unsigned int *) (addr + 4) = insns[1]; | |
840aaef8 | 211 | wmb(); |
92704a1c DM |
212 | __asm__ __volatile__("flush %0" : : "r" (addr + 4)); |
213 | ||
214 | *(unsigned int *) (addr + 8) = insns[2]; | |
840aaef8 | 215 | wmb(); |
92704a1c DM |
216 | __asm__ __volatile__("flush %0" : : "r" (addr + 8)); |
217 | ||
218 | *(unsigned int *) (addr + 12) = insns[3]; | |
840aaef8 | 219 | wmb(); |
92704a1c DM |
220 | __asm__ __volatile__("flush %0" : : "r" (addr + 12)); |
221 | ||
222 | p++; | |
223 | } | |
92704a1c DM |
224 | } |
225 | ||
0b64120c DM |
226 | void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *start, |
227 | struct sun4v_1insn_patch_entry *end) | |
936f482a | 228 | { |
0b64120c DM |
229 | while (start < end) { |
230 | unsigned long addr = start->addr; | |
936f482a | 231 | |
0b64120c | 232 | *(unsigned int *) (addr + 0) = start->insn; |
840aaef8 | 233 | wmb(); |
936f482a DM |
234 | __asm__ __volatile__("flush %0" : : "r" (addr + 0)); |
235 | ||
0b64120c | 236 | start++; |
45fec05f | 237 | } |
0b64120c | 238 | } |
45fec05f | 239 | |
0b64120c DM |
240 | void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *start, |
241 | struct sun4v_2insn_patch_entry *end) | |
242 | { | |
243 | while (start < end) { | |
244 | unsigned long addr = start->addr; | |
45fec05f | 245 | |
0b64120c | 246 | *(unsigned int *) (addr + 0) = start->insns[0]; |
840aaef8 | 247 | wmb(); |
45fec05f DM |
248 | __asm__ __volatile__("flush %0" : : "r" (addr + 0)); |
249 | ||
0b64120c | 250 | *(unsigned int *) (addr + 4) = start->insns[1]; |
840aaef8 | 251 | wmb(); |
45fec05f DM |
252 | __asm__ __volatile__("flush %0" : : "r" (addr + 4)); |
253 | ||
0b64120c | 254 | start++; |
936f482a | 255 | } |
0b64120c DM |
256 | } |
257 | ||
494e5b6f KA |
258 | void sun_m7_patch_2insn_range(struct sun4v_2insn_patch_entry *start, |
259 | struct sun4v_2insn_patch_entry *end) | |
260 | { | |
261 | while (start < end) { | |
262 | unsigned long addr = start->addr; | |
263 | ||
264 | *(unsigned int *) (addr + 0) = start->insns[0]; | |
265 | wmb(); | |
266 | __asm__ __volatile__("flush %0" : : "r" (addr + 0)); | |
267 | ||
268 | *(unsigned int *) (addr + 4) = start->insns[1]; | |
269 | wmb(); | |
270 | __asm__ __volatile__("flush %0" : : "r" (addr + 4)); | |
271 | ||
272 | start++; | |
273 | } | |
274 | } | |
275 | ||
ef3e035c | 276 | static void __init sun4v_patch(void) |
0b64120c DM |
277 | { |
278 | extern void sun4v_hvapi_init(void); | |
279 | ||
280 | if (tlb_type != hypervisor) | |
281 | return; | |
282 | ||
283 | sun4v_patch_1insn_range(&__sun4v_1insn_patch, | |
284 | &__sun4v_1insn_patch_end); | |
285 | ||
286 | sun4v_patch_2insn_range(&__sun4v_2insn_patch, | |
287 | &__sun4v_2insn_patch_end); | |
c5b8b5be KA |
288 | if (sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || |
289 | sun4v_chip_type == SUN4V_CHIP_SPARC_SN) | |
494e5b6f KA |
290 | sun_m7_patch_2insn_range(&__sun_m7_2insn_patch, |
291 | &__sun_m7_2insn_patch_end); | |
c7754d46 DM |
292 | |
293 | sun4v_hvapi_init(); | |
936f482a DM |
294 | } |
295 | ||
ef7c4d46 DM |
296 | static void __init popc_patch(void) |
297 | { | |
298 | struct popc_3insn_patch_entry *p3; | |
56d205cc | 299 | struct popc_6insn_patch_entry *p6; |
ef7c4d46 DM |
300 | |
301 | p3 = &__popc_3insn_patch; | |
302 | while (p3 < &__popc_3insn_patch_end) { | |
56d205cc | 303 | unsigned long i, addr = p3->addr; |
ef7c4d46 | 304 | |
56d205cc DM |
305 | for (i = 0; i < 3; i++) { |
306 | *(unsigned int *) (addr + (i * 4)) = p3->insns[i]; | |
307 | wmb(); | |
308 | __asm__ __volatile__("flush %0" | |
309 | : : "r" (addr + (i * 4))); | |
310 | } | |
ef7c4d46 | 311 | |
56d205cc DM |
312 | p3++; |
313 | } | |
ef7c4d46 | 314 | |
56d205cc DM |
315 | p6 = &__popc_6insn_patch; |
316 | while (p6 < &__popc_6insn_patch_end) { | |
317 | unsigned long i, addr = p6->addr; | |
ef7c4d46 | 318 | |
56d205cc DM |
319 | for (i = 0; i < 6; i++) { |
320 | *(unsigned int *) (addr + (i * 4)) = p6->insns[i]; | |
321 | wmb(); | |
322 | __asm__ __volatile__("flush %0" | |
323 | : : "r" (addr + (i * 4))); | |
324 | } | |
325 | ||
326 | p6++; | |
ef7c4d46 DM |
327 | } |
328 | } | |
329 | ||
e9b9eb59 DM |
330 | static void __init pause_patch(void) |
331 | { | |
332 | struct pause_patch_entry *p; | |
333 | ||
187818cd DM |
334 | p = &__pause_3insn_patch; |
335 | while (p < &__pause_3insn_patch_end) { | |
e9b9eb59 DM |
336 | unsigned long i, addr = p->addr; |
337 | ||
338 | for (i = 0; i < 3; i++) { | |
339 | *(unsigned int *) (addr + (i * 4)) = p->insns[i]; | |
340 | wmb(); | |
341 | __asm__ __volatile__("flush %0" | |
342 | : : "r" (addr + (i * 4))); | |
343 | } | |
344 | ||
345 | p++; | |
346 | } | |
347 | } | |
348 | ||
ef3e035c | 349 | void __init start_early_boot(void) |
951bc82c | 350 | { |
ef3e035c DM |
351 | int cpu; |
352 | ||
353 | check_if_starfire(); | |
354 | per_cpu_patch(); | |
355 | sun4v_patch(); | |
356 | ||
357 | cpu = hard_smp_processor_id(); | |
358 | if (cpu >= NR_CPUS) { | |
359 | prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n", | |
360 | cpu, NR_CPUS); | |
361 | prom_halt(); | |
362 | } | |
363 | current_thread_info()->cpu = cpu; | |
364 | ||
365 | prom_init_report(); | |
366 | start_kernel(); | |
951bc82c | 367 | } |
951bc82c | 368 | |
ac85fe8b DM |
369 | /* On Ultra, we support all of the v8 capabilities. */ |
370 | unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | | |
371 | HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV | | |
372 | HWCAP_SPARC_V9); | |
373 | EXPORT_SYMBOL(sparc64_elf_hwcap); | |
374 | ||
375 | static const char *hwcaps[] = { | |
376 | "flush", "stbar", "swap", "muldiv", "v9", | |
377 | "ultra3", "blkinit", "n2", | |
378 | ||
379 | /* These strings are as they appear in the machine description | |
380 | * 'hwcap-list' property for cpu nodes. | |
381 | */ | |
382 | "mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2", | |
383 | "ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau", | |
82924e54 KA |
384 | "ima", "cspare", "pause", "cbcond", NULL /*reserved for crypto */, |
385 | "adp", | |
6f859c0e DM |
386 | }; |
387 | ||
388 | static const char *crypto_hwcaps[] = { | |
389 | "aes", "des", "kasumi", "camellia", "md5", "sha1", "sha256", | |
390 | "sha512", "mpmul", "montmul", "montsqr", "crc32c", | |
ac85fe8b DM |
391 | }; |
392 | ||
393 | void cpucap_info(struct seq_file *m) | |
394 | { | |
395 | unsigned long caps = sparc64_elf_hwcap; | |
396 | int i, printed = 0; | |
397 | ||
398 | seq_puts(m, "cpucaps\t\t: "); | |
399 | for (i = 0; i < ARRAY_SIZE(hwcaps); i++) { | |
400 | unsigned long bit = 1UL << i; | |
82924e54 | 401 | if (hwcaps[i] && (caps & bit)) { |
ac85fe8b DM |
402 | seq_printf(m, "%s%s", |
403 | printed ? "," : "", hwcaps[i]); | |
404 | printed++; | |
405 | } | |
406 | } | |
6f859c0e DM |
407 | if (caps & HWCAP_SPARC_CRYPTO) { |
408 | unsigned long cfr; | |
409 | ||
410 | __asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr)); | |
411 | for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) { | |
412 | unsigned long bit = 1UL << i; | |
413 | if (cfr & bit) { | |
414 | seq_printf(m, "%s%s", | |
415 | printed ? "," : "", crypto_hwcaps[i]); | |
416 | printed++; | |
417 | } | |
418 | } | |
419 | } | |
ac85fe8b DM |
420 | seq_putc(m, '\n'); |
421 | } | |
422 | ||
6f859c0e DM |
423 | static void __init report_one_hwcap(int *printed, const char *name) |
424 | { | |
425 | if ((*printed) == 0) | |
426 | printk(KERN_INFO "CPU CAPS: ["); | |
427 | printk(KERN_CONT "%s%s", | |
428 | (*printed) ? "," : "", name); | |
429 | if (++(*printed) == 8) { | |
430 | printk(KERN_CONT "]\n"); | |
431 | *printed = 0; | |
432 | } | |
433 | } | |
434 | ||
435 | static void __init report_crypto_hwcaps(int *printed) | |
436 | { | |
437 | unsigned long cfr; | |
438 | int i; | |
439 | ||
440 | __asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr)); | |
441 | ||
442 | for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) { | |
443 | unsigned long bit = 1UL << i; | |
444 | if (cfr & bit) | |
445 | report_one_hwcap(printed, crypto_hwcaps[i]); | |
446 | } | |
447 | } | |
448 | ||
ac85fe8b DM |
449 | static void __init report_hwcaps(unsigned long caps) |
450 | { | |
451 | int i, printed = 0; | |
452 | ||
ac85fe8b DM |
453 | for (i = 0; i < ARRAY_SIZE(hwcaps); i++) { |
454 | unsigned long bit = 1UL << i; | |
82924e54 | 455 | if (hwcaps[i] && (caps & bit)) |
6f859c0e | 456 | report_one_hwcap(&printed, hwcaps[i]); |
ac85fe8b | 457 | } |
6f859c0e DM |
458 | if (caps & HWCAP_SPARC_CRYPTO) |
459 | report_crypto_hwcaps(&printed); | |
460 | if (printed != 0) | |
461 | printk(KERN_CONT "]\n"); | |
ac85fe8b DM |
462 | } |
463 | ||
464 | static unsigned long __init mdesc_cpu_hwcap_list(void) | |
465 | { | |
466 | struct mdesc_handle *hp; | |
467 | unsigned long caps = 0; | |
468 | const char *prop; | |
469 | int len; | |
470 | u64 pn; | |
471 | ||
472 | hp = mdesc_grab(); | |
473 | if (!hp) | |
474 | return 0; | |
475 | ||
476 | pn = mdesc_node_by_name(hp, MDESC_NODE_NULL, "cpu"); | |
477 | if (pn == MDESC_NODE_NULL) | |
478 | goto out; | |
479 | ||
480 | prop = mdesc_get_property(hp, pn, "hwcap-list", &len); | |
481 | if (!prop) | |
482 | goto out; | |
483 | ||
484 | while (len) { | |
485 | int i, plen; | |
486 | ||
487 | for (i = 0; i < ARRAY_SIZE(hwcaps); i++) { | |
488 | unsigned long bit = 1UL << i; | |
489 | ||
82924e54 | 490 | if (hwcaps[i] && !strcmp(prop, hwcaps[i])) { |
ac85fe8b DM |
491 | caps |= bit; |
492 | break; | |
493 | } | |
494 | } | |
6f859c0e DM |
495 | for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) { |
496 | if (!strcmp(prop, crypto_hwcaps[i])) | |
497 | caps |= HWCAP_SPARC_CRYPTO; | |
498 | } | |
ac85fe8b DM |
499 | |
500 | plen = strlen(prop) + 1; | |
501 | prop += plen; | |
502 | len -= plen; | |
503 | } | |
504 | ||
505 | out: | |
506 | mdesc_release(hp); | |
507 | return caps; | |
508 | } | |
509 | ||
510 | /* This yields a mask that user programs can use to figure out what | |
511 | * instruction set this cpu supports. | |
512 | */ | |
513 | static void __init init_sparc64_elf_hwcap(void) | |
514 | { | |
515 | unsigned long cap = sparc64_elf_hwcap; | |
516 | unsigned long mdesc_caps; | |
517 | ||
518 | if (tlb_type == cheetah || tlb_type == cheetah_plus) | |
519 | cap |= HWCAP_SPARC_ULTRA3; | |
520 | else if (tlb_type == hypervisor) { | |
521 | if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || | |
522 | sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || | |
08cefa9f DM |
523 | sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || |
524 | sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || | |
4e963779 | 525 | sun4v_chip_type == SUN4V_CHIP_NIAGARA5 || |
40831625 AP |
526 | sun4v_chip_type == SUN4V_CHIP_SPARC_M6 || |
527 | sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || | |
c5b8b5be | 528 | sun4v_chip_type == SUN4V_CHIP_SPARC_SN || |
4e963779 | 529 | sun4v_chip_type == SUN4V_CHIP_SPARC64X) |
ac85fe8b DM |
530 | cap |= HWCAP_SPARC_BLKINIT; |
531 | if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || | |
08cefa9f DM |
532 | sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || |
533 | sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || | |
4e963779 | 534 | sun4v_chip_type == SUN4V_CHIP_NIAGARA5 || |
40831625 AP |
535 | sun4v_chip_type == SUN4V_CHIP_SPARC_M6 || |
536 | sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || | |
c5b8b5be | 537 | sun4v_chip_type == SUN4V_CHIP_SPARC_SN || |
4e963779 | 538 | sun4v_chip_type == SUN4V_CHIP_SPARC64X) |
ac85fe8b DM |
539 | cap |= HWCAP_SPARC_N2; |
540 | } | |
541 | ||
542 | cap |= (AV_SPARC_MUL32 | AV_SPARC_DIV32 | AV_SPARC_V8PLUS); | |
543 | ||
544 | mdesc_caps = mdesc_cpu_hwcap_list(); | |
545 | if (!mdesc_caps) { | |
546 | if (tlb_type == spitfire) | |
547 | cap |= AV_SPARC_VIS; | |
548 | if (tlb_type == cheetah || tlb_type == cheetah_plus) | |
549 | cap |= AV_SPARC_VIS | AV_SPARC_VIS2; | |
1a8e0da5 DM |
550 | if (tlb_type == cheetah_plus) { |
551 | unsigned long impl, ver; | |
552 | ||
553 | __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver)); | |
554 | impl = ((ver >> 32) & 0xffff); | |
555 | if (impl == PANTHER_IMPL) | |
556 | cap |= AV_SPARC_POPC; | |
557 | } | |
ac85fe8b DM |
558 | if (tlb_type == hypervisor) { |
559 | if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1) | |
560 | cap |= AV_SPARC_ASI_BLK_INIT; | |
561 | if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || | |
08cefa9f DM |
562 | sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || |
563 | sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || | |
4e963779 | 564 | sun4v_chip_type == SUN4V_CHIP_NIAGARA5 || |
40831625 AP |
565 | sun4v_chip_type == SUN4V_CHIP_SPARC_M6 || |
566 | sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || | |
c5b8b5be | 567 | sun4v_chip_type == SUN4V_CHIP_SPARC_SN || |
4e963779 | 568 | sun4v_chip_type == SUN4V_CHIP_SPARC64X) |
ac85fe8b DM |
569 | cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 | |
570 | AV_SPARC_ASI_BLK_INIT | | |
571 | AV_SPARC_POPC); | |
08cefa9f DM |
572 | if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || |
573 | sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || | |
4e963779 | 574 | sun4v_chip_type == SUN4V_CHIP_NIAGARA5 || |
40831625 AP |
575 | sun4v_chip_type == SUN4V_CHIP_SPARC_M6 || |
576 | sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || | |
c5b8b5be | 577 | sun4v_chip_type == SUN4V_CHIP_SPARC_SN || |
4e963779 | 578 | sun4v_chip_type == SUN4V_CHIP_SPARC64X) |
ac85fe8b DM |
579 | cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC | |
580 | AV_SPARC_FMAF); | |
581 | } | |
582 | } | |
583 | sparc64_elf_hwcap = cap | mdesc_caps; | |
584 | ||
585 | report_hwcaps(sparc64_elf_hwcap); | |
ef7c4d46 DM |
586 | |
587 | if (sparc64_elf_hwcap & AV_SPARC_POPC) | |
588 | popc_patch(); | |
e9b9eb59 DM |
589 | if (sparc64_elf_hwcap & AV_SPARC_PAUSE) |
590 | pause_patch(); | |
ac85fe8b DM |
591 | } |
592 | ||
1da177e4 LT |
593 | void __init setup_arch(char **cmdline_p) |
594 | { | |
1da177e4 LT |
595 | /* Initialize PROM console and command line. */ |
596 | *cmdline_p = prom_getbootargs(); | |
117a0c5f | 597 | strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE); |
ce3b1d47 | 598 | parse_early_param(); |
1da177e4 | 599 | |
3c62a2d3 | 600 | boot_flags_init(*cmdline_p); |
c57ec52f DM |
601 | #ifdef CONFIG_EARLYFB |
602 | if (btext_find_display()) | |
603 | #endif | |
604 | register_console(&prom_early_console); | |
3c62a2d3 | 605 | |
3a8c069d DM |
606 | if (tlb_type == hypervisor) |
607 | printk("ARCH: SUN4V\n"); | |
608 | else | |
609 | printk("ARCH: SUN4U\n"); | |
1da177e4 LT |
610 | |
611 | #ifdef CONFIG_DUMMY_CONSOLE | |
612 | conswitchp = &dummy_con; | |
1da177e4 LT |
613 | #endif |
614 | ||
1da177e4 | 615 | idprom_init(); |
1da177e4 LT |
616 | |
617 | if (!root_flags) | |
618 | root_mountflags &= ~MS_RDONLY; | |
619 | ROOT_DEV = old_decode_dev(root_dev); | |
467418f3 | 620 | #ifdef CONFIG_BLK_DEV_RAM |
1da177e4 LT |
621 | rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK; |
622 | rd_prompt = ((ram_flags & RAMDISK_PROMPT_FLAG) != 0); | |
623 | rd_doload = ((ram_flags & RAMDISK_LOAD_FLAG) != 0); | |
624 | #endif | |
625 | ||
f3169641 | 626 | task_thread_info(&init_task)->kregs = &fake_swapper_regs; |
1da177e4 LT |
627 | |
628 | #ifdef CONFIG_IP_PNP | |
629 | if (!ic_set_manually) { | |
8d125562 | 630 | phandle chosen = prom_finddevice("/chosen"); |
1da177e4 LT |
631 | u32 cl, sv, gw; |
632 | ||
633 | cl = prom_getintdefault (chosen, "client-ip", 0); | |
634 | sv = prom_getintdefault (chosen, "server-ip", 0); | |
635 | gw = prom_getintdefault (chosen, "gateway-ip", 0); | |
636 | if (cl && sv) { | |
637 | ic_myaddr = cl; | |
638 | ic_servaddr = sv; | |
639 | if (gw) | |
640 | ic_gateway = gw; | |
641 | #if defined(CONFIG_IP_PNP_BOOTP) || defined(CONFIG_IP_PNP_RARP) | |
642 | ic_proto_enabled = 0; | |
643 | #endif | |
644 | } | |
645 | } | |
646 | #endif | |
647 | ||
56fb4df6 | 648 | /* Get boot processor trap_block[] setup. */ |
72aff53f | 649 | init_cur_cpu_trap(current_thread_info()); |
52845cdb DM |
650 | |
651 | paging_init(); | |
ac85fe8b | 652 | init_sparc64_elf_hwcap(); |
1da177e4 LT |
653 | } |
654 | ||
1da177e4 LT |
655 | extern int stop_a_enabled; |
656 | ||
657 | void sun_do_break(void) | |
658 | { | |
659 | if (!stop_a_enabled) | |
660 | return; | |
661 | ||
662 | prom_printf("\n"); | |
663 | flush_user_windows(); | |
664 | ||
665 | prom_cmdline(); | |
666 | } | |
917c3660 | 667 | EXPORT_SYMBOL(sun_do_break); |
1da177e4 | 668 | |
1da177e4 | 669 | int stop_a_enabled = 1; |
917c3660 | 670 | EXPORT_SYMBOL(stop_a_enabled); |