[linux-2.6-block.git] / arch / sparc / kernel / rtrap_64.S

/*
 * rtrap.S: Preparing for return from trap on Sparc V9.
 *
 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
 */


#include <asm/asi.h>
#include <asm/pstate.h>
#include <asm/ptrace.h>
#include <asm/spitfire.h>
#include <asm/head.h>
#include <asm/visasm.h>
#include <asm/processor.h>

#ifdef CONFIG_CONTEXT_TRACKING
# define SCHEDULE_USER schedule_user
#else
# define SCHEDULE_USER schedule
#endif

		.text
		.align			32
__handle_preemption:
		call			SCHEDULE_USER
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		ba,pt			%xcc, __handle_preemption_continue
		 wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate

__handle_user_windows:
		call			fault_in_user_windows
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		ba,pt			%xcc, __handle_preemption_continue
		 wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate

__handle_userfpu:
		rd			%fprs, %l5
		andcc			%l5, FPRS_FEF, %g0
		sethi			%hi(TSTATE_PEF), %o0
		be,a,pn			%icc, __handle_userfpu_continue
		 andn			%l1, %o0, %l1
		ba,a,pt			%xcc, __handle_userfpu_continue

__handle_signal:
		mov			%l5, %o1
		add			%sp, PTREGS_OFF, %o0
		mov			%l0, %o2
		call			do_notify_resume
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate

		/* Signal delivery can modify pt_regs tstate, so we must
		 * reload it.
		 */
		ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
		sethi			%hi(0xf << 20), %l4
		and			%l1, %l4, %l4
		ba,pt			%xcc, __handle_preemption_continue
		 andn			%l1, %l4, %l1

		/* When returning from a NMI (%pil==15) interrupt we want to
		 * avoid running softirqs, doing IRQ tracing, preempting, etc.
		 */
		.globl			rtrap_nmi
rtrap_nmi:	ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
		sethi			%hi(0xf << 20), %l4
		and			%l1, %l4, %l4
		andn			%l1, %l4, %l1
		srl			%l4, 20, %l4
		ba,pt			%xcc, rtrap_no_irq_enable
		nop
		/* Do not actually set the %pil here.  We will do that
		 * below after we clear PSTATE_IE in the %pstate register.
		 * If we re-enable interrupts here, we can recurse down
		 * the hardirq stack potentially endlessly, causing a
		 * stack overflow.
		 */

		.align			64
		.globl			rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall
rtrap_irq:
rtrap:
		/* mm/ultra.S:xcall_report_regs KNOWS about this load. */
		ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
rtrap_xcall:
		sethi			%hi(0xf << 20), %l4
		and			%l1, %l4, %l4
		andn			%l1, %l4, %l1
		srl			%l4, 20, %l4
#ifdef CONFIG_TRACE_IRQFLAGS
		brnz,pn			%l4, rtrap_no_irq_enable
		 nop
		call			trace_hardirqs_on
		 nop
		/* Do not actually set the %pil here.  We will do that
		 * below after we clear PSTATE_IE in the %pstate register.
		 * If we re-enable interrupts here, we can recurse down
		 * the hardirq stack potentially endlessly, causing a
		 * stack overflow.
		 *
		 * It is tempting to put this test and trace_hardirqs_on
		 * call at the 'rt_continue' label, but that will not work
		 * as that path hits unconditionally and we do not want to
		 * execute this in NMI return paths, for example.
		 */
#endif
rtrap_no_irq_enable:
		andcc			%l1, TSTATE_PRIV, %l3
		bne,pn			%icc, to_kernel
		 nop

		/* We must hold IRQs off and atomically test schedule+signal
		 * state, then hold them off all the way back to userspace.
		 * If we are returning to kernel, none of this matters.  Note
		 * that we are disabling interrupts via PSTATE_IE, not using
		 * %pil.
		 *
		 * If we do not do this, there is a window where we would do
		 * the tests, later the signal/resched event arrives but we do
		 * not process it since we are still in kernel mode.  It would
		 * take until the next local IRQ before the signal/resched
		 * event would be handled.
		 *
		 * This also means that if we have to deal with user
		 * windows, we have to redo all of these sched+signal checks
		 * with IRQs disabled.
		 */
to_user:	wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		wrpr			0, %pil
__handle_preemption_continue:
		ldx			[%g6 + TI_FLAGS], %l0
		sethi			%hi(_TIF_USER_WORK_MASK), %o0
		or			%o0, %lo(_TIF_USER_WORK_MASK), %o0
		andcc			%l0, %o0, %g0
		sethi			%hi(TSTATE_PEF), %o0
		be,pt			%xcc, user_nowork
		 andcc			%l1, %o0, %g0
		andcc			%l0, _TIF_NEED_RESCHED, %g0
		bne,pn			%xcc, __handle_preemption
		 andcc			%l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
		bne,pn			%xcc, __handle_signal
		 ldub			[%g6 + TI_WSAVED], %o2
		brnz,pn			%o2, __handle_user_windows
		 nop
		sethi			%hi(TSTATE_PEF), %o0
		andcc			%l1, %o0, %g0

		/* This fpdepth clear is necessary for non-syscall rtraps only */
user_nowork:
		bne,pn			%xcc, __handle_userfpu
		 stb			%g0, [%g6 + TI_FPDEPTH]
__handle_userfpu_continue:

rt_continue:	ldx			[%sp + PTREGS_OFF + PT_V9_G1], %g1
		ldx			[%sp + PTREGS_OFF + PT_V9_G2], %g2

		ldx			[%sp + PTREGS_OFF + PT_V9_G3], %g3
		ldx			[%sp + PTREGS_OFF + PT_V9_G4], %g4
		ldx			[%sp + PTREGS_OFF + PT_V9_G5], %g5
		brz,pt			%l3, 1f
		mov			%g6, %l2

		/* Must do this before thread reg is clobbered below.  */
		LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
1:
		ldx			[%sp + PTREGS_OFF + PT_V9_G6], %g6
		ldx			[%sp + PTREGS_OFF + PT_V9_G7], %g7

		/* Normal globals are restored, go to trap globals.  */
661:		wrpr			%g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
		nop
		.section		.sun4v_2insn_patch, "ax"
		.word			661b
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		SET_GL(1)
		.previous

		mov			%l2, %g6

		ldx			[%sp + PTREGS_OFF + PT_V9_I0], %i0
		ldx			[%sp + PTREGS_OFF + PT_V9_I1], %i1

		ldx			[%sp + PTREGS_OFF + PT_V9_I2], %i2
		ldx			[%sp + PTREGS_OFF + PT_V9_I3], %i3
		ldx			[%sp + PTREGS_OFF + PT_V9_I4], %i4
		ldx			[%sp + PTREGS_OFF + PT_V9_I5], %i5
		ldx			[%sp + PTREGS_OFF + PT_V9_I6], %i6
		ldx			[%sp + PTREGS_OFF + PT_V9_I7], %i7
		ldx			[%sp + PTREGS_OFF + PT_V9_TPC], %l2
		ldx			[%sp + PTREGS_OFF + PT_V9_TNPC], %o2

		ld			[%sp + PTREGS_OFF + PT_V9_Y], %o3
		wr			%o3, %g0, %y
		wrpr			%l4, 0x0, %pil
		wrpr			%g0, 0x1, %tl
		andn			%l1, TSTATE_SYSCALL, %l1
		wrpr			%l1, %g0, %tstate
		wrpr			%l2, %g0, %tpc
		wrpr			%o2, %g0, %tnpc

		brnz,pn			%l3, kern_rtt
		 mov			PRIMARY_CONTEXT, %l7

661:		ldxa			[%l7 + %l7] ASI_DMMU, %l0
		.section		.sun4v_1insn_patch, "ax"
		.word			661b
		ldxa			[%l7 + %l7] ASI_MMU, %l0
		.previous

		sethi			%hi(sparc64_kern_pri_nuc_bits), %l1
		ldx			[%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
		or			%l0, %l1, %l0

661:		stxa			%l0, [%l7] ASI_DMMU
		.section		.sun4v_1insn_patch, "ax"
		.word			661b
		stxa			%l0, [%l7] ASI_MMU
		.previous

		sethi			%hi(KERNBASE), %l7
		flush			%l7
		rdpr			%wstate, %l1
		rdpr			%otherwin, %l2
		srl			%l1, 3, %l1

		wrpr			%l2, %g0, %canrestore
		wrpr			%l1, %g0, %wstate
		brnz,pt			%l2, user_rtt_restore
		 wrpr			%g0, %g0, %otherwin

		ldx			[%g6 + TI_FLAGS], %g3
		wr			%g0, ASI_AIUP, %asi
		rdpr			%cwp, %g1
		andcc			%g3, _TIF_32BIT, %g0
		sub			%g1, 1, %g1
		bne,pt			%xcc, user_rtt_fill_32bit
		 wrpr			%g1, %cwp
		ba,a,pt			%xcc, user_rtt_fill_64bit

user_rtt_fill_fixup_dax:
		ba,pt	%xcc, user_rtt_fill_fixup_common
		 mov	1, %g3

user_rtt_fill_fixup_mna:
		ba,pt	%xcc, user_rtt_fill_fixup_common
		 mov	2, %g3

user_rtt_fill_fixup:
		ba,pt	%xcc, user_rtt_fill_fixup_common
		 clr	%g3

user_rtt_pre_restore:
		add			%g1, 1, %g1
		wrpr			%g1, 0x0, %cwp

user_rtt_restore:
		restore
		rdpr			%canrestore, %g1
		wrpr			%g1, 0x0, %cleanwin
		retry
		nop

kern_rtt:	rdpr			%canrestore, %g1
		brz,pn			%g1, kern_rtt_fill
		 nop
kern_rtt_restore:
		stw			%g0, [%sp + PTREGS_OFF + PT_V9_MAGIC]
		restore
		retry

to_kernel:
#ifdef CONFIG_PREEMPT
		ldsw			[%g6 + TI_PRE_COUNT], %l5
		brnz			%l5, kern_fpucheck
		 ldx			[%g6 + TI_FLAGS], %l5
		andcc			%l5, _TIF_NEED_RESCHED, %g0
		be,pt			%xcc, kern_fpucheck
		 nop
		cmp			%l4, 0
		bne,pn			%xcc, kern_fpucheck
		 nop
		call			preempt_schedule_irq
		 nop
		ba,pt			%xcc, rtrap
#endif
kern_fpucheck:	ldub			[%g6 + TI_FPDEPTH], %l5
		brz,pt			%l5, rt_continue
		 srl			%l5, 1, %o0
		add			%g6, TI_FPSAVED, %l6
		ldub			[%l6 + %o0], %l2
		sub			%l5, 2, %l5

		add			%g6, TI_GSR, %o1
		andcc			%l2, (FPRS_FEF|FPRS_DU), %g0
		be,pt			%icc, 2f
		 and			%l2, FPRS_DL, %l6
		andcc			%l2, FPRS_FEF, %g0
		be,pn			%icc, 5f
		 sll			%o0, 3, %o5
		rd			%fprs, %g1

		wr			%g1, FPRS_FEF, %fprs
		ldx			[%o1 + %o5], %g1
		add			%g6, TI_XFSR, %o1
		sll			%o0, 8, %o2
		add			%g6, TI_FPREGS, %o3
		brz,pn			%l6, 1f
		 add			%g6, TI_FPREGS+0x40, %o4

		membar			#Sync
		ldda			[%o3 + %o2] ASI_BLK_P, %f0
		ldda			[%o4 + %o2] ASI_BLK_P, %f16
		membar			#Sync
1:		andcc			%l2, FPRS_DU, %g0
		be,pn			%icc, 1f
		 wr			%g1, 0, %gsr
		add			%o2, 0x80, %o2
		membar			#Sync
		ldda			[%o3 + %o2] ASI_BLK_P, %f32
		ldda			[%o4 + %o2] ASI_BLK_P, %f48
1:		membar			#Sync
		ldx			[%o1 + %o5], %fsr
2:		stb			%l5, [%g6 + TI_FPDEPTH]
		ba,pt			%xcc, rt_continue
		 nop
5:		wr			%g0, FPRS_FEF, %fprs
		sll			%o0, 8, %o2

		add			%g6, TI_FPREGS+0x80, %o3
		add			%g6, TI_FPREGS+0xc0, %o4
		membar			#Sync
		ldda			[%o3 + %o2] ASI_BLK_P, %f32
		ldda			[%o4 + %o2] ASI_BLK_P, %f48
		membar			#Sync
		wr			%g0, FPRS_DU, %fprs
		ba,pt			%xcc, rt_continue
		 stb			%l5, [%g6 + TI_FPDEPTH]
Commit	Line	Data
b00dc837	1	/*
1da177e4 LT	2	* rtrap.S: Preparing for return from trap on Sparc V9.
	3	*
	4	* Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
	5	* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
	6	*/
	7
1da177e4 LT	8
	9	#include <asm/asi.h>
	10	#include <asm/pstate.h>
	11	#include <asm/ptrace.h>
	12	#include <asm/spitfire.h>
	13	#include <asm/head.h>
	14	#include <asm/visasm.h>
	15	#include <asm/processor.h>
	16
812cb83a KT	17	#ifdef CONFIG_CONTEXT_TRACKING
	18	# define SCHEDULE_USER schedule_user
	19	#else
	20	# define SCHEDULE_USER schedule
	21	#endif
	22
1da177e4 LT	23	.text
1da177e4 LT	24	.align 32
1da177e4	25	__handle_preemption:
812cb83a	26	call SCHEDULE_USER
1da177e4 LT	27	wrpr %g0, RTRAP_PSTATE, %pstate
	28	ba,pt %xcc, __handle_preemption_continue
	29	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	30
	31	__handle_user_windows:
	32	call fault_in_user_windows
	33	wrpr %g0, RTRAP_PSTATE, %pstate
caebf910 AV	34	ba,pt %xcc, __handle_preemption_continue
caebf910 AV	35	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
1da177e4	36
1da177e4 LT	37	__handle_userfpu:
	38	rd %fprs, %l5
	39	andcc %l5, FPRS_FEF, %g0
	40	sethi %hi(TSTATE_PEF), %o0
	41	be,a,pn %icc, __handle_userfpu_continue
	42	andn %l1, %o0, %l1
	43	ba,a,pt %xcc, __handle_userfpu_continue
	44
	45	__handle_signal:
2d7d5f05	46	mov %l5, %o1
2d7d5f05	47	add %sp, PTREGS_OFF, %o0
7697daaa	48	mov %l0, %o2
1da177e4 LT	49	call do_notify_resume
	50	wrpr %g0, RTRAP_PSTATE, %pstate
	51	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
1da177e4 LT	52
	53	/* Signal delivery can modify pt_regs tstate, so we must
	54	* reload it.
	55	*/
	56	ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
	57	sethi %hi(0xf << 20), %l4
	58	and %l1, %l4, %l4
caebf910	59	ba,pt %xcc, __handle_preemption_continue
1da177e4 LT	60	andn %l1, %l4, %l1
1da177e4 LT	61
5565736e DM	62	/* When returning from a NMI (%pil==15) interrupt we want to
	63	* avoid running softirqs, doing IRQ tracing, preempting, etc.
	64	*/
	65	.globl rtrap_nmi
	66	rtrap_nmi: ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
	67	sethi %hi(0xf << 20), %l4
	68	and %l1, %l4, %l4
	69	andn %l1, %l4, %l1
	70	srl %l4, 20, %l4
	71	ba,pt %xcc, rtrap_no_irq_enable
1ca04a4c RG	72	nop
	73	/* Do not actually set the %pil here. We will do that
	74	* below after we clear PSTATE_IE in the %pstate register.
	75	* If we re-enable interrupts here, we can recurse down
	76	* the hardirq stack potentially endlessly, causing a
	77	* stack overflow.
	78	*/
5565736e	79
1da177e4	80	.align 64
7697daaa	81	.globl rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall
1da177e4	82	rtrap_irq:
1da177e4	83	rtrap:
1da177e4	84	/* mm/ultra.S:xcall_report_regs KNOWS about this load. */
78b7e3d0	85	ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
1da177e4 LT	86	rtrap_xcall:
1da177e4 LT	87	sethi %hi(0xf << 20), %l4
1da177e4	88	and %l1, %l4, %l4
10e26723 DM	89	andn %l1, %l4, %l1
	90	srl %l4, 20, %l4
	91	#ifdef CONFIG_TRACE_IRQFLAGS
	92	brnz,pn %l4, rtrap_no_irq_enable
	93	nop
	94	call trace_hardirqs_on
	95	nop
28a1f533 DM	96	/* Do not actually set the %pil here. We will do that
	97	* below after we clear PSTATE_IE in the %pstate register.
	98	* If we re-enable interrupts here, we can recurse down
	99	* the hardirq stack potentially endlessly, causing a
	100	* stack overflow.
	101	*
	102	* It is tempting to put this test and trace_hardirqs_on
	103	* call at the 'rt_continue' label, but that will not work
	104	* as that path hits unconditionally and we do not want to
	105	* execute this in NMI return paths, for example.
	106	*/
10e26723	107	#endif
5565736e	108	rtrap_no_irq_enable:
10e26723	109	andcc %l1, TSTATE_PRIV, %l3
1da177e4	110	bne,pn %icc, to_kernel
10e26723	111	nop
1da177e4 LT	112
	113	/* We must hold IRQs off and atomically test schedule+signal
	114	* state, then hold them off all the way back to userspace.
10e26723 DM	115	* If we are returning to kernel, none of this matters. Note
	116	* that we are disabling interrupts via PSTATE_IE, not using
	117	* %pil.
1da177e4 LT	118	*
	119	* If we do not do this, there is a window where we would do
	120	* the tests, later the signal/resched event arrives but we do
	121	* not process it since we are still in kernel mode. It would
	122	* take until the next local IRQ before the signal/resched
	123	* event would be handled.
	124	*
c7d5a005 DM	125	* This also means that if we have to deal with user
	126	* windows, we have to redo all of these sched+signal checks
	127	* with IRQs disabled.
1da177e4 LT	128	*/
	129	to_user: wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	130	wrpr 0, %pil
	131	__handle_preemption_continue:
	132	ldx [%g6 + TI_FLAGS], %l0
	133	sethi %hi(_TIF_USER_WORK_MASK), %o0
	134	or %o0, %lo(_TIF_USER_WORK_MASK), %o0
	135	andcc %l0, %o0, %g0
	136	sethi %hi(TSTATE_PEF), %o0
	137	be,pt %xcc, user_nowork
	138	andcc %l1, %o0, %g0
	139	andcc %l0, _TIF_NEED_RESCHED, %g0
	140	bne,pn %xcc, __handle_preemption
e35a8925	141	andcc %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
1da177e4	142	bne,pn %xcc, __handle_signal
1da177e4 LT	143	ldub [%g6 + TI_WSAVED], %o2
	144	brnz,pn %o2, __handle_user_windows
	145	nop
1da177e4	146	sethi %hi(TSTATE_PEF), %o0
c7d5a005	147	andcc %l1, %o0, %g0
1da177e4 LT	148
	149	/* This fpdepth clear is necessary for non-syscall rtraps only */
	150	user_nowork:
	151	bne,pn %xcc, __handle_userfpu
	152	stb %g0, [%g6 + TI_FPDEPTH]
	153	__handle_userfpu_continue:
	154
	155	rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1
	156	ldx [%sp + PTREGS_OFF + PT_V9_G2], %g2
	157
	158	ldx [%sp + PTREGS_OFF + PT_V9_G3], %g3
	159	ldx [%sp + PTREGS_OFF + PT_V9_G4], %g4
	160	ldx [%sp + PTREGS_OFF + PT_V9_G5], %g5
56fb4df6	161	brz,pt %l3, 1f
314981ac DM	162	mov %g6, %l2
314981ac DM	163
56fb4df6	164	/* Must do this before thread reg is clobbered below. */
ffe483d5	165	LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
74bf4312 DM	166	1:
74bf4312 DM	167	ldx [%sp + PTREGS_OFF + PT_V9_G6], %g6
1da177e4	168	ldx [%sp + PTREGS_OFF + PT_V9_G7], %g7
936f482a DM	169
	170	/* Normal globals are restored, go to trap globals. */
	171	661: wrpr %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
af02bec6 DM	172	nop
af02bec6 DM	173	.section .sun4v_2insn_patch, "ax"
936f482a	174	.word 661b
af02bec6	175	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
936f482a DM	176	SET_GL(1)
	177	.previous
	178
314981ac DM	179	mov %l2, %g6
314981ac DM	180
1da177e4 LT	181	ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0
	182	ldx [%sp + PTREGS_OFF + PT_V9_I1], %i1
	183
	184	ldx [%sp + PTREGS_OFF + PT_V9_I2], %i2
	185	ldx [%sp + PTREGS_OFF + PT_V9_I3], %i3
	186	ldx [%sp + PTREGS_OFF + PT_V9_I4], %i4
	187	ldx [%sp + PTREGS_OFF + PT_V9_I5], %i5
	188	ldx [%sp + PTREGS_OFF + PT_V9_I6], %i6
	189	ldx [%sp + PTREGS_OFF + PT_V9_I7], %i7
	190	ldx [%sp + PTREGS_OFF + PT_V9_TPC], %l2
	191	ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %o2
	192
	193	ld [%sp + PTREGS_OFF + PT_V9_Y], %o3
	194	wr %o3, %g0, %y
1da177e4 LT	195	wrpr %l4, 0x0, %pil
1da177e4 LT	196	wrpr %g0, 0x1, %tl
28e61036	197	andn %l1, TSTATE_SYSCALL, %l1
1da177e4 LT	198	wrpr %l1, %g0, %tstate
	199	wrpr %l2, %g0, %tpc
	200	wrpr %o2, %g0, %tnpc
	201
	202	brnz,pn %l3, kern_rtt
	203	mov PRIMARY_CONTEXT, %l7
8b11bd12 DM	204
	205	661: ldxa [%l7 + %l7] ASI_DMMU, %l0
	206	.section .sun4v_1insn_patch, "ax"
	207	.word 661b
	208	ldxa [%l7 + %l7] ASI_MMU, %l0
	209	.previous
	210
0835ae0f DM	211	sethi %hi(sparc64_kern_pri_nuc_bits), %l1
0835ae0f DM	212	ldx [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
1da177e4	213	or %l0, %l1, %l0
8b11bd12 DM	214
	215	661: stxa %l0, [%l7] ASI_DMMU
	216	.section .sun4v_1insn_patch, "ax"
	217	.word 661b
	218	stxa %l0, [%l7] ASI_MMU
	219	.previous
	220
4da808c3 DM	221	sethi %hi(KERNBASE), %l7
4da808c3 DM	222	flush %l7
1da177e4 LT	223	rdpr %wstate, %l1
	224	rdpr %otherwin, %l2
	225	srl %l1, 3, %l1
	226
	227	wrpr %l2, %g0, %canrestore
	228	wrpr %l1, %g0, %wstate
314ef685 DM	229	brnz,pt %l2, user_rtt_restore
	230	wrpr %g0, %g0, %otherwin
	231
	232	ldx [%g6 + TI_FLAGS], %g3
	233	wr %g0, ASI_AIUP, %asi
	234	rdpr %cwp, %g1
	235	andcc %g3, _TIF_32BIT, %g0
	236	sub %g1, 1, %g1
	237	bne,pt %xcc, user_rtt_fill_32bit
	238	wrpr %g1, %cwp
	239	ba,a,pt %xcc, user_rtt_fill_64bit
	240
7cafc0b8 DM	241	user_rtt_fill_fixup_dax:
	242	ba,pt %xcc, user_rtt_fill_fixup_common
	243	mov 1, %g3
314ef685	244
7cafc0b8 DM	245	user_rtt_fill_fixup_mna:
	246	ba,pt %xcc, user_rtt_fill_fixup_common
	247	mov 2, %g3
314ef685	248
7cafc0b8 DM	249	user_rtt_fill_fixup:
	250	ba,pt %xcc, user_rtt_fill_fixup_common
	251	clr %g3
314ef685 DM	252
	253	user_rtt_pre_restore:
	254	add %g1, 1, %g1
	255	wrpr %g1, 0x0, %cwp
	256
	257	user_rtt_restore:
1da177e4 LT	258	restore
	259	rdpr %canrestore, %g1
	260	wrpr %g1, 0x0, %cleanwin
	261	retry
	262	nop
	263
314ef685 DM	264	kern_rtt: rdpr %canrestore, %g1
	265	brz,pn %g1, kern_rtt_fill
	266	nop
	267	kern_rtt_restore:
ada44a04	268	stw %g0, [%sp + PTREGS_OFF + PT_V9_MAGIC]
314ef685	269	restore
1da177e4	270	retry
314ef685	271
1da177e4 LT	272	to_kernel:
	273	#ifdef CONFIG_PREEMPT
	274	ldsw [%g6 + TI_PRE_COUNT], %l5
	275	brnz %l5, kern_fpucheck
	276	ldx [%g6 + TI_FLAGS], %l5
	277	andcc %l5, _TIF_NEED_RESCHED, %g0
	278	be,pt %xcc, kern_fpucheck
10e26723 DM	279	nop
10e26723 DM	280	cmp %l4, 0
1da177e4	281	bne,pn %xcc, kern_fpucheck
9385d949 TG	282	nop
9385d949 TG	283	call preempt_schedule_irq
1da177e4 LT	284	nop
1da177e4 LT	285	ba,pt %xcc, rtrap
1da177e4 LT	286	#endif
	287	kern_fpucheck: ldub [%g6 + TI_FPDEPTH], %l5
	288	brz,pt %l5, rt_continue
	289	srl %l5, 1, %o0
	290	add %g6, TI_FPSAVED, %l6
	291	ldub [%l6 + %o0], %l2
	292	sub %l5, 2, %l5
	293
	294	add %g6, TI_GSR, %o1
	295	andcc %l2, (FPRS_FEF\|FPRS_DU), %g0
	296	be,pt %icc, 2f
	297	and %l2, FPRS_DL, %l6
	298	andcc %l2, FPRS_FEF, %g0
	299	be,pn %icc, 5f
	300	sll %o0, 3, %o5
	301	rd %fprs, %g1
	302
	303	wr %g1, FPRS_FEF, %fprs
	304	ldx [%o1 + %o5], %g1
	305	add %g6, TI_XFSR, %o1
1da177e4 LT	306	sll %o0, 8, %o2
	307	add %g6, TI_FPREGS, %o3
	308	brz,pn %l6, 1f
	309	add %g6, TI_FPREGS+0x40, %o4
	310
ba639933	311	membar #Sync
1da177e4 LT	312	ldda [%o3 + %o2] ASI_BLK_P, %f0
1da177e4 LT	313	ldda [%o4 + %o2] ASI_BLK_P, %f16
ba639933	314	membar #Sync
1da177e4 LT	315	1: andcc %l2, FPRS_DU, %g0
	316	be,pn %icc, 1f
	317	wr %g1, 0, %gsr
	318	add %o2, 0x80, %o2
ba639933	319	membar #Sync
1da177e4 LT	320	ldda [%o3 + %o2] ASI_BLK_P, %f32
1da177e4 LT	321	ldda [%o4 + %o2] ASI_BLK_P, %f48
1da177e4 LT	322	1: membar #Sync
	323	ldx [%o1 + %o5], %fsr
	324	2: stb %l5, [%g6 + TI_FPDEPTH]
	325	ba,pt %xcc, rt_continue
	326	nop
	327	5: wr %g0, FPRS_FEF, %fprs
1da177e4 LT	328	sll %o0, 8, %o2
	329
	330	add %g6, TI_FPREGS+0x80, %o3
	331	add %g6, TI_FPREGS+0xc0, %o4
ba639933	332	membar #Sync
1da177e4 LT	333	ldda [%o3 + %o2] ASI_BLK_P, %f32
	334	ldda [%o4 + %o2] ASI_BLK_P, %f48
	335	membar #Sync
	336	wr %g0, FPRS_DU, %fprs
	337	ba,pt %xcc, rt_continue
	338	stb %l5, [%g6 + TI_FPDEPTH]