[linux-block.git] / arch / sparc / kernel / pci_sun4v_asm.S

/* SPDX-License-Identifier: GPL-2.0 */
/* pci_sun4v_asm: Hypervisor calls for PCI support.
 *
 * Copyright (C) 2006, 2008 David S. Miller <davem@davemloft.net>
 */

#include <linux/linkage.h>
#include <asm/hypervisor.h>

	/* %o0: devhandle
	 * %o1:	tsbid
	 * %o2:	num ttes
	 * %o3:	io_attributes
	 * %o4:	io_page_list phys address
	 *
	 * returns %o0:	-status if status was non-zero, else
	 *         %o0:	num pages mapped
	 */
ENTRY(pci_sun4v_iommu_map)
	mov	%o5, %g1
	mov	HV_FAST_PCI_IOMMU_MAP, %o5
	ta	HV_FAST_TRAP
	brnz,pn %o0, 1f
	 sub	%g0, %o0, %o0
	mov	%o1, %o0
1:	retl
	 nop
ENDPROC(pci_sun4v_iommu_map)

	/* %o0: devhandle
	 * %o1:	tsbid
	 * %o2:	num ttes
	 *
	 * returns %o0:	num ttes demapped
	 */
ENTRY(pci_sun4v_iommu_demap)
	mov	HV_FAST_PCI_IOMMU_DEMAP, %o5
	ta	HV_FAST_TRAP
	retl
	 mov	%o1, %o0
ENDPROC(pci_sun4v_iommu_demap)

	/* %o0: devhandle
	 * %o1:	tsbid
	 * %o2:	&io_attributes
	 * %o3:	&real_address
	 *
	 * returns %o0:	status
	 */
ENTRY(pci_sun4v_iommu_getmap)
	mov	%o2, %o4
	mov	HV_FAST_PCI_IOMMU_GETMAP, %o5
	ta	HV_FAST_TRAP
	stx	%o1, [%o4]
	stx	%o2, [%o3]
	retl
	 mov	%o0, %o0
ENDPROC(pci_sun4v_iommu_getmap)

	/* %o0: devhandle
	 * %o1:	pci_device
	 * %o2:	pci_config_offset
	 * %o3:	size
	 *
	 * returns %o0:	data
	 *
	 * If there is an error, the data will be returned
	 * as all 1's.
	 */
ENTRY(pci_sun4v_config_get)
	mov	HV_FAST_PCI_CONFIG_GET, %o5
	ta	HV_FAST_TRAP
	brnz,a,pn %o1, 1f
	 mov	-1, %o2
1:	retl
	 mov	%o2, %o0
ENDPROC(pci_sun4v_config_get)

	/* %o0: devhandle
	 * %o1:	pci_device
	 * %o2:	pci_config_offset
	 * %o3:	size
	 * %o4:	data
	 *
	 * returns %o0:	status
	 *
	 * status will be zero if the operation completed
	 * successfully, else -1 if not
	 */
ENTRY(pci_sun4v_config_put)
	mov	HV_FAST_PCI_CONFIG_PUT, %o5
	ta	HV_FAST_TRAP
	brnz,a,pn %o1, 1f
	 mov	-1, %o1
1:	retl
	 mov	%o1, %o0
ENDPROC(pci_sun4v_config_put)

	/* %o0: devhandle
	 * %o1: msiqid
	 * %o2: msiq phys address
	 * %o3: num entries
	 *
	 * returns %o0: status
	 *
	 * status will be zero if the operation completed
	 * successfully, else -1 if not
	 */
ENTRY(pci_sun4v_msiq_conf)
	mov	HV_FAST_PCI_MSIQ_CONF, %o5
	ta	HV_FAST_TRAP
	retl
	 mov	%o0, %o0
ENDPROC(pci_sun4v_msiq_conf)

	/* %o0: devhandle
	 * %o1: msiqid
	 * %o2:	&msiq_phys_addr
	 * %o3:	&msiq_num_entries
	 *
	 * returns %o0: status
	 */
ENTRY(pci_sun4v_msiq_info)
	mov	%o2, %o4
	mov	HV_FAST_PCI_MSIQ_INFO, %o5
	ta	HV_FAST_TRAP
	stx	%o1, [%o4]
	stx	%o2, [%o3]
	retl
	 mov	%o0, %o0
ENDPROC(pci_sun4v_msiq_info)

	/* %o0: devhandle
	 * %o1: msiqid
	 * %o2:	&valid
	 *
	 * returns %o0: status
	 */
ENTRY(pci_sun4v_msiq_getvalid)
	mov	HV_FAST_PCI_MSIQ_GETVALID, %o5
	ta	HV_FAST_TRAP
	stx	%o1, [%o2]
	retl
	 mov	%o0, %o0
ENDPROC(pci_sun4v_msiq_getvalid)

	/* %o0: devhandle
	 * %o1: msiqid
	 * %o2:	valid
	 *
	 * returns %o0: status
	 */
ENTRY(pci_sun4v_msiq_setvalid)
	mov	HV_FAST_PCI_MSIQ_SETVALID, %o5
	ta	HV_FAST_TRAP
	retl
	 mov	%o0, %o0
ENDPROC(pci_sun4v_msiq_setvalid)

	/* %o0: devhandle
	 * %o1: msiqid
	 * %o2:	&state
	 *
	 * returns %o0: status
	 */
ENTRY(pci_sun4v_msiq_getstate)
	mov	HV_FAST_PCI_MSIQ_GETSTATE, %o5
	ta	HV_FAST_TRAP
	stx	%o1, [%o2]
	retl
	 mov	%o0, %o0
ENDPROC(pci_sun4v_msiq_getstate)

	/* %o0: devhandle
	 * %o1: msiqid
	 * %o2:	state
	 *
	 * returns %o0: status
	 */
ENTRY(pci_sun4v_msiq_setstate)
	mov	HV_FAST_PCI_MSIQ_SETSTATE, %o5
	ta	HV_FAST_TRAP
	retl
	 mov	%o0, %o0
ENDPROC(pci_sun4v_msiq_setstate)

	/* %o0: devhandle
	 * %o1: msiqid
	 * %o2:	&head
	 *
	 * returns %o0: status
	 */
ENTRY(pci_sun4v_msiq_gethead)
	mov	HV_FAST_PCI_MSIQ_GETHEAD, %o5
	ta	HV_FAST_TRAP
	stx	%o1, [%o2]
	retl
	 mov	%o0, %o0
ENDPROC(pci_sun4v_msiq_gethead)

	/* %o0: devhandle
	 * %o1: msiqid
	 * %o2:	head
	 *
	 * returns %o0: status
	 */
ENTRY(pci_sun4v_msiq_sethead)
	mov	HV_FAST_PCI_MSIQ_SETHEAD, %o5
	ta	HV_FAST_TRAP
	retl
	 mov	%o0, %o0
ENDPROC(pci_sun4v_msiq_sethead)

	/* %o0: devhandle
	 * %o1: msiqid
	 * %o2:	&tail
	 *
	 * returns %o0: status
	 */
ENTRY(pci_sun4v_msiq_gettail)
	mov	HV_FAST_PCI_MSIQ_GETTAIL, %o5
	ta	HV_FAST_TRAP
	stx	%o1, [%o2]
	retl
	 mov	%o0, %o0
ENDPROC(pci_sun4v_msiq_gettail)

	/* %o0: devhandle
	 * %o1: msinum
	 * %o2:	&valid
	 *
	 * returns %o0: status
	 */
ENTRY(pci_sun4v_msi_getvalid)
	mov	HV_FAST_PCI_MSI_GETVALID, %o5
	ta	HV_FAST_TRAP
	stx	%o1, [%o2]
	retl
	 mov	%o0, %o0
ENDPROC(pci_sun4v_msi_getvalid)

	/* %o0: devhandle
	 * %o1: msinum
	 * %o2:	valid
	 *
	 * returns %o0: status
	 */
ENTRY(pci_sun4v_msi_setvalid)
	mov	HV_FAST_PCI_MSI_SETVALID, %o5
	ta	HV_FAST_TRAP
	retl
	 mov	%o0, %o0
ENDPROC(pci_sun4v_msi_setvalid)

	/* %o0: devhandle
	 * %o1: msinum
	 * %o2:	&msiq
	 *
	 * returns %o0: status
	 */
ENTRY(pci_sun4v_msi_getmsiq)
	mov	HV_FAST_PCI_MSI_GETMSIQ, %o5
	ta	HV_FAST_TRAP
	stx	%o1, [%o2]
	retl
	 mov	%o0, %o0
ENDPROC(pci_sun4v_msi_getmsiq)

	/* %o0: devhandle
	 * %o1: msinum
	 * %o2:	msitype
	 * %o3:	msiq
	 *
	 * returns %o0: status
	 */
ENTRY(pci_sun4v_msi_setmsiq)
	mov	HV_FAST_PCI_MSI_SETMSIQ, %o5
	ta	HV_FAST_TRAP
	retl
	 mov	%o0, %o0
ENDPROC(pci_sun4v_msi_setmsiq)

	/* %o0: devhandle
	 * %o1: msinum
	 * %o2:	&state
	 *
	 * returns %o0: status
	 */
ENTRY(pci_sun4v_msi_getstate)
	mov	HV_FAST_PCI_MSI_GETSTATE, %o5
	ta	HV_FAST_TRAP
	stx	%o1, [%o2]
	retl
	 mov	%o0, %o0
ENDPROC(pci_sun4v_msi_getstate)

	/* %o0: devhandle
	 * %o1: msinum
	 * %o2:	state
	 *
	 * returns %o0: status
	 */
ENTRY(pci_sun4v_msi_setstate)
	mov	HV_FAST_PCI_MSI_SETSTATE, %o5
	ta	HV_FAST_TRAP
	retl
	 mov	%o0, %o0
ENDPROC(pci_sun4v_msi_setstate)

	/* %o0: devhandle
	 * %o1: msinum
	 * %o2:	&msiq
	 *
	 * returns %o0: status
	 */
ENTRY(pci_sun4v_msg_getmsiq)
	mov	HV_FAST_PCI_MSG_GETMSIQ, %o5
	ta	HV_FAST_TRAP
	stx	%o1, [%o2]
	retl
	 mov	%o0, %o0
ENDPROC(pci_sun4v_msg_getmsiq)

	/* %o0: devhandle
	 * %o1: msinum
	 * %o2:	msiq
	 *
	 * returns %o0: status
	 */
ENTRY(pci_sun4v_msg_setmsiq)
	mov	HV_FAST_PCI_MSG_SETMSIQ, %o5
	ta	HV_FAST_TRAP
	retl
	 mov	%o0, %o0
ENDPROC(pci_sun4v_msg_setmsiq)

	/* %o0: devhandle
	 * %o1: msinum
	 * %o2:	&valid
	 *
	 * returns %o0: status
	 */
ENTRY(pci_sun4v_msg_getvalid)
	mov	HV_FAST_PCI_MSG_GETVALID, %o5
	ta	HV_FAST_TRAP
	stx	%o1, [%o2]
	retl
	 mov	%o0, %o0
ENDPROC(pci_sun4v_msg_getvalid)

	/* %o0: devhandle
	 * %o1: msinum
	 * %o2:	valid
	 *
	 * returns %o0: status
	 */
ENTRY(pci_sun4v_msg_setvalid)
	mov	HV_FAST_PCI_MSG_SETVALID, %o5
	ta	HV_FAST_TRAP
	retl
	 mov	%o0, %o0
ENDPROC(pci_sun4v_msg_setvalid)

	/*
	 * %o0:	devhandle
	 * %o1:	r_addr
	 * %o2:	size
	 * %o3:	pagesize
	 * %o4:	virt
	 * %o5: &iotsb_num/&iotsb_handle
	 *
	 * returns %o0:	status
	 *         %o1:	iotsb_num/iotsb_handle
	 */
ENTRY(pci_sun4v_iotsb_conf)
	mov	%o5, %g1
	mov	HV_FAST_PCI_IOTSB_CONF, %o5
	ta	HV_FAST_TRAP
	retl
	 stx	%o1, [%g1]
ENDPROC(pci_sun4v_iotsb_conf)

	/*
	 * %o0:	devhandle
	 * %o1:	iotsb_num/iotsb_handle
	 * %o2:	pci_device
	 *
	 * returns %o0:	status
	 */
ENTRY(pci_sun4v_iotsb_bind)
	mov	HV_FAST_PCI_IOTSB_BIND, %o5
	ta	HV_FAST_TRAP
	retl
	 nop
ENDPROC(pci_sun4v_iotsb_bind)

	/*
	 * %o0:	devhandle
	 * %o1:	iotsb_num/iotsb_handle
	 * %o2:	index_count
	 * %o3:	iotte_attributes
	 * %o4:	io_page_list_p
	 * %o5: &mapped
	 *
	 * returns %o0:	status
	 *         %o1:	#mapped
	 */
ENTRY(pci_sun4v_iotsb_map)
	mov	%o5, %g1
	mov	HV_FAST_PCI_IOTSB_MAP, %o5
	ta	HV_FAST_TRAP
	retl
	 stx	%o1, [%g1]
ENDPROC(pci_sun4v_iotsb_map)

	/*
	 * %o0:	devhandle
	 * %o1:	iotsb_num/iotsb_handle
	 * %o2:	iotsb_index
	 * %o3:	#iottes
	 * %o4: &demapped
	 *
	 * returns %o0:	status
	 *         %o1:	#demapped
	 */
ENTRY(pci_sun4v_iotsb_demap)
	mov	HV_FAST_PCI_IOTSB_DEMAP, %o5
	ta	HV_FAST_TRAP
	retl
	 stx	%o1, [%o4]
ENDPROC(pci_sun4v_iotsb_demap)
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
bade5622 DM	2	/* pci_sun4v_asm: Hypervisor calls for PCI support.
bade5622 DM	3	*
fefbbc73	4	* Copyright (C) 2006, 2008 David S. Miller <davem@davemloft.net>
bade5622 DM	5	*/
bade5622 DM	6
fefbbc73	7	#include <linux/linkage.h>
bade5622 DM	8	#include <asm/hypervisor.h>
bade5622 DM	9
bade5622 DM	10	/* %o0: devhandle
	11	* %o1: tsbid
	12	* %o2: num ttes
	13	* %o3: io_attributes
	14	* %o4: io_page_list phys address
	15	*
6a32fd4d DM	16	* returns %o0: -status if status was non-zero, else
6a32fd4d DM	17	* %o0: num pages mapped
bade5622	18	*/
fefbbc73	19	ENTRY(pci_sun4v_iommu_map)
6a32fd4d	20	mov %o5, %g1
18397944	21	mov HV_FAST_PCI_IOMMU_MAP, %o5
bade5622	22	ta HV_FAST_TRAP
6a32fd4d DM	23	brnz,pn %o0, 1f
	24	sub %g0, %o0, %o0
	25	mov %o1, %o0
	26	1: retl
	27	nop
fefbbc73	28	ENDPROC(pci_sun4v_iommu_map)
bade5622 DM	29
	30	/* %o0: devhandle
	31	* %o1: tsbid
	32	* %o2: num ttes
	33	*
	34	* returns %o0: num ttes demapped
	35	*/
fefbbc73	36	ENTRY(pci_sun4v_iommu_demap)
18397944	37	mov HV_FAST_PCI_IOMMU_DEMAP, %o5
bade5622 DM	38	ta HV_FAST_TRAP
	39	retl
	40	mov %o1, %o0
fefbbc73	41	ENDPROC(pci_sun4v_iommu_demap)
7eae642f	42
18397944 DM	43	/* %o0: devhandle
	44	* %o1: tsbid
	45	* %o2: &io_attributes
	46	* %o3: &real_address
	47	*
	48	* returns %o0: status
	49	*/
fefbbc73	50	ENTRY(pci_sun4v_iommu_getmap)
18397944 DM	51	mov %o2, %o4
	52	mov HV_FAST_PCI_IOMMU_GETMAP, %o5
	53	ta HV_FAST_TRAP
	54	stx %o1, [%o4]
	55	stx %o2, [%o3]
	56	retl
	57	mov %o0, %o0
fefbbc73	58	ENDPROC(pci_sun4v_iommu_getmap)
18397944	59
7eae642f DM	60	/* %o0: devhandle
	61	* %o1: pci_device
	62	* %o2: pci_config_offset
	63	* %o3: size
	64	*
	65	* returns %o0: data
	66	*
	67	* If there is an error, the data will be returned
	68	* as all 1's.
	69	*/
fefbbc73	70	ENTRY(pci_sun4v_config_get)
18397944	71	mov HV_FAST_PCI_CONFIG_GET, %o5
7eae642f DM	72	ta HV_FAST_TRAP
	73	brnz,a,pn %o1, 1f
	74	mov -1, %o2
	75	1: retl
	76	mov %o2, %o0
fefbbc73	77	ENDPROC(pci_sun4v_config_get)
7eae642f DM	78
	79	/* %o0: devhandle
	80	* %o1: pci_device
	81	* %o2: pci_config_offset
	82	* %o3: size
	83	* %o4: data
	84	*
	85	* returns %o0: status
	86	*
	87	* status will be zero if the operation completed
	88	* successfully, else -1 if not
	89	*/
fefbbc73	90	ENTRY(pci_sun4v_config_put)
18397944	91	mov HV_FAST_PCI_CONFIG_PUT, %o5
7eae642f DM	92	ta HV_FAST_TRAP
	93	brnz,a,pn %o1, 1f
	94	mov -1, %o1
	95	1: retl
	96	mov %o1, %o0
fefbbc73	97	ENDPROC(pci_sun4v_config_put)
35a17eb6 DM	98
	99	/* %o0: devhandle
	100	* %o1: msiqid
	101	* %o2: msiq phys address
	102	* %o3: num entries
	103	*
	104	* returns %o0: status
	105	*
	106	* status will be zero if the operation completed
	107	* successfully, else -1 if not
	108	*/
fefbbc73	109	ENTRY(pci_sun4v_msiq_conf)
35a17eb6 DM	110	mov HV_FAST_PCI_MSIQ_CONF, %o5
	111	ta HV_FAST_TRAP
	112	retl
	113	mov %o0, %o0
fefbbc73	114	ENDPROC(pci_sun4v_msiq_conf)
35a17eb6 DM	115
	116	/* %o0: devhandle
	117	* %o1: msiqid
	118	* %o2: &msiq_phys_addr
	119	* %o3: &msiq_num_entries
	120	*
	121	* returns %o0: status
	122	*/
fefbbc73	123	ENTRY(pci_sun4v_msiq_info)
35a17eb6 DM	124	mov %o2, %o4
	125	mov HV_FAST_PCI_MSIQ_INFO, %o5
	126	ta HV_FAST_TRAP
	127	stx %o1, [%o4]
	128	stx %o2, [%o3]
	129	retl
	130	mov %o0, %o0
fefbbc73	131	ENDPROC(pci_sun4v_msiq_info)
35a17eb6 DM	132
	133	/* %o0: devhandle
	134	* %o1: msiqid
	135	* %o2: &valid
	136	*
	137	* returns %o0: status
	138	*/
fefbbc73	139	ENTRY(pci_sun4v_msiq_getvalid)
35a17eb6 DM	140	mov HV_FAST_PCI_MSIQ_GETVALID, %o5
	141	ta HV_FAST_TRAP
	142	stx %o1, [%o2]
	143	retl
	144	mov %o0, %o0
fefbbc73	145	ENDPROC(pci_sun4v_msiq_getvalid)
35a17eb6 DM	146
	147	/* %o0: devhandle
	148	* %o1: msiqid
	149	* %o2: valid
	150	*
	151	* returns %o0: status
	152	*/
fefbbc73	153	ENTRY(pci_sun4v_msiq_setvalid)
35a17eb6 DM	154	mov HV_FAST_PCI_MSIQ_SETVALID, %o5
	155	ta HV_FAST_TRAP
	156	retl
	157	mov %o0, %o0
fefbbc73	158	ENDPROC(pci_sun4v_msiq_setvalid)
35a17eb6 DM	159
	160	/* %o0: devhandle
	161	* %o1: msiqid
	162	* %o2: &state
	163	*
	164	* returns %o0: status
	165	*/
fefbbc73	166	ENTRY(pci_sun4v_msiq_getstate)
35a17eb6 DM	167	mov HV_FAST_PCI_MSIQ_GETSTATE, %o5
	168	ta HV_FAST_TRAP
	169	stx %o1, [%o2]
	170	retl
	171	mov %o0, %o0
fefbbc73	172	ENDPROC(pci_sun4v_msiq_getstate)
35a17eb6 DM	173
	174	/* %o0: devhandle
	175	* %o1: msiqid
	176	* %o2: state
	177	*
	178	* returns %o0: status
	179	*/
fefbbc73	180	ENTRY(pci_sun4v_msiq_setstate)
35a17eb6 DM	181	mov HV_FAST_PCI_MSIQ_SETSTATE, %o5
	182	ta HV_FAST_TRAP
	183	retl
	184	mov %o0, %o0
fefbbc73	185	ENDPROC(pci_sun4v_msiq_setstate)
35a17eb6 DM	186
	187	/* %o0: devhandle
	188	* %o1: msiqid
	189	* %o2: &head
	190	*
	191	* returns %o0: status
	192	*/
fefbbc73	193	ENTRY(pci_sun4v_msiq_gethead)
35a17eb6 DM	194	mov HV_FAST_PCI_MSIQ_GETHEAD, %o5
	195	ta HV_FAST_TRAP
	196	stx %o1, [%o2]
	197	retl
	198	mov %o0, %o0
fefbbc73	199	ENDPROC(pci_sun4v_msiq_gethead)
35a17eb6 DM	200
	201	/* %o0: devhandle
	202	* %o1: msiqid
	203	* %o2: head
	204	*
	205	* returns %o0: status
	206	*/
fefbbc73	207	ENTRY(pci_sun4v_msiq_sethead)
35a17eb6 DM	208	mov HV_FAST_PCI_MSIQ_SETHEAD, %o5
	209	ta HV_FAST_TRAP
	210	retl
	211	mov %o0, %o0
fefbbc73	212	ENDPROC(pci_sun4v_msiq_sethead)
35a17eb6 DM	213
	214	/* %o0: devhandle
	215	* %o1: msiqid
	216	* %o2: &tail
	217	*
	218	* returns %o0: status
	219	*/
fefbbc73	220	ENTRY(pci_sun4v_msiq_gettail)
35a17eb6 DM	221	mov HV_FAST_PCI_MSIQ_GETTAIL, %o5
	222	ta HV_FAST_TRAP
	223	stx %o1, [%o2]
	224	retl
	225	mov %o0, %o0
fefbbc73	226	ENDPROC(pci_sun4v_msiq_gettail)
35a17eb6 DM	227
	228	/* %o0: devhandle
	229	* %o1: msinum
	230	* %o2: &valid
	231	*
	232	* returns %o0: status
	233	*/
fefbbc73	234	ENTRY(pci_sun4v_msi_getvalid)
35a17eb6 DM	235	mov HV_FAST_PCI_MSI_GETVALID, %o5
	236	ta HV_FAST_TRAP
	237	stx %o1, [%o2]
	238	retl
	239	mov %o0, %o0
fefbbc73	240	ENDPROC(pci_sun4v_msi_getvalid)
35a17eb6 DM	241
	242	/* %o0: devhandle
	243	* %o1: msinum
	244	* %o2: valid
	245	*
	246	* returns %o0: status
	247	*/
fefbbc73	248	ENTRY(pci_sun4v_msi_setvalid)
35a17eb6 DM	249	mov HV_FAST_PCI_MSI_SETVALID, %o5
	250	ta HV_FAST_TRAP
	251	retl
	252	mov %o0, %o0
fefbbc73	253	ENDPROC(pci_sun4v_msi_setvalid)
35a17eb6 DM	254
	255	/* %o0: devhandle
	256	* %o1: msinum
	257	* %o2: &msiq
	258	*
	259	* returns %o0: status
	260	*/
fefbbc73	261	ENTRY(pci_sun4v_msi_getmsiq)
35a17eb6 DM	262	mov HV_FAST_PCI_MSI_GETMSIQ, %o5
	263	ta HV_FAST_TRAP
	264	stx %o1, [%o2]
	265	retl
	266	mov %o0, %o0
fefbbc73	267	ENDPROC(pci_sun4v_msi_getmsiq)
35a17eb6 DM	268
	269	/* %o0: devhandle
	270	* %o1: msinum
	271	* %o2: msitype
	272	* %o3: msiq
	273	*
	274	* returns %o0: status
	275	*/
fefbbc73	276	ENTRY(pci_sun4v_msi_setmsiq)
35a17eb6 DM	277	mov HV_FAST_PCI_MSI_SETMSIQ, %o5
	278	ta HV_FAST_TRAP
	279	retl
	280	mov %o0, %o0
fefbbc73	281	ENDPROC(pci_sun4v_msi_setmsiq)
35a17eb6 DM	282
	283	/* %o0: devhandle
	284	* %o1: msinum
	285	* %o2: &state
	286	*
	287	* returns %o0: status
	288	*/
fefbbc73	289	ENTRY(pci_sun4v_msi_getstate)
35a17eb6 DM	290	mov HV_FAST_PCI_MSI_GETSTATE, %o5
	291	ta HV_FAST_TRAP
	292	stx %o1, [%o2]
	293	retl
	294	mov %o0, %o0
fefbbc73	295	ENDPROC(pci_sun4v_msi_getstate)
35a17eb6 DM	296
	297	/* %o0: devhandle
	298	* %o1: msinum
	299	* %o2: state
	300	*
	301	* returns %o0: status
	302	*/
fefbbc73	303	ENTRY(pci_sun4v_msi_setstate)
35a17eb6 DM	304	mov HV_FAST_PCI_MSI_SETSTATE, %o5
	305	ta HV_FAST_TRAP
	306	retl
	307	mov %o0, %o0
fefbbc73	308	ENDPROC(pci_sun4v_msi_setstate)
35a17eb6 DM	309
	310	/* %o0: devhandle
	311	* %o1: msinum
	312	* %o2: &msiq
	313	*
	314	* returns %o0: status
	315	*/
fefbbc73	316	ENTRY(pci_sun4v_msg_getmsiq)
35a17eb6 DM	317	mov HV_FAST_PCI_MSG_GETMSIQ, %o5
	318	ta HV_FAST_TRAP
	319	stx %o1, [%o2]
	320	retl
	321	mov %o0, %o0
fefbbc73	322	ENDPROC(pci_sun4v_msg_getmsiq)
35a17eb6 DM	323
	324	/* %o0: devhandle
	325	* %o1: msinum
	326	* %o2: msiq
	327	*
	328	* returns %o0: status
	329	*/
fefbbc73	330	ENTRY(pci_sun4v_msg_setmsiq)
35a17eb6 DM	331	mov HV_FAST_PCI_MSG_SETMSIQ, %o5
	332	ta HV_FAST_TRAP
	333	retl
	334	mov %o0, %o0
fefbbc73	335	ENDPROC(pci_sun4v_msg_setmsiq)
35a17eb6 DM	336
	337	/* %o0: devhandle
	338	* %o1: msinum
	339	* %o2: &valid
	340	*
	341	* returns %o0: status
	342	*/
fefbbc73	343	ENTRY(pci_sun4v_msg_getvalid)
35a17eb6 DM	344	mov HV_FAST_PCI_MSG_GETVALID, %o5
	345	ta HV_FAST_TRAP
	346	stx %o1, [%o2]
	347	retl
	348	mov %o0, %o0
fefbbc73	349	ENDPROC(pci_sun4v_msg_getvalid)
35a17eb6 DM	350
	351	/* %o0: devhandle
	352	* %o1: msinum
	353	* %o2: valid
	354	*
	355	* returns %o0: status
	356	*/
fefbbc73	357	ENTRY(pci_sun4v_msg_setvalid)
35a17eb6 DM	358	mov HV_FAST_PCI_MSG_SETVALID, %o5
	359	ta HV_FAST_TRAP
	360	retl
	361	mov %o0, %o0
fefbbc73	362	ENDPROC(pci_sun4v_msg_setvalid)
35a17eb6	363
f0248c15 TD	364	/*
	365	* %o0: devhandle
	366	* %o1: r_addr
	367	* %o2: size
	368	* %o3: pagesize
	369	* %o4: virt
	370	* %o5: &iotsb_num/&iotsb_handle
	371	*
	372	* returns %o0: status
	373	* %o1: iotsb_num/iotsb_handle
	374	*/
	375	ENTRY(pci_sun4v_iotsb_conf)
	376	mov %o5, %g1
	377	mov HV_FAST_PCI_IOTSB_CONF, %o5
	378	ta HV_FAST_TRAP
	379	retl
	380	stx %o1, [%g1]
	381	ENDPROC(pci_sun4v_iotsb_conf)
5116ab4e TD	382
	383	/*
	384	* %o0: devhandle
	385	* %o1: iotsb_num/iotsb_handle
	386	* %o2: pci_device
	387	*
	388	* returns %o0: status
	389	*/
	390	ENTRY(pci_sun4v_iotsb_bind)
	391	mov HV_FAST_PCI_IOTSB_BIND, %o5
	392	ta HV_FAST_TRAP
	393	retl
	394	nop
	395	ENDPROC(pci_sun4v_iotsb_bind)
f08978b0 TD	396
	397	/*
	398	* %o0: devhandle
	399	* %o1: iotsb_num/iotsb_handle
	400	* %o2: index_count
	401	* %o3: iotte_attributes
	402	* %o4: io_page_list_p
	403	* %o5: &mapped
	404	*
	405	* returns %o0: status
	406	* %o1: #mapped
	407	*/
	408	ENTRY(pci_sun4v_iotsb_map)
	409	mov %o5, %g1
	410	mov HV_FAST_PCI_IOTSB_MAP, %o5
	411	ta HV_FAST_TRAP
	412	retl
	413	stx %o1, [%g1]
	414	ENDPROC(pci_sun4v_iotsb_map)
	415
	416	/*
	417	* %o0: devhandle
	418	* %o1: iotsb_num/iotsb_handle
	419	* %o2: iotsb_index
	420	* %o3: #iottes
	421	* %o4: &demapped
	422	*
	423	* returns %o0: status
	424	* %o1: #demapped
	425	*/
	426	ENTRY(pci_sun4v_iotsb_demap)
	427	mov HV_FAST_PCI_IOTSB_DEMAP, %o5
	428	ta HV_FAST_TRAP
	429	retl
	430	stx %o1, [%o4]
	431	ENDPROC(pci_sun4v_iotsb_demap)