Commit | Line | Data |
---|---|---|
16ce82d8 | 1 | /* pci_sabre.c: Sabre specific PCI controller support. |
1da177e4 | 2 | * |
16ce82d8 | 3 | * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
4 | * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be) |
5 | * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com) | |
6 | */ | |
7 | ||
8 | #include <linux/kernel.h> | |
9 | #include <linux/types.h> | |
10 | #include <linux/pci.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/slab.h> | |
13 | #include <linux/interrupt.h> | |
764f2579 | 14 | #include <linux/of_device.h> |
1da177e4 LT |
15 | |
16 | #include <asm/apb.h> | |
1da177e4 LT |
17 | #include <asm/iommu.h> |
18 | #include <asm/irq.h> | |
e87dc350 | 19 | #include <asm/prom.h> |
87395fc6 | 20 | #include <asm/upa.h> |
1da177e4 LT |
21 | |
22 | #include "pci_impl.h" | |
23 | #include "iommu_common.h" | |
a21cff3e | 24 | #include "psycho_common.h" |
1da177e4 | 25 | |
edbe805b DM |
26 | #define DRIVER_NAME "sabre" |
27 | #define PFX DRIVER_NAME ": " | |
28 | ||
1da177e4 LT |
29 | /* SABRE PCI controller register offsets and definitions. */ |
30 | #define SABRE_UE_AFSR 0x0030UL | |
31 | #define SABRE_UEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */ | |
32 | #define SABRE_UEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */ | |
33 | #define SABRE_UEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */ | |
34 | #define SABRE_UEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */ | |
35 | #define SABRE_UEAFSR_SDTE 0x0200000000000000UL /* Secondary DMA Translation Error */ | |
36 | #define SABRE_UEAFSR_PDTE 0x0100000000000000UL /* Primary DMA Translation Error */ | |
37 | #define SABRE_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */ | |
38 | #define SABRE_UEAFSR_OFF 0x00000000e0000000UL /* Offset (AFAR bits [5:3] */ | |
39 | #define SABRE_UEAFSR_BLK 0x0000000000800000UL /* Was block operation */ | |
40 | #define SABRE_UECE_AFAR 0x0038UL | |
41 | #define SABRE_CE_AFSR 0x0040UL | |
42 | #define SABRE_CEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */ | |
43 | #define SABRE_CEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */ | |
44 | #define SABRE_CEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */ | |
45 | #define SABRE_CEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */ | |
46 | #define SABRE_CEAFSR_ESYND 0x00ff000000000000UL /* ECC Syndrome */ | |
47 | #define SABRE_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */ | |
48 | #define SABRE_CEAFSR_OFF 0x00000000e0000000UL /* Offset */ | |
49 | #define SABRE_CEAFSR_BLK 0x0000000000800000UL /* Was block operation */ | |
50 | #define SABRE_UECE_AFAR_ALIAS 0x0048UL /* Aliases to 0x0038 */ | |
51 | #define SABRE_IOMMU_CONTROL 0x0200UL | |
52 | #define SABRE_IOMMUCTRL_ERRSTS 0x0000000006000000UL /* Error status bits */ | |
53 | #define SABRE_IOMMUCTRL_ERR 0x0000000001000000UL /* Error present in IOTLB */ | |
54 | #define SABRE_IOMMUCTRL_LCKEN 0x0000000000800000UL /* IOTLB lock enable */ | |
55 | #define SABRE_IOMMUCTRL_LCKPTR 0x0000000000780000UL /* IOTLB lock pointer */ | |
56 | #define SABRE_IOMMUCTRL_TSBSZ 0x0000000000070000UL /* TSB Size */ | |
57 | #define SABRE_IOMMU_TSBSZ_1K 0x0000000000000000 | |
58 | #define SABRE_IOMMU_TSBSZ_2K 0x0000000000010000 | |
59 | #define SABRE_IOMMU_TSBSZ_4K 0x0000000000020000 | |
60 | #define SABRE_IOMMU_TSBSZ_8K 0x0000000000030000 | |
61 | #define SABRE_IOMMU_TSBSZ_16K 0x0000000000040000 | |
62 | #define SABRE_IOMMU_TSBSZ_32K 0x0000000000050000 | |
63 | #define SABRE_IOMMU_TSBSZ_64K 0x0000000000060000 | |
64 | #define SABRE_IOMMU_TSBSZ_128K 0x0000000000070000 | |
65 | #define SABRE_IOMMUCTRL_TBWSZ 0x0000000000000004UL /* TSB assumed page size */ | |
66 | #define SABRE_IOMMUCTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */ | |
67 | #define SABRE_IOMMUCTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */ | |
68 | #define SABRE_IOMMU_TSBBASE 0x0208UL | |
69 | #define SABRE_IOMMU_FLUSH 0x0210UL | |
70 | #define SABRE_IMAP_A_SLOT0 0x0c00UL | |
71 | #define SABRE_IMAP_B_SLOT0 0x0c20UL | |
72 | #define SABRE_IMAP_SCSI 0x1000UL | |
73 | #define SABRE_IMAP_ETH 0x1008UL | |
74 | #define SABRE_IMAP_BPP 0x1010UL | |
75 | #define SABRE_IMAP_AU_REC 0x1018UL | |
76 | #define SABRE_IMAP_AU_PLAY 0x1020UL | |
77 | #define SABRE_IMAP_PFAIL 0x1028UL | |
78 | #define SABRE_IMAP_KMS 0x1030UL | |
79 | #define SABRE_IMAP_FLPY 0x1038UL | |
80 | #define SABRE_IMAP_SHW 0x1040UL | |
81 | #define SABRE_IMAP_KBD 0x1048UL | |
82 | #define SABRE_IMAP_MS 0x1050UL | |
83 | #define SABRE_IMAP_SER 0x1058UL | |
84 | #define SABRE_IMAP_UE 0x1070UL | |
85 | #define SABRE_IMAP_CE 0x1078UL | |
86 | #define SABRE_IMAP_PCIERR 0x1080UL | |
87 | #define SABRE_IMAP_GFX 0x1098UL | |
88 | #define SABRE_IMAP_EUPA 0x10a0UL | |
89 | #define SABRE_ICLR_A_SLOT0 0x1400UL | |
90 | #define SABRE_ICLR_B_SLOT0 0x1480UL | |
91 | #define SABRE_ICLR_SCSI 0x1800UL | |
92 | #define SABRE_ICLR_ETH 0x1808UL | |
93 | #define SABRE_ICLR_BPP 0x1810UL | |
94 | #define SABRE_ICLR_AU_REC 0x1818UL | |
95 | #define SABRE_ICLR_AU_PLAY 0x1820UL | |
96 | #define SABRE_ICLR_PFAIL 0x1828UL | |
97 | #define SABRE_ICLR_KMS 0x1830UL | |
98 | #define SABRE_ICLR_FLPY 0x1838UL | |
99 | #define SABRE_ICLR_SHW 0x1840UL | |
100 | #define SABRE_ICLR_KBD 0x1848UL | |
101 | #define SABRE_ICLR_MS 0x1850UL | |
102 | #define SABRE_ICLR_SER 0x1858UL | |
103 | #define SABRE_ICLR_UE 0x1870UL | |
104 | #define SABRE_ICLR_CE 0x1878UL | |
105 | #define SABRE_ICLR_PCIERR 0x1880UL | |
106 | #define SABRE_WRSYNC 0x1c20UL | |
107 | #define SABRE_PCICTRL 0x2000UL | |
108 | #define SABRE_PCICTRL_MRLEN 0x0000001000000000UL /* Use MemoryReadLine for block loads/stores */ | |
109 | #define SABRE_PCICTRL_SERR 0x0000000400000000UL /* Set when SERR asserted on PCI bus */ | |
110 | #define SABRE_PCICTRL_ARBPARK 0x0000000000200000UL /* Bus Parking 0=Ultra-IIi 1=prev-bus-owner */ | |
111 | #define SABRE_PCICTRL_CPUPRIO 0x0000000000100000UL /* Ultra-IIi granted every other bus cycle */ | |
112 | #define SABRE_PCICTRL_ARBPRIO 0x00000000000f0000UL /* Slot which is granted every other bus cycle */ | |
113 | #define SABRE_PCICTRL_ERREN 0x0000000000000100UL /* PCI Error Interrupt Enable */ | |
114 | #define SABRE_PCICTRL_RTRYWE 0x0000000000000080UL /* DMA Flow Control 0=wait-if-possible 1=retry */ | |
115 | #define SABRE_PCICTRL_AEN 0x000000000000000fUL /* Slot PCI arbitration enables */ | |
116 | #define SABRE_PIOAFSR 0x2010UL | |
117 | #define SABRE_PIOAFSR_PMA 0x8000000000000000UL /* Primary Master Abort */ | |
118 | #define SABRE_PIOAFSR_PTA 0x4000000000000000UL /* Primary Target Abort */ | |
119 | #define SABRE_PIOAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */ | |
120 | #define SABRE_PIOAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */ | |
121 | #define SABRE_PIOAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort */ | |
122 | #define SABRE_PIOAFSR_STA 0x0400000000000000UL /* Secondary Target Abort */ | |
123 | #define SABRE_PIOAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */ | |
124 | #define SABRE_PIOAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */ | |
125 | #define SABRE_PIOAFSR_BMSK 0x0000ffff00000000UL /* Byte Mask */ | |
126 | #define SABRE_PIOAFSR_BLK 0x0000000080000000UL /* Was Block Operation */ | |
127 | #define SABRE_PIOAFAR 0x2018UL | |
128 | #define SABRE_PCIDIAG 0x2020UL | |
129 | #define SABRE_PCIDIAG_DRTRY 0x0000000000000040UL /* Disable PIO Retry Limit */ | |
130 | #define SABRE_PCIDIAG_IPAPAR 0x0000000000000008UL /* Invert PIO Address Parity */ | |
131 | #define SABRE_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO Data Parity */ | |
132 | #define SABRE_PCIDIAG_IDDPAR 0x0000000000000002UL /* Invert DMA Data Parity */ | |
133 | #define SABRE_PCIDIAG_ELPBK 0x0000000000000001UL /* Loopback Enable - not supported */ | |
134 | #define SABRE_PCITASR 0x2028UL | |
135 | #define SABRE_PCITASR_EF 0x0000000000000080UL /* Respond to 0xe0000000-0xffffffff */ | |
136 | #define SABRE_PCITASR_CD 0x0000000000000040UL /* Respond to 0xc0000000-0xdfffffff */ | |
137 | #define SABRE_PCITASR_AB 0x0000000000000020UL /* Respond to 0xa0000000-0xbfffffff */ | |
138 | #define SABRE_PCITASR_89 0x0000000000000010UL /* Respond to 0x80000000-0x9fffffff */ | |
139 | #define SABRE_PCITASR_67 0x0000000000000008UL /* Respond to 0x60000000-0x7fffffff */ | |
140 | #define SABRE_PCITASR_45 0x0000000000000004UL /* Respond to 0x40000000-0x5fffffff */ | |
141 | #define SABRE_PCITASR_23 0x0000000000000002UL /* Respond to 0x20000000-0x3fffffff */ | |
142 | #define SABRE_PCITASR_01 0x0000000000000001UL /* Respond to 0x00000000-0x1fffffff */ | |
143 | #define SABRE_PIOBUF_DIAG 0x5000UL | |
144 | #define SABRE_DMABUF_DIAGLO 0x5100UL | |
145 | #define SABRE_DMABUF_DIAGHI 0x51c0UL | |
146 | #define SABRE_IMAP_GFX_ALIAS 0x6000UL /* Aliases to 0x1098 */ | |
147 | #define SABRE_IMAP_EUPA_ALIAS 0x8000UL /* Aliases to 0x10a0 */ | |
148 | #define SABRE_IOMMU_VADIAG 0xa400UL | |
149 | #define SABRE_IOMMU_TCDIAG 0xa408UL | |
150 | #define SABRE_IOMMU_TAG 0xa580UL | |
151 | #define SABRE_IOMMUTAG_ERRSTS 0x0000000001800000UL /* Error status bits */ | |
152 | #define SABRE_IOMMUTAG_ERR 0x0000000000400000UL /* Error present */ | |
153 | #define SABRE_IOMMUTAG_WRITE 0x0000000000200000UL /* Page is writable */ | |
154 | #define SABRE_IOMMUTAG_STREAM 0x0000000000100000UL /* Streamable bit - unused */ | |
155 | #define SABRE_IOMMUTAG_SIZE 0x0000000000080000UL /* 0=8k 1=16k */ | |
156 | #define SABRE_IOMMUTAG_VPN 0x000000000007ffffUL /* Virtual Page Number [31:13] */ | |
157 | #define SABRE_IOMMU_DATA 0xa600UL | |
158 | #define SABRE_IOMMUDATA_VALID 0x0000000040000000UL /* Valid */ | |
159 | #define SABRE_IOMMUDATA_USED 0x0000000020000000UL /* Used (for LRU algorithm) */ | |
160 | #define SABRE_IOMMUDATA_CACHE 0x0000000010000000UL /* Cacheable */ | |
161 | #define SABRE_IOMMUDATA_PPN 0x00000000001fffffUL /* Physical Page Number [33:13] */ | |
162 | #define SABRE_PCI_IRQSTATE 0xa800UL | |
163 | #define SABRE_OBIO_IRQSTATE 0xa808UL | |
164 | #define SABRE_FFBCFG 0xf000UL | |
165 | #define SABRE_FFBCFG_SPRQS 0x000000000f000000 /* Slave P_RQST queue size */ | |
166 | #define SABRE_FFBCFG_ONEREAD 0x0000000000004000 /* Slave supports one outstanding read */ | |
167 | #define SABRE_MCCTRL0 0xf010UL | |
168 | #define SABRE_MCCTRL0_RENAB 0x0000000080000000 /* Refresh Enable */ | |
169 | #define SABRE_MCCTRL0_EENAB 0x0000000010000000 /* Enable all ECC functions */ | |
170 | #define SABRE_MCCTRL0_11BIT 0x0000000000001000 /* Enable 11-bit column addressing */ | |
171 | #define SABRE_MCCTRL0_DPP 0x0000000000000f00 /* DIMM Pair Present Bits */ | |
172 | #define SABRE_MCCTRL0_RINTVL 0x00000000000000ff /* Refresh Interval */ | |
173 | #define SABRE_MCCTRL1 0xf018UL | |
174 | #define SABRE_MCCTRL1_AMDC 0x0000000038000000 /* Advance Memdata Clock */ | |
175 | #define SABRE_MCCTRL1_ARDC 0x0000000007000000 /* Advance DRAM Read Data Clock */ | |
176 | #define SABRE_MCCTRL1_CSR 0x0000000000e00000 /* CAS to RAS delay for CBR refresh */ | |
177 | #define SABRE_MCCTRL1_CASRW 0x00000000001c0000 /* CAS length for read/write */ | |
178 | #define SABRE_MCCTRL1_RCD 0x0000000000038000 /* RAS to CAS delay */ | |
179 | #define SABRE_MCCTRL1_CP 0x0000000000007000 /* CAS Precharge */ | |
180 | #define SABRE_MCCTRL1_RP 0x0000000000000e00 /* RAS Precharge */ | |
181 | #define SABRE_MCCTRL1_RAS 0x00000000000001c0 /* Length of RAS for refresh */ | |
182 | #define SABRE_MCCTRL1_CASRW2 0x0000000000000038 /* Must be same as CASRW */ | |
183 | #define SABRE_MCCTRL1_RSC 0x0000000000000007 /* RAS after CAS hold time */ | |
184 | #define SABRE_RESETCTRL 0xf020UL | |
185 | ||
186 | #define SABRE_CONFIGSPACE 0x001000000UL | |
187 | #define SABRE_IOSPACE 0x002000000UL | |
188 | #define SABRE_IOSPACE_SIZE 0x000ffffffUL | |
189 | #define SABRE_MEMSPACE 0x100000000UL | |
190 | #define SABRE_MEMSPACE_SIZE 0x07fffffffUL | |
191 | ||
1da177e4 LT |
192 | static int hummingbird_p; |
193 | static struct pci_bus *sabre_root_bus; | |
194 | ||
6d24c8dc | 195 | static irqreturn_t sabre_ue_intr(int irq, void *dev_id) |
1da177e4 | 196 | { |
6c108f12 DM |
197 | struct pci_pbm_info *pbm = dev_id; |
198 | unsigned long afsr_reg = pbm->controller_regs + SABRE_UE_AFSR; | |
199 | unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR; | |
1da177e4 LT |
200 | unsigned long afsr, afar, error_bits; |
201 | int reported; | |
202 | ||
203 | /* Latch uncorrectable error status. */ | |
87395fc6 DM |
204 | afar = upa_readq(afar_reg); |
205 | afsr = upa_readq(afsr_reg); | |
1da177e4 LT |
206 | |
207 | /* Clear the primary/secondary error status bits. */ | |
208 | error_bits = afsr & | |
209 | (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR | | |
210 | SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR | | |
211 | SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE); | |
212 | if (!error_bits) | |
213 | return IRQ_NONE; | |
87395fc6 | 214 | upa_writeq(error_bits, afsr_reg); |
1da177e4 LT |
215 | |
216 | /* Log the error. */ | |
6c108f12 DM |
217 | printk("%s: Uncorrectable Error, primary error type[%s%s]\n", |
218 | pbm->name, | |
1da177e4 LT |
219 | ((error_bits & SABRE_UEAFSR_PDRD) ? |
220 | "DMA Read" : | |
221 | ((error_bits & SABRE_UEAFSR_PDWR) ? | |
222 | "DMA Write" : "???")), | |
223 | ((error_bits & SABRE_UEAFSR_PDTE) ? | |
224 | ":Translation Error" : "")); | |
6c108f12 DM |
225 | printk("%s: bytemask[%04lx] dword_offset[%lx] was_block(%d)\n", |
226 | pbm->name, | |
1da177e4 LT |
227 | (afsr & SABRE_UEAFSR_BMSK) >> 32UL, |
228 | (afsr & SABRE_UEAFSR_OFF) >> 29UL, | |
229 | ((afsr & SABRE_UEAFSR_BLK) ? 1 : 0)); | |
6c108f12 DM |
230 | printk("%s: UE AFAR [%016lx]\n", pbm->name, afar); |
231 | printk("%s: UE Secondary errors [", pbm->name); | |
1da177e4 LT |
232 | reported = 0; |
233 | if (afsr & SABRE_UEAFSR_SDRD) { | |
234 | reported++; | |
235 | printk("(DMA Read)"); | |
236 | } | |
237 | if (afsr & SABRE_UEAFSR_SDWR) { | |
238 | reported++; | |
239 | printk("(DMA Write)"); | |
240 | } | |
241 | if (afsr & SABRE_UEAFSR_SDTE) { | |
242 | reported++; | |
243 | printk("(Translation Error)"); | |
244 | } | |
245 | if (!reported) | |
246 | printk("(none)"); | |
247 | printk("]\n"); | |
248 | ||
249 | /* Interrogate IOMMU for error status. */ | |
e6e00372 | 250 | psycho_check_iommu_error(pbm, afsr, afar, UE_ERR); |
1da177e4 LT |
251 | |
252 | return IRQ_HANDLED; | |
253 | } | |
254 | ||
6d24c8dc | 255 | static irqreturn_t sabre_ce_intr(int irq, void *dev_id) |
1da177e4 | 256 | { |
6c108f12 DM |
257 | struct pci_pbm_info *pbm = dev_id; |
258 | unsigned long afsr_reg = pbm->controller_regs + SABRE_CE_AFSR; | |
259 | unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR; | |
1da177e4 LT |
260 | unsigned long afsr, afar, error_bits; |
261 | int reported; | |
262 | ||
263 | /* Latch error status. */ | |
87395fc6 DM |
264 | afar = upa_readq(afar_reg); |
265 | afsr = upa_readq(afsr_reg); | |
1da177e4 LT |
266 | |
267 | /* Clear primary/secondary error status bits. */ | |
268 | error_bits = afsr & | |
269 | (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR | | |
270 | SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR); | |
271 | if (!error_bits) | |
272 | return IRQ_NONE; | |
87395fc6 | 273 | upa_writeq(error_bits, afsr_reg); |
1da177e4 LT |
274 | |
275 | /* Log the error. */ | |
6c108f12 DM |
276 | printk("%s: Correctable Error, primary error type[%s]\n", |
277 | pbm->name, | |
1da177e4 LT |
278 | ((error_bits & SABRE_CEAFSR_PDRD) ? |
279 | "DMA Read" : | |
280 | ((error_bits & SABRE_CEAFSR_PDWR) ? | |
281 | "DMA Write" : "???"))); | |
282 | ||
283 | /* XXX Use syndrome and afar to print out module string just like | |
284 | * XXX UDB CE trap handler does... -DaveM | |
285 | */ | |
6c108f12 | 286 | printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] " |
1da177e4 | 287 | "was_block(%d)\n", |
6c108f12 | 288 | pbm->name, |
1da177e4 LT |
289 | (afsr & SABRE_CEAFSR_ESYND) >> 48UL, |
290 | (afsr & SABRE_CEAFSR_BMSK) >> 32UL, | |
291 | (afsr & SABRE_CEAFSR_OFF) >> 29UL, | |
292 | ((afsr & SABRE_CEAFSR_BLK) ? 1 : 0)); | |
6c108f12 DM |
293 | printk("%s: CE AFAR [%016lx]\n", pbm->name, afar); |
294 | printk("%s: CE Secondary errors [", pbm->name); | |
1da177e4 LT |
295 | reported = 0; |
296 | if (afsr & SABRE_CEAFSR_SDRD) { | |
297 | reported++; | |
298 | printk("(DMA Read)"); | |
299 | } | |
300 | if (afsr & SABRE_CEAFSR_SDWR) { | |
301 | reported++; | |
302 | printk("(DMA Write)"); | |
303 | } | |
304 | if (!reported) | |
305 | printk("(none)"); | |
306 | printk("]\n"); | |
307 | ||
308 | return IRQ_HANDLED; | |
309 | } | |
310 | ||
34768bc8 | 311 | static void sabre_register_error_handlers(struct pci_pbm_info *pbm) |
1da177e4 | 312 | { |
61c7a080 | 313 | struct device_node *dp = pbm->op->dev.of_node; |
2b1e5978 | 314 | struct of_device *op; |
1da177e4 | 315 | unsigned long base = pbm->controller_regs; |
1da177e4 | 316 | u64 tmp; |
af80318e | 317 | int err; |
1da177e4 | 318 | |
2b1e5978 DM |
319 | if (pbm->chip_type == PBM_CHIP_TYPE_SABRE) |
320 | dp = dp->parent; | |
321 | ||
322 | op = of_find_device_by_node(dp); | |
323 | if (!op) | |
324 | return; | |
325 | ||
326 | /* Sabre/Hummingbird IRQ property layout is: | |
327 | * 0: PCI ERR | |
328 | * 1: UE ERR | |
329 | * 2: CE ERR | |
330 | * 3: POWER FAIL | |
331 | */ | |
332 | if (op->num_irqs < 4) | |
333 | return; | |
334 | ||
1da177e4 LT |
335 | /* We clear the error bits in the appropriate AFSR before |
336 | * registering the handler so that we don't get spurious | |
337 | * interrupts. | |
338 | */ | |
87395fc6 DM |
339 | upa_writeq((SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR | |
340 | SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR | | |
341 | SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE), | |
342 | base + SABRE_UE_AFSR); | |
2b1e5978 | 343 | |
af80318e DM |
344 | err = request_irq(op->irqs[1], sabre_ue_intr, 0, "SABRE_UE", pbm); |
345 | if (err) | |
346 | printk(KERN_WARNING "%s: Couldn't register UE, err=%d.\n", | |
347 | pbm->name, err); | |
1da177e4 | 348 | |
87395fc6 DM |
349 | upa_writeq((SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR | |
350 | SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR), | |
351 | base + SABRE_CE_AFSR); | |
352 | ||
1da177e4 | 353 | |
af80318e DM |
354 | err = request_irq(op->irqs[2], sabre_ce_intr, 0, "SABRE_CE", pbm); |
355 | if (err) | |
356 | printk(KERN_WARNING "%s: Couldn't register CE, err=%d.\n", | |
357 | pbm->name, err); | |
e6e00372 | 358 | err = request_irq(op->irqs[0], psycho_pcierr_intr, 0, |
af80318e DM |
359 | "SABRE_PCIERR", pbm); |
360 | if (err) | |
361 | printk(KERN_WARNING "%s: Couldn't register PCIERR, err=%d.\n", | |
362 | pbm->name, err); | |
1da177e4 | 363 | |
87395fc6 | 364 | tmp = upa_readq(base + SABRE_PCICTRL); |
1da177e4 | 365 | tmp |= SABRE_PCICTRL_ERREN; |
87395fc6 | 366 | upa_writeq(tmp, base + SABRE_PCICTRL); |
1da177e4 LT |
367 | } |
368 | ||
34768bc8 | 369 | static void apb_init(struct pci_bus *sabre_bus) |
1da177e4 LT |
370 | { |
371 | struct pci_dev *pdev; | |
372 | ||
373 | list_for_each_entry(pdev, &sabre_bus->devices, bus_list) { | |
1da177e4 LT |
374 | if (pdev->vendor == PCI_VENDOR_ID_SUN && |
375 | pdev->device == PCI_DEVICE_ID_SUN_SIMBA) { | |
1da177e4 LT |
376 | u16 word16; |
377 | ||
01f94c4a | 378 | pci_read_config_word(pdev, PCI_COMMAND, &word16); |
1da177e4 LT |
379 | word16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY | |
380 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | | |
381 | PCI_COMMAND_IO; | |
01f94c4a | 382 | pci_write_config_word(pdev, PCI_COMMAND, word16); |
1da177e4 LT |
383 | |
384 | /* Status register bits are "write 1 to clear". */ | |
01f94c4a DM |
385 | pci_write_config_word(pdev, PCI_STATUS, 0xffff); |
386 | pci_write_config_word(pdev, PCI_SEC_STATUS, 0xffff); | |
1da177e4 LT |
387 | |
388 | /* Use a primary/seconday latency timer value | |
389 | * of 64. | |
390 | */ | |
01f94c4a DM |
391 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64); |
392 | pci_write_config_byte(pdev, PCI_SEC_LATENCY_TIMER, 64); | |
1da177e4 LT |
393 | |
394 | /* Enable reporting/forwarding of master aborts, | |
395 | * parity, and SERR. | |
396 | */ | |
01f94c4a DM |
397 | pci_write_config_byte(pdev, PCI_BRIDGE_CONTROL, |
398 | (PCI_BRIDGE_CTL_PARITY | | |
399 | PCI_BRIDGE_CTL_SERR | | |
400 | PCI_BRIDGE_CTL_MASTER_ABORT)); | |
1da177e4 LT |
401 | } |
402 | } | |
403 | } | |
404 | ||
9a2ed5cc DM |
405 | static void __devinit sabre_scan_bus(struct pci_pbm_info *pbm, |
406 | struct device *parent) | |
1da177e4 LT |
407 | { |
408 | static int once; | |
1da177e4 LT |
409 | |
410 | /* The APB bridge speaks to the Sabre host PCI bridge | |
411 | * at 66Mhz, but the front side of APB runs at 33Mhz | |
412 | * for both segments. | |
321566c2 DM |
413 | * |
414 | * Hummingbird systems do not use APB, so they run | |
415 | * at 66MHZ. | |
1da177e4 | 416 | */ |
321566c2 DM |
417 | if (hummingbird_p) |
418 | pbm->is_66mhz_capable = 1; | |
419 | else | |
420 | pbm->is_66mhz_capable = 0; | |
1da177e4 LT |
421 | |
422 | /* This driver has not been verified to handle | |
423 | * multiple SABREs yet, so trap this. | |
424 | * | |
425 | * Also note that the SABRE host bridge is hardwired | |
426 | * to live at bus 0. | |
427 | */ | |
428 | if (once != 0) { | |
edbe805b DM |
429 | printk(KERN_ERR PFX "Multiple controllers unsupported.\n"); |
430 | return; | |
1da177e4 LT |
431 | } |
432 | once++; | |
433 | ||
e822358a | 434 | pbm->pci_bus = pci_scan_one_pbm(pbm, parent); |
321566c2 | 435 | if (!pbm->pci_bus) |
a2fb23af | 436 | return; |
1da177e4 | 437 | |
321566c2 | 438 | sabre_root_bus = pbm->pci_bus; |
1da177e4 | 439 | |
321566c2 | 440 | apb_init(pbm->pci_bus); |
1da177e4 | 441 | |
34768bc8 | 442 | sabre_register_error_handlers(pbm); |
1da177e4 LT |
443 | } |
444 | ||
9a2ed5cc DM |
445 | static void __devinit sabre_pbm_init(struct pci_pbm_info *pbm, |
446 | struct of_device *op) | |
1da177e4 | 447 | { |
1c03a55c | 448 | psycho_pbm_init_common(pbm, op, "SABRE", PBM_CHIP_TYPE_SABRE); |
e6e00372 DM |
449 | pbm->pci_afsr = pbm->controller_regs + SABRE_PIOAFSR; |
450 | pbm->pci_afar = pbm->controller_regs + SABRE_PIOAFAR; | |
451 | pbm->pci_csr = pbm->controller_regs + SABRE_PCICTRL; | |
e822358a | 452 | sabre_scan_bus(pbm, &op->dev); |
1da177e4 LT |
453 | } |
454 | ||
edbe805b DM |
455 | static int __devinit sabre_probe(struct of_device *op, |
456 | const struct of_device_id *match) | |
1da177e4 | 457 | { |
a165b420 | 458 | const struct linux_prom64_registers *pr_regs; |
61c7a080 | 459 | struct device_node *dp = op->dev.of_node; |
28113a99 | 460 | struct pci_pbm_info *pbm; |
edbe805b | 461 | u32 upa_portid, dma_mask; |
16ce82d8 | 462 | struct iommu *iommu; |
edbe805b | 463 | int tsbsize, err; |
a165b420 | 464 | const u32 *vdma; |
1da177e4 LT |
465 | u64 clear_irq; |
466 | ||
edbe805b DM |
467 | hummingbird_p = (match->data != NULL); |
468 | if (!hummingbird_p) { | |
469 | struct device_node *cpu_dp; | |
470 | ||
471 | /* Of course, Sun has to encode things a thousand | |
472 | * different ways, inconsistently. | |
473 | */ | |
474 | for_each_node_by_type(cpu_dp, "cpu") { | |
475 | if (!strcmp(cpu_dp->name, "SUNW,UltraSPARC-IIe")) | |
476 | hummingbird_p = 1; | |
1da177e4 LT |
477 | } |
478 | } | |
479 | ||
edbe805b | 480 | err = -ENOMEM; |
d3ae4b5b DM |
481 | pbm = kzalloc(sizeof(*pbm), GFP_KERNEL); |
482 | if (!pbm) { | |
483 | printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n"); | |
d7472c38 | 484 | goto out_err; |
edbe805b | 485 | } |
1da177e4 | 486 | |
d3ae4b5b | 487 | iommu = kzalloc(sizeof(*iommu), GFP_KERNEL); |
edbe805b DM |
488 | if (!iommu) { |
489 | printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n"); | |
d7472c38 | 490 | goto out_free_controller; |
edbe805b DM |
491 | } |
492 | ||
28113a99 | 493 | pbm->iommu = iommu; |
1da177e4 | 494 | |
01f94c4a | 495 | upa_portid = of_getintprop_default(dp, "upa-portid", 0xff); |
1da177e4 | 496 | |
28113a99 | 497 | pbm->portid = upa_portid; |
1da177e4 LT |
498 | |
499 | /* | |
500 | * Map in SABRE register set and report the presence of this SABRE. | |
501 | */ | |
e87dc350 | 502 | |
01f94c4a | 503 | pr_regs = of_get_property(dp, "reg", NULL); |
edbe805b DM |
504 | err = -ENODEV; |
505 | if (!pr_regs) { | |
506 | printk(KERN_ERR PFX "No reg property\n"); | |
d7472c38 | 507 | goto out_free_iommu; |
edbe805b | 508 | } |
1da177e4 LT |
509 | |
510 | /* | |
511 | * First REG in property is base of entire SABRE register space. | |
512 | */ | |
28113a99 | 513 | pbm->controller_regs = pr_regs[0].phys_addr; |
1da177e4 | 514 | |
1da177e4 LT |
515 | /* Clear interrupts */ |
516 | ||
517 | /* PCI first */ | |
518 | for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8) | |
87395fc6 | 519 | upa_writeq(0x0UL, pbm->controller_regs + clear_irq); |
1da177e4 LT |
520 | |
521 | /* Then OBIO */ | |
522 | for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8) | |
87395fc6 | 523 | upa_writeq(0x0UL, pbm->controller_regs + clear_irq); |
1da177e4 LT |
524 | |
525 | /* Error interrupts are enabled later after the bus scan. */ | |
87395fc6 DM |
526 | upa_writeq((SABRE_PCICTRL_MRLEN | SABRE_PCICTRL_SERR | |
527 | SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN), | |
528 | pbm->controller_regs + SABRE_PCICTRL); | |
1da177e4 LT |
529 | |
530 | /* Now map in PCI config space for entire SABRE. */ | |
d3ae4b5b | 531 | pbm->config_space = pbm->controller_regs + SABRE_CONFIGSPACE; |
e87dc350 | 532 | |
01f94c4a | 533 | vdma = of_get_property(dp, "virtual-dma", NULL); |
edbe805b DM |
534 | if (!vdma) { |
535 | printk(KERN_ERR PFX "No virtual-dma property\n"); | |
d7472c38 | 536 | goto out_free_iommu; |
edbe805b | 537 | } |
1da177e4 LT |
538 | |
539 | dma_mask = vdma[0]; | |
540 | switch(vdma[1]) { | |
541 | case 0x20000000: | |
542 | dma_mask |= 0x1fffffff; | |
543 | tsbsize = 64; | |
544 | break; | |
545 | case 0x40000000: | |
546 | dma_mask |= 0x3fffffff; | |
547 | tsbsize = 128; | |
548 | break; | |
549 | ||
550 | case 0x80000000: | |
551 | dma_mask |= 0x7fffffff; | |
552 | tsbsize = 128; | |
553 | break; | |
554 | default: | |
edbe805b | 555 | printk(KERN_ERR PFX "Strange virtual-dma size.\n"); |
d7472c38 | 556 | goto out_free_iommu; |
1da177e4 LT |
557 | } |
558 | ||
a21cff3e | 559 | err = psycho_iommu_init(pbm, tsbsize, vdma[0], dma_mask, SABRE_WRSYNC); |
edbe805b | 560 | if (err) |
d7472c38 | 561 | goto out_free_iommu; |
1da177e4 | 562 | |
1da177e4 LT |
563 | /* |
564 | * Look for APB underneath. | |
565 | */ | |
d3ae4b5b DM |
566 | sabre_pbm_init(pbm, op); |
567 | ||
568 | pbm->next = pci_pbm_root; | |
569 | pci_pbm_root = pbm; | |
570 | ||
571 | dev_set_drvdata(&op->dev, pbm); | |
572 | ||
edbe805b | 573 | return 0; |
ad7ad57c | 574 | |
d7472c38 | 575 | out_free_iommu: |
d3ae4b5b | 576 | kfree(pbm->iommu); |
d7472c38 DM |
577 | |
578 | out_free_controller: | |
d3ae4b5b | 579 | kfree(pbm); |
d7472c38 DM |
580 | |
581 | out_err: | |
edbe805b | 582 | return err; |
1da177e4 | 583 | } |
edbe805b | 584 | |
fd098316 | 585 | static struct of_device_id __initdata sabre_match[] = { |
edbe805b DM |
586 | { |
587 | .name = "pci", | |
588 | .compatible = "pci108e,a001", | |
589 | .data = (void *) 1, | |
590 | }, | |
591 | { | |
592 | .name = "pci", | |
593 | .compatible = "pci108e,a000", | |
594 | }, | |
595 | {}, | |
596 | }; | |
597 | ||
598 | static struct of_platform_driver sabre_driver = { | |
4018294b GL |
599 | .driver = { |
600 | .name = DRIVER_NAME, | |
601 | .owner = THIS_MODULE, | |
602 | .of_match_table = sabre_match, | |
603 | }, | |
edbe805b DM |
604 | .probe = sabre_probe, |
605 | }; | |
606 | ||
607 | static int __init sabre_init(void) | |
608 | { | |
609 | return of_register_driver(&sabre_driver, &of_bus_type); | |
610 | } | |
611 | ||
612 | subsys_initcall(sabre_init); |