Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
9fd8b647 | 2 | /* pci_psycho.c: PSYCHO/U2P specific PCI controller support. |
1da177e4 | 3 | * |
9fd8b647 | 4 | * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
5 | * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be) |
6 | * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com) | |
7 | */ | |
8 | ||
9 | #include <linux/kernel.h> | |
10 | #include <linux/types.h> | |
11 | #include <linux/pci.h> | |
12 | #include <linux/init.h> | |
7b64db60 | 13 | #include <linux/export.h> |
1da177e4 LT |
14 | #include <linux/slab.h> |
15 | #include <linux/interrupt.h> | |
764f2579 | 16 | #include <linux/of_device.h> |
1da177e4 | 17 | |
1da177e4 LT |
18 | #include <asm/iommu.h> |
19 | #include <asm/irq.h> | |
20 | #include <asm/starfire.h> | |
e87dc350 | 21 | #include <asm/prom.h> |
87395fc6 | 22 | #include <asm/upa.h> |
1da177e4 LT |
23 | |
24 | #include "pci_impl.h" | |
25 | #include "iommu_common.h" | |
a21cff3e | 26 | #include "psycho_common.h" |
1da177e4 | 27 | |
b20bfe41 DM |
28 | #define DRIVER_NAME "psycho" |
29 | #define PFX DRIVER_NAME ": " | |
30 | ||
1da177e4 LT |
31 | /* Misc. PSYCHO PCI controller register offsets and definitions. */ |
32 | #define PSYCHO_CONTROL 0x0010UL | |
33 | #define PSYCHO_CONTROL_IMPL 0xf000000000000000UL /* Implementation of this PSYCHO*/ | |
34 | #define PSYCHO_CONTROL_VER 0x0f00000000000000UL /* Version of this PSYCHO */ | |
35 | #define PSYCHO_CONTROL_MID 0x00f8000000000000UL /* UPA Module ID of PSYCHO */ | |
36 | #define PSYCHO_CONTROL_IGN 0x0007c00000000000UL /* Interrupt Group Number */ | |
37 | #define PSYCHO_CONTROL_RESV 0x00003ffffffffff0UL /* Reserved */ | |
38 | #define PSYCHO_CONTROL_APCKEN 0x0000000000000008UL /* Address Parity Check Enable */ | |
39 | #define PSYCHO_CONTROL_APERR 0x0000000000000004UL /* Incoming System Addr Parerr */ | |
40 | #define PSYCHO_CONTROL_IAP 0x0000000000000002UL /* Invert UPA Parity */ | |
41 | #define PSYCHO_CONTROL_MODE 0x0000000000000001UL /* PSYCHO clock mode */ | |
42 | #define PSYCHO_PCIA_CTRL 0x2000UL | |
43 | #define PSYCHO_PCIB_CTRL 0x4000UL | |
44 | #define PSYCHO_PCICTRL_RESV1 0xfffffff000000000UL /* Reserved */ | |
45 | #define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL /* Streaming byte hole error */ | |
46 | #define PSYCHO_PCICTRL_SERR 0x0000000400000000UL /* SERR signal asserted */ | |
47 | #define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */ | |
48 | #define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000UL /* Reserved */ | |
49 | #define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */ | |
50 | #define PSYCHO_PCICTRL_RESV3 0x00000000001ff800UL /* Reserved */ | |
51 | #define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400UL /* Streaming byte hole int enab */ | |
52 | #define PSYCHO_PCICTRL_WEN 0x0000000000000200UL /* Power Mgmt Wake Enable */ | |
53 | #define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */ | |
54 | #define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */ | |
55 | #define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */ | |
56 | ||
1da177e4 | 57 | /* PSYCHO error handling support. */ |
1da177e4 LT |
58 | |
59 | /* Helper function of IOMMU error checking, which checks out | |
60 | * the state of the streaming buffers. The IOMMU lock is | |
61 | * held when this is called. | |
62 | * | |
63 | * For the PCI error case we know which PBM (and thus which | |
64 | * streaming buffer) caused the error, but for the uncorrectable | |
65 | * error case we do not. So we always check both streaming caches. | |
66 | */ | |
67 | #define PSYCHO_STRBUF_CONTROL_A 0x2800UL | |
68 | #define PSYCHO_STRBUF_CONTROL_B 0x4800UL | |
69 | #define PSYCHO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */ | |
70 | #define PSYCHO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */ | |
71 | #define PSYCHO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */ | |
72 | #define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */ | |
73 | #define PSYCHO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */ | |
74 | #define PSYCHO_STRBUF_FLUSH_A 0x2808UL | |
75 | #define PSYCHO_STRBUF_FLUSH_B 0x4808UL | |
76 | #define PSYCHO_STRBUF_FSYNC_A 0x2810UL | |
77 | #define PSYCHO_STRBUF_FSYNC_B 0x4810UL | |
78 | #define PSYCHO_STC_DATA_A 0xb000UL | |
79 | #define PSYCHO_STC_DATA_B 0xc000UL | |
80 | #define PSYCHO_STC_ERR_A 0xb400UL | |
81 | #define PSYCHO_STC_ERR_B 0xc400UL | |
1da177e4 LT |
82 | #define PSYCHO_STC_TAG_A 0xb800UL |
83 | #define PSYCHO_STC_TAG_B 0xc800UL | |
1da177e4 LT |
84 | #define PSYCHO_STC_LINE_A 0xb900UL |
85 | #define PSYCHO_STC_LINE_B 0xc900UL | |
1da177e4 | 86 | |
1da177e4 LT |
87 | /* When an Uncorrectable Error or a PCI Error happens, we |
88 | * interrogate the IOMMU state to see if it is the cause. | |
89 | */ | |
90 | #define PSYCHO_IOMMU_CONTROL 0x0200UL | |
91 | #define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */ | |
92 | #define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */ | |
93 | #define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */ | |
94 | #define PSYCHO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */ | |
95 | #define PSYCHO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */ | |
96 | #define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */ | |
97 | #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */ | |
98 | #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */ | |
99 | #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */ | |
100 | #define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */ | |
101 | #define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */ | |
102 | #define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */ | |
103 | #define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */ | |
104 | #define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */ | |
105 | #define PSYCHO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */ | |
106 | #define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */ | |
107 | #define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */ | |
108 | #define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */ | |
109 | #define PSYCHO_IOMMU_TSBBASE 0x0208UL | |
110 | #define PSYCHO_IOMMU_FLUSH 0x0210UL | |
111 | #define PSYCHO_IOMMU_TAG 0xa580UL | |
1da177e4 | 112 | #define PSYCHO_IOMMU_DATA 0xa600UL |
1da177e4 LT |
113 | |
114 | /* Uncorrectable Errors. Cause of the error and the address are | |
115 | * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors | |
116 | * relating to UPA interface transactions. | |
117 | */ | |
118 | #define PSYCHO_UE_AFSR 0x0030UL | |
119 | #define PSYCHO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */ | |
120 | #define PSYCHO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */ | |
121 | #define PSYCHO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */ | |
122 | #define PSYCHO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */ | |
123 | #define PSYCHO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */ | |
124 | #define PSYCHO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/ | |
125 | #define PSYCHO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */ | |
126 | #define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */ | |
127 | #define PSYCHO_UEAFSR_DOFF 0x00000000e0000000UL /* Doubleword Offset */ | |
128 | #define PSYCHO_UEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */ | |
129 | #define PSYCHO_UEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */ | |
130 | #define PSYCHO_UEAFSR_RESV2 0x00000000007fffffUL /* Reserved */ | |
131 | #define PSYCHO_UE_AFAR 0x0038UL | |
132 | ||
6d24c8dc | 133 | static irqreturn_t psycho_ue_intr(int irq, void *dev_id) |
1da177e4 | 134 | { |
34768bc8 | 135 | struct pci_pbm_info *pbm = dev_id; |
34768bc8 DM |
136 | unsigned long afsr_reg = pbm->controller_regs + PSYCHO_UE_AFSR; |
137 | unsigned long afar_reg = pbm->controller_regs + PSYCHO_UE_AFAR; | |
1da177e4 LT |
138 | unsigned long afsr, afar, error_bits; |
139 | int reported; | |
140 | ||
141 | /* Latch uncorrectable error status. */ | |
87395fc6 DM |
142 | afar = upa_readq(afar_reg); |
143 | afsr = upa_readq(afsr_reg); | |
1da177e4 LT |
144 | |
145 | /* Clear the primary/secondary error status bits. */ | |
146 | error_bits = afsr & | |
147 | (PSYCHO_UEAFSR_PPIO | PSYCHO_UEAFSR_PDRD | PSYCHO_UEAFSR_PDWR | | |
148 | PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR); | |
149 | if (!error_bits) | |
150 | return IRQ_NONE; | |
87395fc6 | 151 | upa_writeq(error_bits, afsr_reg); |
1da177e4 LT |
152 | |
153 | /* Log the error. */ | |
6c108f12 DM |
154 | printk("%s: Uncorrectable Error, primary error type[%s]\n", |
155 | pbm->name, | |
1da177e4 LT |
156 | (((error_bits & PSYCHO_UEAFSR_PPIO) ? |
157 | "PIO" : | |
158 | ((error_bits & PSYCHO_UEAFSR_PDRD) ? | |
159 | "DMA Read" : | |
160 | ((error_bits & PSYCHO_UEAFSR_PDWR) ? | |
161 | "DMA Write" : "???"))))); | |
6c108f12 DM |
162 | printk("%s: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n", |
163 | pbm->name, | |
1da177e4 LT |
164 | (afsr & PSYCHO_UEAFSR_BMSK) >> 32UL, |
165 | (afsr & PSYCHO_UEAFSR_DOFF) >> 29UL, | |
166 | (afsr & PSYCHO_UEAFSR_MID) >> 24UL, | |
167 | ((afsr & PSYCHO_UEAFSR_BLK) ? 1 : 0)); | |
6c108f12 DM |
168 | printk("%s: UE AFAR [%016lx]\n", pbm->name, afar); |
169 | printk("%s: UE Secondary errors [", pbm->name); | |
1da177e4 LT |
170 | reported = 0; |
171 | if (afsr & PSYCHO_UEAFSR_SPIO) { | |
172 | reported++; | |
173 | printk("(PIO)"); | |
174 | } | |
175 | if (afsr & PSYCHO_UEAFSR_SDRD) { | |
176 | reported++; | |
177 | printk("(DMA Read)"); | |
178 | } | |
179 | if (afsr & PSYCHO_UEAFSR_SDWR) { | |
180 | reported++; | |
181 | printk("(DMA Write)"); | |
182 | } | |
183 | if (!reported) | |
184 | printk("(none)"); | |
185 | printk("]\n"); | |
186 | ||
34768bc8 | 187 | /* Interrogate both IOMMUs for error status. */ |
d3ae4b5b DM |
188 | psycho_check_iommu_error(pbm, afsr, afar, UE_ERR); |
189 | if (pbm->sibling) | |
190 | psycho_check_iommu_error(pbm->sibling, afsr, afar, UE_ERR); | |
1da177e4 LT |
191 | |
192 | return IRQ_HANDLED; | |
193 | } | |
194 | ||
195 | /* Correctable Errors. */ | |
196 | #define PSYCHO_CE_AFSR 0x0040UL | |
197 | #define PSYCHO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */ | |
198 | #define PSYCHO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */ | |
199 | #define PSYCHO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */ | |
200 | #define PSYCHO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */ | |
201 | #define PSYCHO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */ | |
202 | #define PSYCHO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/ | |
203 | #define PSYCHO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */ | |
204 | #define PSYCHO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */ | |
205 | #define PSYCHO_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */ | |
206 | #define PSYCHO_CEAFSR_DOFF 0x00000000e0000000UL /* Double Offset */ | |
207 | #define PSYCHO_CEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */ | |
208 | #define PSYCHO_CEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */ | |
209 | #define PSYCHO_CEAFSR_RESV2 0x00000000007fffffUL /* Reserved */ | |
210 | #define PSYCHO_CE_AFAR 0x0040UL | |
211 | ||
6d24c8dc | 212 | static irqreturn_t psycho_ce_intr(int irq, void *dev_id) |
1da177e4 | 213 | { |
34768bc8 | 214 | struct pci_pbm_info *pbm = dev_id; |
34768bc8 DM |
215 | unsigned long afsr_reg = pbm->controller_regs + PSYCHO_CE_AFSR; |
216 | unsigned long afar_reg = pbm->controller_regs + PSYCHO_CE_AFAR; | |
1da177e4 LT |
217 | unsigned long afsr, afar, error_bits; |
218 | int reported; | |
219 | ||
220 | /* Latch error status. */ | |
87395fc6 DM |
221 | afar = upa_readq(afar_reg); |
222 | afsr = upa_readq(afsr_reg); | |
1da177e4 LT |
223 | |
224 | /* Clear primary/secondary error status bits. */ | |
225 | error_bits = afsr & | |
226 | (PSYCHO_CEAFSR_PPIO | PSYCHO_CEAFSR_PDRD | PSYCHO_CEAFSR_PDWR | | |
227 | PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR); | |
228 | if (!error_bits) | |
229 | return IRQ_NONE; | |
87395fc6 | 230 | upa_writeq(error_bits, afsr_reg); |
1da177e4 LT |
231 | |
232 | /* Log the error. */ | |
6c108f12 DM |
233 | printk("%s: Correctable Error, primary error type[%s]\n", |
234 | pbm->name, | |
1da177e4 LT |
235 | (((error_bits & PSYCHO_CEAFSR_PPIO) ? |
236 | "PIO" : | |
237 | ((error_bits & PSYCHO_CEAFSR_PDRD) ? | |
238 | "DMA Read" : | |
239 | ((error_bits & PSYCHO_CEAFSR_PDWR) ? | |
240 | "DMA Write" : "???"))))); | |
241 | ||
242 | /* XXX Use syndrome and afar to print out module string just like | |
243 | * XXX UDB CE trap handler does... -DaveM | |
244 | */ | |
6c108f12 | 245 | printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] " |
1da177e4 | 246 | "UPA_MID[%02lx] was_block(%d)\n", |
6c108f12 | 247 | pbm->name, |
1da177e4 LT |
248 | (afsr & PSYCHO_CEAFSR_ESYND) >> 48UL, |
249 | (afsr & PSYCHO_CEAFSR_BMSK) >> 32UL, | |
250 | (afsr & PSYCHO_CEAFSR_DOFF) >> 29UL, | |
251 | (afsr & PSYCHO_CEAFSR_MID) >> 24UL, | |
252 | ((afsr & PSYCHO_CEAFSR_BLK) ? 1 : 0)); | |
6c108f12 DM |
253 | printk("%s: CE AFAR [%016lx]\n", pbm->name, afar); |
254 | printk("%s: CE Secondary errors [", pbm->name); | |
1da177e4 LT |
255 | reported = 0; |
256 | if (afsr & PSYCHO_CEAFSR_SPIO) { | |
257 | reported++; | |
258 | printk("(PIO)"); | |
259 | } | |
260 | if (afsr & PSYCHO_CEAFSR_SDRD) { | |
261 | reported++; | |
262 | printk("(DMA Read)"); | |
263 | } | |
264 | if (afsr & PSYCHO_CEAFSR_SDWR) { | |
265 | reported++; | |
266 | printk("(DMA Write)"); | |
267 | } | |
268 | if (!reported) | |
269 | printk("(none)"); | |
270 | printk("]\n"); | |
271 | ||
272 | return IRQ_HANDLED; | |
273 | } | |
274 | ||
275 | /* PCI Errors. They are signalled by the PCI bus module since they | |
276 | * are associated with a specific bus segment. | |
277 | */ | |
278 | #define PSYCHO_PCI_AFSR_A 0x2010UL | |
279 | #define PSYCHO_PCI_AFSR_B 0x4010UL | |
1da177e4 LT |
280 | #define PSYCHO_PCI_AFAR_A 0x2018UL |
281 | #define PSYCHO_PCI_AFAR_B 0x4018UL | |
282 | ||
1da177e4 LT |
283 | /* XXX What about PowerFail/PowerManagement??? -DaveM */ |
284 | #define PSYCHO_ECC_CTRL 0x0020 | |
285 | #define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */ | |
286 | #define PSYCHO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */ | |
287 | #define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */ | |
34768bc8 | 288 | static void psycho_register_error_handlers(struct pci_pbm_info *pbm) |
1da177e4 | 289 | { |
cd4cd730 | 290 | struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node); |
34768bc8 | 291 | unsigned long base = pbm->controller_regs; |
1da177e4 | 292 | u64 tmp; |
af80318e | 293 | int err; |
1da177e4 | 294 | |
2b1e5978 DM |
295 | if (!op) |
296 | return; | |
1da177e4 | 297 | |
2b1e5978 | 298 | /* Psycho interrupt property order is: |
34768bc8 | 299 | * 0: PCIERR INO for this PBM |
2b1e5978 DM |
300 | * 1: UE ERR |
301 | * 2: CE ERR | |
302 | * 3: POWER FAIL | |
303 | * 4: SPARE HARDWARE | |
34768bc8 | 304 | * 5: POWER MANAGEMENT |
2b1e5978 | 305 | */ |
1da177e4 | 306 | |
1636f8ac | 307 | if (op->archdata.num_irqs < 6) |
2b1e5978 | 308 | return; |
1da177e4 | 309 | |
af80318e DM |
310 | /* We really mean to ignore the return result here. Two |
311 | * PCI controller share the same interrupt numbers and | |
a0381a94 | 312 | * drive the same front-end hardware. |
af80318e | 313 | */ |
1636f8ac | 314 | err = request_irq(op->archdata.irqs[1], psycho_ue_intr, IRQF_SHARED, |
af80318e | 315 | "PSYCHO_UE", pbm); |
1636f8ac | 316 | err = request_irq(op->archdata.irqs[2], psycho_ce_intr, IRQF_SHARED, |
af80318e DM |
317 | "PSYCHO_CE", pbm); |
318 | ||
319 | /* This one, however, ought not to fail. We can just warn | |
320 | * about it since the system can still operate properly even | |
321 | * if this fails. | |
322 | */ | |
1636f8ac | 323 | err = request_irq(op->archdata.irqs[0], psycho_pcierr_intr, IRQF_SHARED, |
af80318e DM |
324 | "PSYCHO_PCIERR", pbm); |
325 | if (err) | |
326 | printk(KERN_WARNING "%s: Could not register PCIERR, " | |
327 | "err=%d\n", pbm->name, err); | |
1da177e4 LT |
328 | |
329 | /* Enable UE and CE interrupts for controller. */ | |
87395fc6 DM |
330 | upa_writeq((PSYCHO_ECCCTRL_EE | |
331 | PSYCHO_ECCCTRL_UE | | |
332 | PSYCHO_ECCCTRL_CE), base + PSYCHO_ECC_CTRL); | |
1da177e4 LT |
333 | |
334 | /* Enable PCI Error interrupts and clear error | |
335 | * bits for each PBM. | |
336 | */ | |
87395fc6 | 337 | tmp = upa_readq(base + PSYCHO_PCIA_CTRL); |
1da177e4 LT |
338 | tmp |= (PSYCHO_PCICTRL_SERR | |
339 | PSYCHO_PCICTRL_SBH_ERR | | |
340 | PSYCHO_PCICTRL_EEN); | |
341 | tmp &= ~(PSYCHO_PCICTRL_SBH_INT); | |
87395fc6 | 342 | upa_writeq(tmp, base + PSYCHO_PCIA_CTRL); |
1da177e4 | 343 | |
87395fc6 | 344 | tmp = upa_readq(base + PSYCHO_PCIB_CTRL); |
1da177e4 LT |
345 | tmp |= (PSYCHO_PCICTRL_SERR | |
346 | PSYCHO_PCICTRL_SBH_ERR | | |
347 | PSYCHO_PCICTRL_EEN); | |
348 | tmp &= ~(PSYCHO_PCICTRL_SBH_INT); | |
87395fc6 | 349 | upa_writeq(tmp, base + PSYCHO_PCIB_CTRL); |
1da177e4 LT |
350 | } |
351 | ||
352 | /* PSYCHO boot time probing and initialization. */ | |
085ae41f | 353 | static void pbm_config_busmastering(struct pci_pbm_info *pbm) |
1da177e4 LT |
354 | { |
355 | u8 *addr; | |
356 | ||
357 | /* Set cache-line size to 64 bytes, this is actually | |
358 | * a nop but I do it for completeness. | |
359 | */ | |
360 | addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno, | |
361 | 0, PCI_CACHE_LINE_SIZE); | |
362 | pci_config_write8(addr, 64 / sizeof(u32)); | |
363 | ||
364 | /* Set PBM latency timer to 64 PCI clocks. */ | |
365 | addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno, | |
366 | 0, PCI_LATENCY_TIMER); | |
367 | pci_config_write8(addr, 64); | |
368 | } | |
369 | ||
b7c13f76 SR |
370 | static void psycho_scan_bus(struct pci_pbm_info *pbm, |
371 | struct device *parent) | |
1da177e4 | 372 | { |
34768bc8 DM |
373 | pbm_config_busmastering(pbm); |
374 | pbm->is_66mhz_capable = 0; | |
e822358a | 375 | pbm->pci_bus = pci_scan_one_pbm(pbm, parent); |
1da177e4 LT |
376 | |
377 | /* After the PCI bus scan is complete, we can register | |
378 | * the error interrupt handlers. | |
379 | */ | |
34768bc8 | 380 | psycho_register_error_handlers(pbm); |
1da177e4 LT |
381 | } |
382 | ||
1da177e4 LT |
383 | #define PSYCHO_IRQ_RETRY 0x1a00UL |
384 | #define PSYCHO_PCIA_DIAG 0x2020UL | |
385 | #define PSYCHO_PCIB_DIAG 0x4020UL | |
386 | #define PSYCHO_PCIDIAG_RESV 0xffffffffffffff80UL /* Reserved */ | |
387 | #define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040UL /* Disable retry limit */ | |
388 | #define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020UL /* Disable DMA wr / irq sync */ | |
389 | #define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010UL /* Disable DMA wr / PIO rd sync */ | |
390 | #define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008UL /* Invert DMA data parity */ | |
391 | #define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO data parity */ | |
392 | #define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002UL /* Invert PIO address parity */ | |
393 | #define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001UL /* Enable loopback mode */ | |
394 | ||
28113a99 | 395 | static void psycho_controller_hwinit(struct pci_pbm_info *pbm) |
1da177e4 LT |
396 | { |
397 | u64 tmp; | |
398 | ||
87395fc6 | 399 | upa_writeq(5, pbm->controller_regs + PSYCHO_IRQ_RETRY); |
1da177e4 LT |
400 | |
401 | /* Enable arbiter for all PCI slots. */ | |
87395fc6 | 402 | tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIA_CTRL); |
1da177e4 | 403 | tmp |= PSYCHO_PCICTRL_AEN; |
87395fc6 | 404 | upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIA_CTRL); |
1da177e4 | 405 | |
87395fc6 | 406 | tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIB_CTRL); |
1da177e4 | 407 | tmp |= PSYCHO_PCICTRL_AEN; |
87395fc6 | 408 | upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIB_CTRL); |
1da177e4 LT |
409 | |
410 | /* Disable DMA write / PIO read synchronization on | |
411 | * both PCI bus segments. | |
412 | * [ U2P Erratum 1243770, STP2223BGA data sheet ] | |
413 | */ | |
87395fc6 | 414 | tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIA_DIAG); |
1da177e4 | 415 | tmp |= PSYCHO_PCIDIAG_DDWSYNC; |
87395fc6 | 416 | upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIA_DIAG); |
1da177e4 | 417 | |
87395fc6 | 418 | tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIB_DIAG); |
1da177e4 | 419 | tmp |= PSYCHO_PCIDIAG_DDWSYNC; |
87395fc6 | 420 | upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIB_DIAG); |
1da177e4 LT |
421 | } |
422 | ||
28113a99 | 423 | static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm, |
1da177e4 LT |
424 | int is_pbm_a) |
425 | { | |
426 | unsigned long base = pbm->controller_regs; | |
427 | u64 control; | |
428 | ||
429 | if (is_pbm_a) { | |
430 | pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A; | |
431 | pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A; | |
432 | pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A; | |
d3ae4b5b DM |
433 | pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_A; |
434 | pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_A; | |
435 | pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_A; | |
1da177e4 LT |
436 | } else { |
437 | pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B; | |
438 | pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B; | |
439 | pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B; | |
d3ae4b5b DM |
440 | pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_B; |
441 | pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_B; | |
442 | pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_B; | |
1da177e4 LT |
443 | } |
444 | /* PSYCHO's streaming buffer lacks ctx flushing. */ | |
445 | pbm->stc.strbuf_ctxflush = 0; | |
446 | pbm->stc.strbuf_ctxmatch_base = 0; | |
447 | ||
448 | pbm->stc.strbuf_flushflag = (volatile unsigned long *) | |
449 | ((((unsigned long)&pbm->stc.__flushflag_buf[0]) | |
450 | + 63UL) | |
451 | & ~63UL); | |
452 | pbm->stc.strbuf_flushflag_pa = (unsigned long) | |
453 | __pa(pbm->stc.strbuf_flushflag); | |
454 | ||
455 | /* Enable the streaming buffer. We have to be careful | |
456 | * just in case OBP left it with LRU locking enabled. | |
457 | * | |
458 | * It is possible to control if PBM will be rerun on | |
459 | * line misses. Currently I just retain whatever setting | |
460 | * OBP left us with. All checks so far show it having | |
461 | * a value of zero. | |
462 | */ | |
463 | #undef PSYCHO_STRBUF_RERUN_ENABLE | |
464 | #undef PSYCHO_STRBUF_RERUN_DISABLE | |
87395fc6 | 465 | control = upa_readq(pbm->stc.strbuf_control); |
1da177e4 LT |
466 | control |= PSYCHO_STRBUF_CTRL_ENAB; |
467 | control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR); | |
468 | #ifdef PSYCHO_STRBUF_RERUN_ENABLE | |
469 | control &= ~(PSYCHO_STRBUF_CTRL_RRDIS); | |
470 | #else | |
471 | #ifdef PSYCHO_STRBUF_RERUN_DISABLE | |
472 | control |= PSYCHO_STRBUF_CTRL_RRDIS; | |
473 | #endif | |
474 | #endif | |
87395fc6 | 475 | upa_writeq(control, pbm->stc.strbuf_control); |
1da177e4 LT |
476 | |
477 | pbm->stc.strbuf_enabled = 1; | |
478 | } | |
479 | ||
480 | #define PSYCHO_IOSPACE_A 0x002000000UL | |
481 | #define PSYCHO_IOSPACE_B 0x002010000UL | |
482 | #define PSYCHO_IOSPACE_SIZE 0x00000ffffUL | |
483 | #define PSYCHO_MEMSPACE_A 0x100000000UL | |
484 | #define PSYCHO_MEMSPACE_B 0x180000000UL | |
485 | #define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL | |
486 | ||
b7c13f76 SR |
487 | static void psycho_pbm_init(struct pci_pbm_info *pbm, |
488 | struct platform_device *op, int is_pbm_a) | |
1da177e4 | 489 | { |
1c03a55c | 490 | psycho_pbm_init_common(pbm, op, "PSYCHO", PBM_CHIP_TYPE_PSYCHO); |
28113a99 | 491 | psycho_pbm_strbuf_init(pbm, is_pbm_a); |
e822358a | 492 | psycho_scan_bus(pbm, &op->dev); |
1da177e4 LT |
493 | } |
494 | ||
b7c13f76 | 495 | static struct pci_pbm_info *psycho_find_sibling(u32 upa_portid) |
d3ae4b5b DM |
496 | { |
497 | struct pci_pbm_info *pbm; | |
498 | ||
499 | for (pbm = pci_pbm_root; pbm; pbm = pbm->next) { | |
500 | if (pbm->portid == upa_portid) | |
501 | return pbm; | |
502 | } | |
503 | return NULL; | |
504 | } | |
505 | ||
1da177e4 LT |
506 | #define PSYCHO_CONFIGSPACE 0x001000000UL |
507 | ||
b7c13f76 | 508 | static int psycho_probe(struct platform_device *op) |
1da177e4 | 509 | { |
b20bfe41 | 510 | const struct linux_prom64_registers *pr_regs; |
61c7a080 | 511 | struct device_node *dp = op->dev.of_node; |
34768bc8 | 512 | struct pci_pbm_info *pbm; |
16ce82d8 | 513 | struct iommu *iommu; |
b20bfe41 | 514 | int is_pbm_a, err; |
1da177e4 | 515 | u32 upa_portid; |
1da177e4 | 516 | |
0f73d1bb | 517 | upa_portid = of_getintprop_default(dp, "upa-portid", 0xff); |
1da177e4 | 518 | |
b20bfe41 | 519 | err = -ENOMEM; |
d3ae4b5b DM |
520 | pbm = kzalloc(sizeof(*pbm), GFP_KERNEL); |
521 | if (!pbm) { | |
522 | printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n"); | |
d7472c38 | 523 | goto out_err; |
b20bfe41 DM |
524 | } |
525 | ||
d3ae4b5b DM |
526 | pbm->sibling = psycho_find_sibling(upa_portid); |
527 | if (pbm->sibling) { | |
528 | iommu = pbm->sibling->iommu; | |
529 | } else { | |
530 | iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL); | |
531 | if (!iommu) { | |
532 | printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n"); | |
533 | goto out_free_controller; | |
534 | } | |
b20bfe41 | 535 | } |
ad7ad57c | 536 | |
d3ae4b5b DM |
537 | pbm->iommu = iommu; |
538 | pbm->portid = upa_portid; | |
1da177e4 | 539 | |
b20bfe41 DM |
540 | pr_regs = of_get_property(dp, "reg", NULL); |
541 | err = -ENODEV; | |
542 | if (!pr_regs) { | |
543 | printk(KERN_ERR PFX "No reg property.\n"); | |
d7472c38 | 544 | goto out_free_iommu; |
b20bfe41 | 545 | } |
1da177e4 | 546 | |
d3ae4b5b DM |
547 | is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000); |
548 | ||
549 | pbm->controller_regs = pr_regs[2].phys_addr; | |
550 | pbm->config_space = (pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE); | |
1da177e4 | 551 | |
d3ae4b5b DM |
552 | if (is_pbm_a) { |
553 | pbm->pci_afsr = pbm->controller_regs + PSYCHO_PCI_AFSR_A; | |
554 | pbm->pci_afar = pbm->controller_regs + PSYCHO_PCI_AFAR_A; | |
555 | pbm->pci_csr = pbm->controller_regs + PSYCHO_PCIA_CTRL; | |
556 | } else { | |
557 | pbm->pci_afsr = pbm->controller_regs + PSYCHO_PCI_AFSR_B; | |
558 | pbm->pci_afar = pbm->controller_regs + PSYCHO_PCI_AFAR_B; | |
559 | pbm->pci_csr = pbm->controller_regs + PSYCHO_PCIB_CTRL; | |
560 | } | |
1da177e4 | 561 | |
d3ae4b5b DM |
562 | psycho_controller_hwinit(pbm); |
563 | if (!pbm->sibling) { | |
a21cff3e DM |
564 | err = psycho_iommu_init(pbm, 128, 0xc0000000, |
565 | 0xffffffff, PSYCHO_CONTROL); | |
d3ae4b5b DM |
566 | if (err) |
567 | goto out_free_iommu; | |
a21cff3e DM |
568 | |
569 | /* If necessary, hook us up for starfire IRQ translations. */ | |
570 | if (this_is_starfire) | |
571 | starfire_hookup(pbm->portid); | |
d3ae4b5b | 572 | } |
1da177e4 | 573 | |
d3ae4b5b | 574 | psycho_pbm_init(pbm, op, is_pbm_a); |
1da177e4 | 575 | |
1c03a55c DM |
576 | pbm->next = pci_pbm_root; |
577 | pci_pbm_root = pbm; | |
578 | ||
d3ae4b5b DM |
579 | if (pbm->sibling) |
580 | pbm->sibling->sibling = pbm; | |
b20bfe41 | 581 | |
d3ae4b5b | 582 | dev_set_drvdata(&op->dev, pbm); |
ad7ad57c | 583 | |
b20bfe41 DM |
584 | return 0; |
585 | ||
d7472c38 | 586 | out_free_iommu: |
d3ae4b5b DM |
587 | if (!pbm->sibling) |
588 | kfree(pbm->iommu); | |
d7472c38 DM |
589 | |
590 | out_free_controller: | |
d3ae4b5b | 591 | kfree(pbm); |
d7472c38 DM |
592 | |
593 | out_err: | |
b20bfe41 DM |
594 | return err; |
595 | } | |
596 | ||
3628aa06 | 597 | static const struct of_device_id psycho_match[] = { |
b20bfe41 DM |
598 | { |
599 | .name = "pci", | |
600 | .compatible = "pci108e,8000", | |
601 | }, | |
602 | {}, | |
603 | }; | |
604 | ||
4ebb24f7 | 605 | static struct platform_driver psycho_driver = { |
4018294b GL |
606 | .driver = { |
607 | .name = DRIVER_NAME, | |
4018294b GL |
608 | .of_match_table = psycho_match, |
609 | }, | |
b20bfe41 DM |
610 | .probe = psycho_probe, |
611 | }; | |
612 | ||
613 | static int __init psycho_init(void) | |
614 | { | |
4ebb24f7 | 615 | return platform_driver_register(&psycho_driver); |
1da177e4 | 616 | } |
b20bfe41 DM |
617 | |
618 | subsys_initcall(psycho_init); |