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Merge tag 'armsoc-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/arm...
[linux-2.6-block.git] / arch / sparc / kernel / pci_psycho.c
CommitLineData
9fd8b647 1/* pci_psycho.c: PSYCHO/U2P specific PCI controller support.
1da177e4 2 *
9fd8b647 3 * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
1da177e4
LT		 4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
6 */
7
8#include <linux/kernel.h>
9#include <linux/types.h>
10#include <linux/pci.h>
11#include <linux/init.h>
7b64db60 12#include <linux/export.h>
1da177e4
LT		 13#include <linux/slab.h>
14#include <linux/interrupt.h>
764f2579 15#include <linux/of_device.h>
1da177e4 16
1da177e4
LT		 17#include <asm/iommu.h>
18#include <asm/irq.h>
19#include <asm/starfire.h>
e87dc350 20#include <asm/prom.h>
87395fc6 21#include <asm/upa.h>
1da177e4
LT		 22
23#include "pci_impl.h"
24#include "iommu_common.h"
a21cff3e 25#include "psycho_common.h"
1da177e4 26
b20bfe41
DM		 27#define DRIVER_NAME "psycho"
28#define PFX DRIVER_NAME ": "
29
1da177e4
LT		 30/* Misc. PSYCHO PCI controller register offsets and definitions. */
31#define PSYCHO_CONTROL 0x0010UL
32#define PSYCHO_CONTROL_IMPL 0xf000000000000000UL /* Implementation of this PSYCHO*/
33#define PSYCHO_CONTROL_VER 0x0f00000000000000UL /* Version of this PSYCHO */
34#define PSYCHO_CONTROL_MID 0x00f8000000000000UL /* UPA Module ID of PSYCHO */
35#define PSYCHO_CONTROL_IGN 0x0007c00000000000UL /* Interrupt Group Number */
36#define PSYCHO_CONTROL_RESV 0x00003ffffffffff0UL /* Reserved */
37#define PSYCHO_CONTROL_APCKEN 0x0000000000000008UL /* Address Parity Check Enable */
38#define PSYCHO_CONTROL_APERR 0x0000000000000004UL /* Incoming System Addr Parerr */
39#define PSYCHO_CONTROL_IAP 0x0000000000000002UL /* Invert UPA Parity */
40#define PSYCHO_CONTROL_MODE 0x0000000000000001UL /* PSYCHO clock mode */
41#define PSYCHO_PCIA_CTRL 0x2000UL
42#define PSYCHO_PCIB_CTRL 0x4000UL
43#define PSYCHO_PCICTRL_RESV1 0xfffffff000000000UL /* Reserved */
44#define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL /* Streaming byte hole error */
45#define PSYCHO_PCICTRL_SERR 0x0000000400000000UL /* SERR signal asserted */
46#define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */
47#define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000UL /* Reserved */
48#define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */
49#define PSYCHO_PCICTRL_RESV3 0x00000000001ff800UL /* Reserved */
50#define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400UL /* Streaming byte hole int enab */
51#define PSYCHO_PCICTRL_WEN 0x0000000000000200UL /* Power Mgmt Wake Enable */
52#define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */
53#define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */
54#define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */
55
1da177e4 56/* PSYCHO error handling support. */
1da177e4
LT		 57
58/* Helper function of IOMMU error checking, which checks out
59 * the state of the streaming buffers. The IOMMU lock is
60 * held when this is called.
61 *
62 * For the PCI error case we know which PBM (and thus which
63 * streaming buffer) caused the error, but for the uncorrectable
64 * error case we do not. So we always check both streaming caches.
65 */
66#define PSYCHO_STRBUF_CONTROL_A 0x2800UL
67#define PSYCHO_STRBUF_CONTROL_B 0x4800UL
68#define PSYCHO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
69#define PSYCHO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
70#define PSYCHO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
71#define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
72#define PSYCHO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
73#define PSYCHO_STRBUF_FLUSH_A 0x2808UL
74#define PSYCHO_STRBUF_FLUSH_B 0x4808UL
75#define PSYCHO_STRBUF_FSYNC_A 0x2810UL
76#define PSYCHO_STRBUF_FSYNC_B 0x4810UL
77#define PSYCHO_STC_DATA_A 0xb000UL
78#define PSYCHO_STC_DATA_B 0xc000UL
79#define PSYCHO_STC_ERR_A 0xb400UL
80#define PSYCHO_STC_ERR_B 0xc400UL
1da177e4
LT		 81#define PSYCHO_STC_TAG_A 0xb800UL
82#define PSYCHO_STC_TAG_B 0xc800UL
1da177e4
LT		 83#define PSYCHO_STC_LINE_A 0xb900UL
84#define PSYCHO_STC_LINE_B 0xc900UL
1da177e4 85
1da177e4
LT		 86/* When an Uncorrectable Error or a PCI Error happens, we
87 * interrogate the IOMMU state to see if it is the cause.
88 */
89#define PSYCHO_IOMMU_CONTROL 0x0200UL
90#define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
91#define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
92#define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
93#define PSYCHO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
94#define PSYCHO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
95#define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
96#define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
97#define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
98#define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
99#define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
100#define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
101#define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
102#define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
103#define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
104#define PSYCHO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
105#define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
106#define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
107#define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
108#define PSYCHO_IOMMU_TSBBASE 0x0208UL
109#define PSYCHO_IOMMU_FLUSH 0x0210UL
110#define PSYCHO_IOMMU_TAG 0xa580UL
1da177e4 111#define PSYCHO_IOMMU_DATA 0xa600UL
1da177e4
LT		 112
113/* Uncorrectable Errors. Cause of the error and the address are
114 * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors
115 * relating to UPA interface transactions.
116 */
117#define PSYCHO_UE_AFSR 0x0030UL
118#define PSYCHO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
119#define PSYCHO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
120#define PSYCHO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
121#define PSYCHO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
122#define PSYCHO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
123#define PSYCHO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
124#define PSYCHO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */
125#define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
126#define PSYCHO_UEAFSR_DOFF 0x00000000e0000000UL /* Doubleword Offset */
127#define PSYCHO_UEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
128#define PSYCHO_UEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
129#define PSYCHO_UEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
130#define PSYCHO_UE_AFAR 0x0038UL
131
6d24c8dc 132static irqreturn_t psycho_ue_intr(int irq, void *dev_id)
1da177e4 133{
34768bc8 134 struct pci_pbm_info *pbm = dev_id;
34768bc8
DM		 135 unsigned long afsr_reg = pbm->controller_regs + PSYCHO_UE_AFSR;
136 unsigned long afar_reg = pbm->controller_regs + PSYCHO_UE_AFAR;
1da177e4
LT		 137 unsigned long afsr, afar, error_bits;
138 int reported;
139
140 /* Latch uncorrectable error status. */
87395fc6
DM		 141 afar = upa_readq(afar_reg);
142 afsr = upa_readq(afsr_reg);
1da177e4
LT		 143
144 /* Clear the primary/secondary error status bits. */
145 error_bits = afsr &
146 (PSYCHO_UEAFSR_PPIO | PSYCHO_UEAFSR_PDRD | PSYCHO_UEAFSR_PDWR |
147 PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR);
148 if (!error_bits)
149 return IRQ_NONE;
87395fc6 150 upa_writeq(error_bits, afsr_reg);
1da177e4
LT		 151
152 /* Log the error. */
6c108f12
DM		 153 printk("%s: Uncorrectable Error, primary error type[%s]\n",
154 pbm->name,
1da177e4
LT		 155 (((error_bits & PSYCHO_UEAFSR_PPIO) ?
156 "PIO" :
157 ((error_bits & PSYCHO_UEAFSR_PDRD) ?
158 "DMA Read" :
159 ((error_bits & PSYCHO_UEAFSR_PDWR) ?
160 "DMA Write" : "???")))));
6c108f12
DM		 161 printk("%s: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n",
162 pbm->name,
1da177e4
LT		 163 (afsr & PSYCHO_UEAFSR_BMSK) >> 32UL,
164 (afsr & PSYCHO_UEAFSR_DOFF) >> 29UL,
165 (afsr & PSYCHO_UEAFSR_MID) >> 24UL,
166 ((afsr & PSYCHO_UEAFSR_BLK) ? 1 : 0));
6c108f12
DM		 167 printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
168 printk("%s: UE Secondary errors [", pbm->name);
1da177e4
LT		 169 reported = 0;
170 if (afsr & PSYCHO_UEAFSR_SPIO) {
171 reported++;
172 printk("(PIO)");
173 }
174 if (afsr & PSYCHO_UEAFSR_SDRD) {
175 reported++;
176 printk("(DMA Read)");
177 }
178 if (afsr & PSYCHO_UEAFSR_SDWR) {
179 reported++;
180 printk("(DMA Write)");
181 }
182 if (!reported)
183 printk("(none)");
184 printk("]\n");
185
34768bc8 186 /* Interrogate both IOMMUs for error status. */
d3ae4b5b
DM		 187 psycho_check_iommu_error(pbm, afsr, afar, UE_ERR);
188 if (pbm->sibling)
189 psycho_check_iommu_error(pbm->sibling, afsr, afar, UE_ERR);
1da177e4
LT		 190
191 return IRQ_HANDLED;
192}
193
194/* Correctable Errors. */
195#define PSYCHO_CE_AFSR 0x0040UL
196#define PSYCHO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
197#define PSYCHO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
198#define PSYCHO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
199#define PSYCHO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
200#define PSYCHO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
201#define PSYCHO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
202#define PSYCHO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */
203#define PSYCHO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */
204#define PSYCHO_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
205#define PSYCHO_CEAFSR_DOFF 0x00000000e0000000UL /* Double Offset */
206#define PSYCHO_CEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
207#define PSYCHO_CEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
208#define PSYCHO_CEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
209#define PSYCHO_CE_AFAR 0x0040UL
210
6d24c8dc 211static irqreturn_t psycho_ce_intr(int irq, void *dev_id)
1da177e4 212{
34768bc8 213 struct pci_pbm_info *pbm = dev_id;
34768bc8
DM		 214 unsigned long afsr_reg = pbm->controller_regs + PSYCHO_CE_AFSR;
215 unsigned long afar_reg = pbm->controller_regs + PSYCHO_CE_AFAR;
1da177e4
LT		 216 unsigned long afsr, afar, error_bits;
217 int reported;
218
219 /* Latch error status. */
87395fc6
DM		 220 afar = upa_readq(afar_reg);
221 afsr = upa_readq(afsr_reg);
1da177e4
LT		 222
223 /* Clear primary/secondary error status bits. */
224 error_bits = afsr &
225 (PSYCHO_CEAFSR_PPIO | PSYCHO_CEAFSR_PDRD | PSYCHO_CEAFSR_PDWR |
226 PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR);
227 if (!error_bits)
228 return IRQ_NONE;
87395fc6 229 upa_writeq(error_bits, afsr_reg);
1da177e4
LT		 230
231 /* Log the error. */
6c108f12
DM		 232 printk("%s: Correctable Error, primary error type[%s]\n",
233 pbm->name,
1da177e4
LT		 234 (((error_bits & PSYCHO_CEAFSR_PPIO) ?
235 "PIO" :
236 ((error_bits & PSYCHO_CEAFSR_PDRD) ?
237 "DMA Read" :
238 ((error_bits & PSYCHO_CEAFSR_PDWR) ?
239 "DMA Write" : "???")))));
240
241 /* XXX Use syndrome and afar to print out module string just like
242 * XXX UDB CE trap handler does... -DaveM
243 */
6c108f12 244 printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
1da177e4 245 "UPA_MID[%02lx] was_block(%d)\n",
6c108f12 246 pbm->name,
1da177e4
LT		 247 (afsr & PSYCHO_CEAFSR_ESYND) >> 48UL,
248 (afsr & PSYCHO_CEAFSR_BMSK) >> 32UL,
249 (afsr & PSYCHO_CEAFSR_DOFF) >> 29UL,
250 (afsr & PSYCHO_CEAFSR_MID) >> 24UL,
251 ((afsr & PSYCHO_CEAFSR_BLK) ? 1 : 0));
6c108f12
DM		 252 printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
253 printk("%s: CE Secondary errors [", pbm->name);
1da177e4
LT		 254 reported = 0;
255 if (afsr & PSYCHO_CEAFSR_SPIO) {
256 reported++;
257 printk("(PIO)");
258 }
259 if (afsr & PSYCHO_CEAFSR_SDRD) {
260 reported++;
261 printk("(DMA Read)");
262 }
263 if (afsr & PSYCHO_CEAFSR_SDWR) {
264 reported++;
265 printk("(DMA Write)");
266 }
267 if (!reported)
268 printk("(none)");
269 printk("]\n");
270
271 return IRQ_HANDLED;
272}
273
274/* PCI Errors. They are signalled by the PCI bus module since they
275 * are associated with a specific bus segment.
276 */
277#define PSYCHO_PCI_AFSR_A 0x2010UL
278#define PSYCHO_PCI_AFSR_B 0x4010UL
1da177e4
LT		 279#define PSYCHO_PCI_AFAR_A 0x2018UL
280#define PSYCHO_PCI_AFAR_B 0x4018UL
281
1da177e4
LT		 282/* XXX What about PowerFail/PowerManagement??? -DaveM */
283#define PSYCHO_ECC_CTRL 0x0020
284#define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
285#define PSYCHO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
286#define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
34768bc8 287static void psycho_register_error_handlers(struct pci_pbm_info *pbm)
1da177e4 288{
cd4cd730 289 struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node);
34768bc8 290 unsigned long base = pbm->controller_regs;
1da177e4 291 u64 tmp;
af80318e 292 int err;
1da177e4 293
2b1e5978
DM		 294 if (!op)
295 return;
1da177e4 296
2b1e5978 297 /* Psycho interrupt property order is:
34768bc8 298 * 0: PCIERR INO for this PBM
2b1e5978
DM		 299 * 1: UE ERR
300 * 2: CE ERR
301 * 3: POWER FAIL
302 * 4: SPARE HARDWARE
34768bc8 303 * 5: POWER MANAGEMENT
2b1e5978 304 */
1da177e4 305
1636f8ac 306 if (op->archdata.num_irqs < 6)
2b1e5978 307 return;
1da177e4 308
af80318e
DM		 309 /* We really mean to ignore the return result here. Two
310 * PCI controller share the same interrupt numbers and
a0381a94 311 * drive the same front-end hardware.
af80318e 312 */
1636f8ac 313 err = request_irq(op->archdata.irqs[1], psycho_ue_intr, IRQF_SHARED,
af80318e 314 "PSYCHO_UE", pbm);
1636f8ac 315 err = request_irq(op->archdata.irqs[2], psycho_ce_intr, IRQF_SHARED,
af80318e
DM		 316 "PSYCHO_CE", pbm);
317
318 /* This one, however, ought not to fail. We can just warn
319 * about it since the system can still operate properly even
320 * if this fails.
321 */
1636f8ac 322 err = request_irq(op->archdata.irqs[0], psycho_pcierr_intr, IRQF_SHARED,
af80318e
DM		 323 "PSYCHO_PCIERR", pbm);
324 if (err)
325 printk(KERN_WARNING "%s: Could not register PCIERR, "
326 "err=%d\n", pbm->name, err);
1da177e4
LT		 327
328 /* Enable UE and CE interrupts for controller. */
87395fc6
DM		 329 upa_writeq((PSYCHO_ECCCTRL_EE |
330 PSYCHO_ECCCTRL_UE |
331 PSYCHO_ECCCTRL_CE), base + PSYCHO_ECC_CTRL);
1da177e4
LT		 332
333 /* Enable PCI Error interrupts and clear error
334 * bits for each PBM.
335 */
87395fc6 336 tmp = upa_readq(base + PSYCHO_PCIA_CTRL);
1da177e4
LT		 337 tmp |= (PSYCHO_PCICTRL_SERR |
338 PSYCHO_PCICTRL_SBH_ERR |
339 PSYCHO_PCICTRL_EEN);
340 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
87395fc6 341 upa_writeq(tmp, base + PSYCHO_PCIA_CTRL);
1da177e4 342
87395fc6 343 tmp = upa_readq(base + PSYCHO_PCIB_CTRL);
1da177e4
LT		 344 tmp |= (PSYCHO_PCICTRL_SERR |
345 PSYCHO_PCICTRL_SBH_ERR |
346 PSYCHO_PCICTRL_EEN);
347 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
87395fc6 348 upa_writeq(tmp, base + PSYCHO_PCIB_CTRL);
1da177e4
LT		 349}
350
351/* PSYCHO boot time probing and initialization. */
085ae41f 352static void pbm_config_busmastering(struct pci_pbm_info *pbm)
1da177e4
LT		 353{
354 u8 *addr;
355
356 /* Set cache-line size to 64 bytes, this is actually
357 * a nop but I do it for completeness.
358 */
359 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
360 0, PCI_CACHE_LINE_SIZE);
361 pci_config_write8(addr, 64 / sizeof(u32));
362
363 /* Set PBM latency timer to 64 PCI clocks. */
364 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
365 0, PCI_LATENCY_TIMER);
366 pci_config_write8(addr, 64);
367}
368
b7c13f76
SR		 369static void psycho_scan_bus(struct pci_pbm_info *pbm,
370 struct device *parent)
1da177e4 371{
34768bc8
DM		 372 pbm_config_busmastering(pbm);
373 pbm->is_66mhz_capable = 0;
e822358a 374 pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
1da177e4
LT		 375
376 /* After the PCI bus scan is complete, we can register
377 * the error interrupt handlers.
378 */
34768bc8 379 psycho_register_error_handlers(pbm);
1da177e4
LT		 380}
381
1da177e4
LT		 382#define PSYCHO_IRQ_RETRY 0x1a00UL
383#define PSYCHO_PCIA_DIAG 0x2020UL
384#define PSYCHO_PCIB_DIAG 0x4020UL
385#define PSYCHO_PCIDIAG_RESV 0xffffffffffffff80UL /* Reserved */
386#define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040UL /* Disable retry limit */
387#define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020UL /* Disable DMA wr / irq sync */
388#define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010UL /* Disable DMA wr / PIO rd sync */
389#define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008UL /* Invert DMA data parity */
390#define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO data parity */
391#define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002UL /* Invert PIO address parity */
392#define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001UL /* Enable loopback mode */
393
28113a99 394static void psycho_controller_hwinit(struct pci_pbm_info *pbm)
1da177e4
LT		 395{
396 u64 tmp;
397
87395fc6 398 upa_writeq(5, pbm->controller_regs + PSYCHO_IRQ_RETRY);
1da177e4
LT		 399
400 /* Enable arbiter for all PCI slots. */
87395fc6 401 tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIA_CTRL);
1da177e4 402 tmp |= PSYCHO_PCICTRL_AEN;
87395fc6 403 upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIA_CTRL);
1da177e4 404
87395fc6 405 tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIB_CTRL);
1da177e4 406 tmp |= PSYCHO_PCICTRL_AEN;
87395fc6 407 upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIB_CTRL);
1da177e4
LT		 408
409 /* Disable DMA write / PIO read synchronization on
410 * both PCI bus segments.
411 * [ U2P Erratum 1243770, STP2223BGA data sheet ]
412 */
87395fc6 413 tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIA_DIAG);
1da177e4 414 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
87395fc6 415 upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIA_DIAG);
1da177e4 416
87395fc6 417 tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIB_DIAG);
1da177e4 418 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
87395fc6 419 upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIB_DIAG);
1da177e4
LT		 420}
421
28113a99 422static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm,
1da177e4
LT		 423 int is_pbm_a)
424{
425 unsigned long base = pbm->controller_regs;
426 u64 control;
427
428 if (is_pbm_a) {
429 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A;
430 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A;
431 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A;
d3ae4b5b
DM		 432 pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_A;
433 pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_A;
434 pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_A;
1da177e4
LT		 435 } else {
436 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B;
437 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B;
438 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B;
d3ae4b5b
DM		 439 pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_B;
440 pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_B;
441 pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_B;
1da177e4
LT		 442 }
443 /* PSYCHO's streaming buffer lacks ctx flushing. */
444 pbm->stc.strbuf_ctxflush = 0;
445 pbm->stc.strbuf_ctxmatch_base = 0;
446
447 pbm->stc.strbuf_flushflag = (volatile unsigned long *)
448 ((((unsigned long)&pbm->stc.__flushflag_buf[0])
449 + 63UL)
450 & ~63UL);
451 pbm->stc.strbuf_flushflag_pa = (unsigned long)
452 __pa(pbm->stc.strbuf_flushflag);
453
454 /* Enable the streaming buffer. We have to be careful
455 * just in case OBP left it with LRU locking enabled.
456 *
457 * It is possible to control if PBM will be rerun on
458 * line misses. Currently I just retain whatever setting
459 * OBP left us with. All checks so far show it having
460 * a value of zero.
461 */
462#undef PSYCHO_STRBUF_RERUN_ENABLE
463#undef PSYCHO_STRBUF_RERUN_DISABLE
87395fc6 464 control = upa_readq(pbm->stc.strbuf_control);
1da177e4
LT		 465 control |= PSYCHO_STRBUF_CTRL_ENAB;
466 control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR);
467#ifdef PSYCHO_STRBUF_RERUN_ENABLE
468 control &= ~(PSYCHO_STRBUF_CTRL_RRDIS);
469#else
470#ifdef PSYCHO_STRBUF_RERUN_DISABLE
471 control |= PSYCHO_STRBUF_CTRL_RRDIS;
472#endif
473#endif
87395fc6 474 upa_writeq(control, pbm->stc.strbuf_control);
1da177e4
LT		 475
476 pbm->stc.strbuf_enabled = 1;
477}
478
479#define PSYCHO_IOSPACE_A 0x002000000UL
480#define PSYCHO_IOSPACE_B 0x002010000UL
481#define PSYCHO_IOSPACE_SIZE 0x00000ffffUL
482#define PSYCHO_MEMSPACE_A 0x100000000UL
483#define PSYCHO_MEMSPACE_B 0x180000000UL
484#define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL
485
b7c13f76
SR		 486static void psycho_pbm_init(struct pci_pbm_info *pbm,
487 struct platform_device *op, int is_pbm_a)
1da177e4 488{
1c03a55c 489 psycho_pbm_init_common(pbm, op, "PSYCHO", PBM_CHIP_TYPE_PSYCHO);
28113a99 490 psycho_pbm_strbuf_init(pbm, is_pbm_a);
e822358a 491 psycho_scan_bus(pbm, &op->dev);
1da177e4
LT		 492}
493
b7c13f76 494static struct pci_pbm_info *psycho_find_sibling(u32 upa_portid)
d3ae4b5b
DM		 495{
496 struct pci_pbm_info *pbm;
497
498 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
499 if (pbm->portid == upa_portid)
500 return pbm;
501 }
502 return NULL;
503}
504
1da177e4
LT		 505#define PSYCHO_CONFIGSPACE 0x001000000UL
506
b7c13f76 507static int psycho_probe(struct platform_device *op)
1da177e4 508{
b20bfe41 509 const struct linux_prom64_registers *pr_regs;
61c7a080 510 struct device_node *dp = op->dev.of_node;
34768bc8 511 struct pci_pbm_info *pbm;
16ce82d8 512 struct iommu *iommu;
b20bfe41 513 int is_pbm_a, err;
1da177e4 514 u32 upa_portid;
1da177e4 515
0f73d1bb 516 upa_portid = of_getintprop_default(dp, "upa-portid", 0xff);
1da177e4 517
b20bfe41 518 err = -ENOMEM;
d3ae4b5b
DM		 519 pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
520 if (!pbm) {
521 printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n");
d7472c38 522 goto out_err;
b20bfe41
DM		 523 }
524
d3ae4b5b
DM		 525 pbm->sibling = psycho_find_sibling(upa_portid);
526 if (pbm->sibling) {
527 iommu = pbm->sibling->iommu;
528 } else {
529 iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
530 if (!iommu) {
531 printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n");
532 goto out_free_controller;
533 }
b20bfe41 534 }
ad7ad57c 535
d3ae4b5b
DM		 536 pbm->iommu = iommu;
537 pbm->portid = upa_portid;
1da177e4 538
b20bfe41
DM		 539 pr_regs = of_get_property(dp, "reg", NULL);
540 err = -ENODEV;
541 if (!pr_regs) {
542 printk(KERN_ERR PFX "No reg property.\n");
d7472c38 543 goto out_free_iommu;
b20bfe41 544 }
1da177e4 545
d3ae4b5b
DM		 546 is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000);
547
548 pbm->controller_regs = pr_regs[2].phys_addr;
549 pbm->config_space = (pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE);
1da177e4 550
d3ae4b5b
DM		 551 if (is_pbm_a) {
552 pbm->pci_afsr = pbm->controller_regs + PSYCHO_PCI_AFSR_A;
553 pbm->pci_afar = pbm->controller_regs + PSYCHO_PCI_AFAR_A;
554 pbm->pci_csr = pbm->controller_regs + PSYCHO_PCIA_CTRL;
555 } else {
556 pbm->pci_afsr = pbm->controller_regs + PSYCHO_PCI_AFSR_B;
557 pbm->pci_afar = pbm->controller_regs + PSYCHO_PCI_AFAR_B;
558 pbm->pci_csr = pbm->controller_regs + PSYCHO_PCIB_CTRL;
559 }
1da177e4 560
d3ae4b5b
DM		 561 psycho_controller_hwinit(pbm);
562 if (!pbm->sibling) {
a21cff3e
DM		 563 err = psycho_iommu_init(pbm, 128, 0xc0000000,
564 0xffffffff, PSYCHO_CONTROL);
d3ae4b5b
DM		 565 if (err)
566 goto out_free_iommu;
a21cff3e
DM		 567
568 /* If necessary, hook us up for starfire IRQ translations. */
569 if (this_is_starfire)
570 starfire_hookup(pbm->portid);
d3ae4b5b 571 }
1da177e4 572
d3ae4b5b 573 psycho_pbm_init(pbm, op, is_pbm_a);
1da177e4 574
1c03a55c
DM		 575 pbm->next = pci_pbm_root;
576 pci_pbm_root = pbm;
577
d3ae4b5b
DM		 578 if (pbm->sibling)
579 pbm->sibling->sibling = pbm;
b20bfe41 580
d3ae4b5b 581 dev_set_drvdata(&op->dev, pbm);
ad7ad57c 582
b20bfe41
DM		 583 return 0;
584
d7472c38 585out_free_iommu:
d3ae4b5b
DM		 586 if (!pbm->sibling)
587 kfree(pbm->iommu);
d7472c38
DM		 588
589out_free_controller:
d3ae4b5b 590 kfree(pbm);
d7472c38
DM		 591
592out_err:
b20bfe41
DM		 593 return err;
594}
595
3628aa06 596static const struct of_device_id psycho_match[] = {
b20bfe41
DM		 597 {
598 .name = "pci",
599 .compatible = "pci108e,8000",
600 },
601 {},
602};
603
4ebb24f7 604static struct platform_driver psycho_driver = {
4018294b
GL		 605 .driver = {
606 .name = DRIVER_NAME,
4018294b
GL		 607 .of_match_table = psycho_match,
608 },
b20bfe41
DM		 609 .probe = psycho_probe,
610};
611
612static int __init psycho_init(void)
613{
4ebb24f7 614 return platform_driver_register(&psycho_driver);
1da177e4 615}
b20bfe41
DM		 616
617subsys_initcall(psycho_init);
Linux 6.x block layer and io_uring tree(s)