[linux-2.6-block.git] / arch / sparc / kernel / pci_msi.c

// SPDX-License-Identifier: GPL-2.0
/* pci_msi.c: Sparc64 MSI support common layer.
 *
 * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
 */
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/irq.h>

#include "pci_impl.h"

static irqreturn_t sparc64_msiq_interrupt(int irq, void *cookie)
{
	struct sparc64_msiq_cookie *msiq_cookie = cookie;
	struct pci_pbm_info *pbm = msiq_cookie->pbm;
	unsigned long msiqid = msiq_cookie->msiqid;
	const struct sparc64_msiq_ops *ops;
	unsigned long orig_head, head;
	int err;

	ops = pbm->msi_ops;

	err = ops->get_head(pbm, msiqid, &head);
	if (unlikely(err < 0))
		goto err_get_head;

	orig_head = head;
	for (;;) {
		unsigned long msi;

		err = ops->dequeue_msi(pbm, msiqid, &head, &msi);
		if (likely(err > 0)) {
			unsigned int irq;

			irq = pbm->msi_irq_table[msi - pbm->msi_first];
			generic_handle_irq(irq);
		}

		if (unlikely(err < 0))
			goto err_dequeue;

		if (err == 0)
			break;
	}
	if (likely(head != orig_head)) {
		err = ops->set_head(pbm, msiqid, head);
		if (unlikely(err < 0))
			goto err_set_head;
	}
	return IRQ_HANDLED;

err_get_head:
	printk(KERN_EMERG "MSI: Get head on msiqid[%lu] gives error %d\n",
	       msiqid, err);
	goto err_out;

err_dequeue:
	printk(KERN_EMERG "MSI: Dequeue head[%lu] from msiqid[%lu] "
	       "gives error %d\n",
	       head, msiqid, err);
	goto err_out;

err_set_head:
	printk(KERN_EMERG "MSI: Set head[%lu] on msiqid[%lu] "
	       "gives error %d\n",
	       head, msiqid, err);
	goto err_out;

err_out:
	return IRQ_NONE;
}

static u32 pick_msiq(struct pci_pbm_info *pbm)
{
	static DEFINE_SPINLOCK(rotor_lock);
	unsigned long flags;
	u32 ret, rotor;

	spin_lock_irqsave(&rotor_lock, flags);

	rotor = pbm->msiq_rotor;
	ret = pbm->msiq_first + rotor;

	if (++rotor >= pbm->msiq_num)
		rotor = 0;
	pbm->msiq_rotor = rotor;

	spin_unlock_irqrestore(&rotor_lock, flags);

	return ret;
}


static int alloc_msi(struct pci_pbm_info *pbm)
{
	int i;

	for (i = 0; i < pbm->msi_num; i++) {
		if (!test_and_set_bit(i, pbm->msi_bitmap))
			return i + pbm->msi_first;
	}

	return -ENOENT;
}

static void free_msi(struct pci_pbm_info *pbm, int msi_num)
{
	msi_num -= pbm->msi_first;
	clear_bit(msi_num, pbm->msi_bitmap);
}

static struct irq_chip msi_irq = {
	.name		= "PCI-MSI",
	.irq_mask	= pci_msi_mask_irq,
	.irq_unmask	= pci_msi_unmask_irq,
	.irq_enable	= pci_msi_unmask_irq,
	.irq_disable	= pci_msi_mask_irq,
	/* XXX affinity XXX */
};

static int sparc64_setup_msi_irq(unsigned int *irq_p,
				 struct pci_dev *pdev,
				 struct msi_desc *entry)
{
	struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
	const struct sparc64_msiq_ops *ops = pbm->msi_ops;
	struct msi_msg msg;
	int msi, err;
	u32 msiqid;

	*irq_p = irq_alloc(0, 0);
	err = -ENOMEM;
	if (!*irq_p)
		goto out_err;

	irq_set_chip_and_handler_name(*irq_p, &msi_irq, handle_simple_irq,
				      "MSI");

	err = alloc_msi(pbm);
	if (unlikely(err < 0))
		goto out_irq_free;

	msi = err;

	msiqid = pick_msiq(pbm);

	err = ops->msi_setup(pbm, msiqid, msi,
			     (entry->msi_attrib.is_64 ? 1 : 0));
	if (err)
		goto out_msi_free;

	pbm->msi_irq_table[msi - pbm->msi_first] = *irq_p;

	if (entry->msi_attrib.is_64) {
		msg.address_hi = pbm->msi64_start >> 32;
		msg.address_lo = pbm->msi64_start & 0xffffffff;
	} else {
		msg.address_hi = 0;
		msg.address_lo = pbm->msi32_start;
	}
	msg.data = msi;

	irq_set_msi_desc(*irq_p, entry);
	pci_write_msi_msg(*irq_p, &msg);

	return 0;

out_msi_free:
	free_msi(pbm, msi);

out_irq_free:
	irq_set_chip(*irq_p, NULL);
	irq_free(*irq_p);
	*irq_p = 0;

out_err:
	return err;
}

static void sparc64_teardown_msi_irq(unsigned int irq,
				     struct pci_dev *pdev)
{
	struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
	const struct sparc64_msiq_ops *ops = pbm->msi_ops;
	unsigned int msi_num;
	int i, err;

	for (i = 0; i < pbm->msi_num; i++) {
		if (pbm->msi_irq_table[i] == irq)
			break;
	}
	if (i >= pbm->msi_num) {
		printk(KERN_ERR "%s: teardown: No MSI for irq %u\n",
		       pbm->name, irq);
		return;
	}

	msi_num = pbm->msi_first + i;
	pbm->msi_irq_table[i] = ~0U;

	err = ops->msi_teardown(pbm, msi_num);
	if (err) {
		printk(KERN_ERR "%s: teardown: ops->teardown() on MSI %u, "
		       "irq %u, gives error %d\n",
		       pbm->name, msi_num, irq, err);
		return;
	}

	free_msi(pbm, msi_num);

	irq_set_chip(irq, NULL);
	irq_free(irq);
}

static int msi_bitmap_alloc(struct pci_pbm_info *pbm)
{
	unsigned long size, bits_per_ulong;

	bits_per_ulong = sizeof(unsigned long) * 8;
	size = (pbm->msi_num + (bits_per_ulong - 1)) & ~(bits_per_ulong - 1);
	size /= 8;
	BUG_ON(size % sizeof(unsigned long));

	pbm->msi_bitmap = kzalloc(size, GFP_KERNEL);
	if (!pbm->msi_bitmap)
		return -ENOMEM;

	return 0;
}

static void msi_bitmap_free(struct pci_pbm_info *pbm)
{
	kfree(pbm->msi_bitmap);
	pbm->msi_bitmap = NULL;
}

static int msi_table_alloc(struct pci_pbm_info *pbm)
{
	int size, i;

	size = pbm->msiq_num * sizeof(struct sparc64_msiq_cookie);
	pbm->msiq_irq_cookies = kzalloc(size, GFP_KERNEL);
	if (!pbm->msiq_irq_cookies)
		return -ENOMEM;

	for (i = 0; i < pbm->msiq_num; i++) {
		struct sparc64_msiq_cookie *p;

		p = &pbm->msiq_irq_cookies[i];
		p->pbm = pbm;
		p->msiqid = pbm->msiq_first + i;
	}

	size = pbm->msi_num * sizeof(unsigned int);
	pbm->msi_irq_table = kzalloc(size, GFP_KERNEL);
	if (!pbm->msi_irq_table) {
		kfree(pbm->msiq_irq_cookies);
		pbm->msiq_irq_cookies = NULL;
		return -ENOMEM;
	}

	return 0;
}

static void msi_table_free(struct pci_pbm_info *pbm)
{
	kfree(pbm->msiq_irq_cookies);
	pbm->msiq_irq_cookies = NULL;

	kfree(pbm->msi_irq_table);
	pbm->msi_irq_table = NULL;
}

static int bringup_one_msi_queue(struct pci_pbm_info *pbm,
				 const struct sparc64_msiq_ops *ops,
				 unsigned long msiqid,
				 unsigned long devino)
{
	int irq = ops->msiq_build_irq(pbm, msiqid, devino);
	int err, nid;

	if (irq < 0)
		return irq;

	nid = pbm->numa_node;
	if (nid != -1) {
		cpumask_t numa_mask;

		cpumask_copy(&numa_mask, cpumask_of_node(nid));
		irq_set_affinity(irq, &numa_mask);
	}
	err = request_irq(irq, sparc64_msiq_interrupt, 0,
			  "MSIQ",
			  &pbm->msiq_irq_cookies[msiqid - pbm->msiq_first]);
	if (err)
		return err;

	return 0;
}

static int sparc64_bringup_msi_queues(struct pci_pbm_info *pbm,
				      const struct sparc64_msiq_ops *ops)
{
	int i;

	for (i = 0; i < pbm->msiq_num; i++) {
		unsigned long msiqid = i + pbm->msiq_first;
		unsigned long devino = i + pbm->msiq_first_devino;
		int err;

		err = bringup_one_msi_queue(pbm, ops, msiqid, devino);
		if (err)
			return err;
	}

	return 0;
}

void sparc64_pbm_msi_init(struct pci_pbm_info *pbm,
			  const struct sparc64_msiq_ops *ops)
{
	const u32 *val;
	int len;

	val = of_get_property(pbm->op->dev.of_node, "#msi-eqs", &len);
	if (!val || len != 4)
		goto no_msi;
	pbm->msiq_num = *val;
	if (pbm->msiq_num) {
		const struct msiq_prop {
			u32 first_msiq;
			u32 num_msiq;
			u32 first_devino;
		} *mqp;
		const struct msi_range_prop {
			u32 first_msi;
			u32 num_msi;
		} *mrng;
		const struct addr_range_prop {
			u32 msi32_high;
			u32 msi32_low;
			u32 msi32_len;
			u32 msi64_high;
			u32 msi64_low;
			u32 msi64_len;
		} *arng;

		val = of_get_property(pbm->op->dev.of_node, "msi-eq-size", &len);
		if (!val || len != 4)
			goto no_msi;

		pbm->msiq_ent_count = *val;

		mqp = of_get_property(pbm->op->dev.of_node,
				      "msi-eq-to-devino", &len);
		if (!mqp)
			mqp = of_get_property(pbm->op->dev.of_node,
					      "msi-eq-devino", &len);
		if (!mqp || len != sizeof(struct msiq_prop))
			goto no_msi;

		pbm->msiq_first = mqp->first_msiq;
		pbm->msiq_first_devino = mqp->first_devino;

		val = of_get_property(pbm->op->dev.of_node, "#msi", &len);
		if (!val || len != 4)
			goto no_msi;
		pbm->msi_num = *val;

		mrng = of_get_property(pbm->op->dev.of_node, "msi-ranges", &len);
		if (!mrng || len != sizeof(struct msi_range_prop))
			goto no_msi;
		pbm->msi_first = mrng->first_msi;

		val = of_get_property(pbm->op->dev.of_node, "msi-data-mask", &len);
		if (!val || len != 4)
			goto no_msi;
		pbm->msi_data_mask = *val;

		val = of_get_property(pbm->op->dev.of_node, "msix-data-width", &len);
		if (!val || len != 4)
			goto no_msi;
		pbm->msix_data_width = *val;

		arng = of_get_property(pbm->op->dev.of_node, "msi-address-ranges",
				       &len);
		if (!arng || len != sizeof(struct addr_range_prop))
			goto no_msi;
		pbm->msi32_start = ((u64)arng->msi32_high << 32) |
			(u64) arng->msi32_low;
		pbm->msi64_start = ((u64)arng->msi64_high << 32) |
			(u64) arng->msi64_low;
		pbm->msi32_len = arng->msi32_len;
		pbm->msi64_len = arng->msi64_len;

		if (msi_bitmap_alloc(pbm))
			goto no_msi;

		if (msi_table_alloc(pbm)) {
			msi_bitmap_free(pbm);
			goto no_msi;
		}

		if (ops->msiq_alloc(pbm)) {
			msi_table_free(pbm);
			msi_bitmap_free(pbm);
			goto no_msi;
		}

		if (sparc64_bringup_msi_queues(pbm, ops)) {
			ops->msiq_free(pbm);
			msi_table_free(pbm);
			msi_bitmap_free(pbm);
			goto no_msi;
		}

		printk(KERN_INFO "%s: MSI Queue first[%u] num[%u] count[%u] "
		       "devino[0x%x]\n",
		       pbm->name,
		       pbm->msiq_first, pbm->msiq_num,
		       pbm->msiq_ent_count,
		       pbm->msiq_first_devino);
		printk(KERN_INFO "%s: MSI first[%u] num[%u] mask[0x%x] "
		       "width[%u]\n",
		       pbm->name,
		       pbm->msi_first, pbm->msi_num, pbm->msi_data_mask,
		       pbm->msix_data_width);
		printk(KERN_INFO "%s: MSI addr32[0x%llx:0x%x] "
		       "addr64[0x%llx:0x%x]\n",
		       pbm->name,
		       pbm->msi32_start, pbm->msi32_len,
		       pbm->msi64_start, pbm->msi64_len);
		printk(KERN_INFO "%s: MSI queues at RA [%016lx]\n",
		       pbm->name,
		       __pa(pbm->msi_queues));

		pbm->msi_ops = ops;
		pbm->setup_msi_irq = sparc64_setup_msi_irq;
		pbm->teardown_msi_irq = sparc64_teardown_msi_irq;
	}
	return;

no_msi:
	pbm->msiq_num = 0;
	printk(KERN_INFO "%s: No MSI support.\n", pbm->name);
}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
759f89e0 DM	2	/* pci_msi.c: Sparc64 MSI support common layer.
	3	*
	4	* Copyright (C) 2007 David S. Miller (davem@davemloft.net)
	5	*/
	6	#include <linux/kernel.h>
	7	#include <linux/interrupt.h>
5a0e3ad6	8	#include <linux/slab.h>
759f89e0 DM	9	#include <linux/irq.h>
	10
	11	#include "pci_impl.h"
	12
	13	static irqreturn_t sparc64_msiq_interrupt(int irq, void *cookie)
	14	{
	15	struct sparc64_msiq_cookie *msiq_cookie = cookie;
	16	struct pci_pbm_info *pbm = msiq_cookie->pbm;
	17	unsigned long msiqid = msiq_cookie->msiqid;
	18	const struct sparc64_msiq_ops *ops;
	19	unsigned long orig_head, head;
	20	int err;
	21
	22	ops = pbm->msi_ops;
	23
	24	err = ops->get_head(pbm, msiqid, &head);
	25	if (unlikely(err < 0))
	26	goto err_get_head;
	27
	28	orig_head = head;
	29	for (;;) {
	30	unsigned long msi;
	31
	32	err = ops->dequeue_msi(pbm, msiqid, &head, &msi);
8d57d3ad	33	if (likely(err > 0)) {
44ed3c0c	34	unsigned int irq;
8d57d3ad	35
44ed3c0c	36	irq = pbm->msi_irq_table[msi - pbm->msi_first];
16741ea0	37	generic_handle_irq(irq);
8d57d3ad	38	}
759f89e0 DM	39
	40	if (unlikely(err < 0))
	41	goto err_dequeue;
	42
	43	if (err == 0)
	44	break;
	45	}
	46	if (likely(head != orig_head)) {
	47	err = ops->set_head(pbm, msiqid, head);
	48	if (unlikely(err < 0))
	49	goto err_set_head;
	50	}
	51	return IRQ_HANDLED;
	52
	53	err_get_head:
	54	printk(KERN_EMERG "MSI: Get head on msiqid[%lu] gives error %d\n",
	55	msiqid, err);
	56	goto err_out;
	57
	58	err_dequeue:
	59	printk(KERN_EMERG "MSI: Dequeue head[%lu] from msiqid[%lu] "
	60	"gives error %d\n",
	61	head, msiqid, err);
	62	goto err_out;
	63
	64	err_set_head:
	65	printk(KERN_EMERG "MSI: Set head[%lu] on msiqid[%lu] "
	66	"gives error %d\n",
	67	head, msiqid, err);
	68	goto err_out;
	69
	70	err_out:
	71	return IRQ_NONE;
	72	}
	73
	74	static u32 pick_msiq(struct pci_pbm_info *pbm)
	75	{
	76	static DEFINE_SPINLOCK(rotor_lock);
	77	unsigned long flags;
	78	u32 ret, rotor;
	79
	80	spin_lock_irqsave(&rotor_lock, flags);
	81
	82	rotor = pbm->msiq_rotor;
	83	ret = pbm->msiq_first + rotor;
	84
	85	if (++rotor >= pbm->msiq_num)
	86	rotor = 0;
	87	pbm->msiq_rotor = rotor;
	88
	89	spin_unlock_irqrestore(&rotor_lock, flags);
	90
	91	return ret;
	92	}
	93
	94
	95	static int alloc_msi(struct pci_pbm_info *pbm)
	96	{
	97	int i;
	98
	99	for (i = 0; i < pbm->msi_num; i++) {
	100	if (!test_and_set_bit(i, pbm->msi_bitmap))
	101	return i + pbm->msi_first;
	102	}
103
104	return -ENOENT;
105	}
106
107	static void free_msi(struct pci_pbm_info *pbm, int msi_num)
108	{
109	msi_num -= pbm->msi_first;
110	clear_bit(msi_num, pbm->msi_bitmap);
111	}
112
113	static struct irq_chip msi_irq = {
89a7183d	114	.name = "PCI-MSI",
280510f1 TG	115	.irq_mask = pci_msi_mask_irq,
	116	.irq_unmask = pci_msi_unmask_irq,
	117	.irq_enable = pci_msi_unmask_irq,
	118	.irq_disable = pci_msi_mask_irq,
759f89e0 DM	119	/* XXX affinity XXX */
	120	};
	121
44ed3c0c	122	static int sparc64_setup_msi_irq(unsigned int *irq_p,
908f5162 AB	123	struct pci_dev *pdev,
908f5162 AB	124	struct msi_desc *entry)
759f89e0 DM	125	{
	126	struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
	127	const struct sparc64_msiq_ops *ops = pbm->msi_ops;
	128	struct msi_msg msg;
	129	int msi, err;
	130	u32 msiqid;
	131
44ed3c0c	132	*irq_p = irq_alloc(0, 0);
759f89e0	133	err = -ENOMEM;
44ed3c0c	134	if (!*irq_p)
759f89e0 DM	135	goto out_err;
759f89e0 DM	136
394d441b TG	137	irq_set_chip_and_handler_name(*irq_p, &msi_irq, handle_simple_irq,
394d441b TG	138	"MSI");
759f89e0 DM	139
	140	err = alloc_msi(pbm);
	141	if (unlikely(err < 0))
44ed3c0c	142	goto out_irq_free;
759f89e0 DM	143
	144	msi = err;
	145
	146	msiqid = pick_msiq(pbm);
	147
	148	err = ops->msi_setup(pbm, msiqid, msi,
	149	(entry->msi_attrib.is_64 ? 1 : 0));
	150	if (err)
	151	goto out_msi_free;
	152
44ed3c0c	153	pbm->msi_irq_table[msi - pbm->msi_first] = *irq_p;
759f89e0 DM	154
	155	if (entry->msi_attrib.is_64) {
	156	msg.address_hi = pbm->msi64_start >> 32;
	157	msg.address_lo = pbm->msi64_start & 0xffffffff;
	158	} else {
	159	msg.address_hi = 0;
	160	msg.address_lo = pbm->msi32_start;
	161	}
	162	msg.data = msi;
	163
394d441b	164	irq_set_msi_desc(*irq_p, entry);
83a18912	165	pci_write_msi_msg(*irq_p, &msg);
759f89e0 DM	166
	167	return 0;
	168
	169	out_msi_free:
	170	free_msi(pbm, msi);
	171
44ed3c0c	172	out_irq_free:
394d441b	173	irq_set_chip(*irq_p, NULL);
44ed3c0c SR	174	irq_free(*irq_p);
44ed3c0c SR	175	*irq_p = 0;
759f89e0 DM	176
	177	out_err:
	178	return err;
	179	}
	180
44ed3c0c	181	static void sparc64_teardown_msi_irq(unsigned int irq,
908f5162	182	struct pci_dev *pdev)
759f89e0 DM	183	{
	184	struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
	185	const struct sparc64_msiq_ops *ops = pbm->msi_ops;
	186	unsigned int msi_num;
	187	int i, err;
	188
	189	for (i = 0; i < pbm->msi_num; i++) {
44ed3c0c	190	if (pbm->msi_irq_table[i] == irq)
759f89e0 DM	191	break;
	192	}
	193	if (i >= pbm->msi_num) {
	194	printk(KERN_ERR "%s: teardown: No MSI for irq %u\n",
44ed3c0c	195	pbm->name, irq);
759f89e0 DM	196	return;
	197	}
	198
	199	msi_num = pbm->msi_first + i;
	200	pbm->msi_irq_table[i] = ~0U;
	201
	202	err = ops->msi_teardown(pbm, msi_num);
	203	if (err) {
	204	printk(KERN_ERR "%s: teardown: ops->teardown() on MSI %u, "
	205	"irq %u, gives error %d\n",
44ed3c0c	206	pbm->name, msi_num, irq, err);
759f89e0 DM	207	return;
	208	}
	209
	210	free_msi(pbm, msi_num);
	211
394d441b	212	irq_set_chip(irq, NULL);
44ed3c0c	213	irq_free(irq);
759f89e0 DM	214	}
	215
	216	static int msi_bitmap_alloc(struct pci_pbm_info *pbm)
	217	{
	218	unsigned long size, bits_per_ulong;
	219
	220	bits_per_ulong = sizeof(unsigned long) * 8;
	221	size = (pbm->msi_num + (bits_per_ulong - 1)) & ~(bits_per_ulong - 1);
	222	size /= 8;
	223	BUG_ON(size % sizeof(unsigned long));
	224
	225	pbm->msi_bitmap = kzalloc(size, GFP_KERNEL);
	226	if (!pbm->msi_bitmap)
	227	return -ENOMEM;
	228
	229	return 0;
	230	}
	231
	232	static void msi_bitmap_free(struct pci_pbm_info *pbm)
	233	{
	234	kfree(pbm->msi_bitmap);
	235	pbm->msi_bitmap = NULL;
	236	}
	237
	238	static int msi_table_alloc(struct pci_pbm_info *pbm)
	239	{
	240	int size, i;
	241
	242	size = pbm->msiq_num * sizeof(struct sparc64_msiq_cookie);
	243	pbm->msiq_irq_cookies = kzalloc(size, GFP_KERNEL);
	244	if (!pbm->msiq_irq_cookies)
	245	return -ENOMEM;
	246
	247	for (i = 0; i < pbm->msiq_num; i++) {
	248	struct sparc64_msiq_cookie *p;
	249
	250	p = &pbm->msiq_irq_cookies[i];
	251	p->pbm = pbm;
	252	p->msiqid = pbm->msiq_first + i;
	253	}
	254
	255	size = pbm->msi_num * sizeof(unsigned int);
	256	pbm->msi_irq_table = kzalloc(size, GFP_KERNEL);
	257	if (!pbm->msi_irq_table) {
	258	kfree(pbm->msiq_irq_cookies);
	259	pbm->msiq_irq_cookies = NULL;
	260	return -ENOMEM;
	261	}
	262
	263	return 0;
	264	}
	265
	266	static void msi_table_free(struct pci_pbm_info *pbm)
	267	{
	268	kfree(pbm->msiq_irq_cookies);
	269	pbm->msiq_irq_cookies = NULL;
	270
	271	kfree(pbm->msi_irq_table);
	272	pbm->msi_irq_table = NULL;
	273	}
	274
	275	static int bringup_one_msi_queue(struct pci_pbm_info *pbm,
	276	const struct sparc64_msiq_ops *ops,
	277	unsigned long msiqid,
278	unsigned long devino)
279	{
280	int irq = ops->msiq_build_irq(pbm, msiqid, devino);
c1b1a5f1	281	int err, nid;
759f89e0 DM	282
	283	if (irq < 0)
	284	return irq;
	285
c1b1a5f1 DM	286	nid = pbm->numa_node;
c1b1a5f1 DM	287	if (nid != -1) {
fb1fece5	288	cpumask_t numa_mask;
c1b1a5f1	289
fb1fece5	290	cpumask_copy(&numa_mask, cpumask_of_node(nid));
0de26520	291	irq_set_affinity(irq, &numa_mask);
c1b1a5f1	292	}
759f89e0 DM	293	err = request_irq(irq, sparc64_msiq_interrupt, 0,
	294	"MSIQ",
	295	&pbm->msiq_irq_cookies[msiqid - pbm->msiq_first]);
	296	if (err)
	297	return err;
	298
	299	return 0;
	300	}
	301
	302	static int sparc64_bringup_msi_queues(struct pci_pbm_info *pbm,
	303	const struct sparc64_msiq_ops *ops)
	304	{
	305	int i;
	306
	307	for (i = 0; i < pbm->msiq_num; i++) {
	308	unsigned long msiqid = i + pbm->msiq_first;
	309	unsigned long devino = i + pbm->msiq_first_devino;
	310	int err;
	311
	312	err = bringup_one_msi_queue(pbm, ops, msiqid, devino);
	313	if (err)
	314	return err;
	315	}
	316
	317	return 0;
	318	}
	319
	320	void sparc64_pbm_msi_init(struct pci_pbm_info *pbm,
	321	const struct sparc64_msiq_ops *ops)
	322	{
	323	const u32 *val;
	324	int len;
	325
61c7a080	326	val = of_get_property(pbm->op->dev.of_node, "#msi-eqs", &len);
759f89e0 DM	327	if (!val \|\| len != 4)
	328	goto no_msi;
	329	pbm->msiq_num = *val;
	330	if (pbm->msiq_num) {
	331	const struct msiq_prop {
	332	u32 first_msiq;
	333	u32 num_msiq;
	334	u32 first_devino;
	335	} *mqp;
	336	const struct msi_range_prop {
	337	u32 first_msi;
	338	u32 num_msi;
	339	} *mrng;
	340	const struct addr_range_prop {
	341	u32 msi32_high;
	342	u32 msi32_low;
	343	u32 msi32_len;
	344	u32 msi64_high;
	345	u32 msi64_low;
	346	u32 msi64_len;
	347	} *arng;
	348
61c7a080	349	val = of_get_property(pbm->op->dev.of_node, "msi-eq-size", &len);
759f89e0 DM	350	if (!val \|\| len != 4)
	351	goto no_msi;
	352
	353	pbm->msiq_ent_count = *val;
	354
61c7a080	355	mqp = of_get_property(pbm->op->dev.of_node,
759f89e0 DM	356	"msi-eq-to-devino", &len);
759f89e0 DM	357	if (!mqp)
61c7a080	358	mqp = of_get_property(pbm->op->dev.of_node,
759f89e0 DM	359	"msi-eq-devino", &len);
	360	if (!mqp \|\| len != sizeof(struct msiq_prop))
	361	goto no_msi;
	362
	363	pbm->msiq_first = mqp->first_msiq;
	364	pbm->msiq_first_devino = mqp->first_devino;
	365
61c7a080	366	val = of_get_property(pbm->op->dev.of_node, "#msi", &len);
759f89e0 DM	367	if (!val \|\| len != 4)
	368	goto no_msi;
	369	pbm->msi_num = *val;
	370
61c7a080	371	mrng = of_get_property(pbm->op->dev.of_node, "msi-ranges", &len);
759f89e0 DM	372	if (!mrng \|\| len != sizeof(struct msi_range_prop))
	373	goto no_msi;
	374	pbm->msi_first = mrng->first_msi;
	375
61c7a080	376	val = of_get_property(pbm->op->dev.of_node, "msi-data-mask", &len);
759f89e0 DM	377	if (!val \|\| len != 4)
	378	goto no_msi;
	379	pbm->msi_data_mask = *val;
	380
61c7a080	381	val = of_get_property(pbm->op->dev.of_node, "msix-data-width", &len);
759f89e0 DM	382	if (!val \|\| len != 4)
	383	goto no_msi;
	384	pbm->msix_data_width = *val;
	385
61c7a080	386	arng = of_get_property(pbm->op->dev.of_node, "msi-address-ranges",
759f89e0 DM	387	&len);
	388	if (!arng \|\| len != sizeof(struct addr_range_prop))
	389	goto no_msi;
	390	pbm->msi32_start = ((u64)arng->msi32_high << 32) \|
	391	(u64) arng->msi32_low;
	392	pbm->msi64_start = ((u64)arng->msi64_high << 32) \|
	393	(u64) arng->msi64_low;
	394	pbm->msi32_len = arng->msi32_len;
	395	pbm->msi64_len = arng->msi64_len;
	396
	397	if (msi_bitmap_alloc(pbm))
	398	goto no_msi;
	399
	400	if (msi_table_alloc(pbm)) {
	401	msi_bitmap_free(pbm);
	402	goto no_msi;
	403	}
	404
	405	if (ops->msiq_alloc(pbm)) {
	406	msi_table_free(pbm);
	407	msi_bitmap_free(pbm);
	408	goto no_msi;
	409	}
	410
	411	if (sparc64_bringup_msi_queues(pbm, ops)) {
	412	ops->msiq_free(pbm);
	413	msi_table_free(pbm);
	414	msi_bitmap_free(pbm);
	415	goto no_msi;
	416	}
	417
	418	printk(KERN_INFO "%s: MSI Queue first[%u] num[%u] count[%u] "
	419	"devino[0x%x]\n",
	420	pbm->name,
	421	pbm->msiq_first, pbm->msiq_num,
	422	pbm->msiq_ent_count,
	423	pbm->msiq_first_devino);
	424	printk(KERN_INFO "%s: MSI first[%u] num[%u] mask[0x%x] "
	425	"width[%u]\n",
	426	pbm->name,
	427	pbm->msi_first, pbm->msi_num, pbm->msi_data_mask,
	428	pbm->msix_data_width);
90181136 SR	429	printk(KERN_INFO "%s: MSI addr32[0x%llx:0x%x] "
90181136 SR	430	"addr64[0x%llx:0x%x]\n",
759f89e0 DM	431	pbm->name,
	432	pbm->msi32_start, pbm->msi32_len,
	433	pbm->msi64_start, pbm->msi64_len);
	434	printk(KERN_INFO "%s: MSI queues at RA [%016lx]\n",
	435	pbm->name,
	436	__pa(pbm->msi_queues));
	437
	438	pbm->msi_ops = ops;
	439	pbm->setup_msi_irq = sparc64_setup_msi_irq;
	440	pbm->teardown_msi_irq = sparc64_teardown_msi_irq;
	441	}
	442	return;
	443
	444	no_msi:
	445	pbm->msiq_num = 0;
	446	printk(KERN_INFO "%s: No MSI support.\n", pbm->name);
	447	}