[linux-2.6-block.git] / arch / sparc / kernel / pci_common.c

// SPDX-License-Identifier: GPL-2.0
/* pci_common.c: PCI controller common support.
 *
 * Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net)
 */

#include <linux/string.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/device.h>
#include <linux/of.h>
#include <linux/platform_device.h>

#include <asm/prom.h>
#include <asm/oplib.h>

#include "pci_impl.h"
#include "pci_sun4v.h"

static int config_out_of_range(struct pci_pbm_info *pbm,
			       unsigned long bus,
			       unsigned long devfn,
			       unsigned long reg)
{
	if (bus < pbm->pci_first_busno ||
	    bus > pbm->pci_last_busno)
		return 1;
	return 0;
}

static void *sun4u_config_mkaddr(struct pci_pbm_info *pbm,
				 unsigned long bus,
				 unsigned long devfn,
				 unsigned long reg)
{
	unsigned long rbits = pbm->config_space_reg_bits;

	if (config_out_of_range(pbm, bus, devfn, reg))
		return NULL;

	reg = (reg & ((1 << rbits) - 1));
	devfn <<= rbits;
	bus <<= rbits + 8;

	return (void *)	(pbm->config_space | bus | devfn | reg);
}

/* At least on Sabre, it is necessary to access all PCI host controller
 * registers at their natural size, otherwise zeros are returned.
 * Strange but true, and I see no language in the UltraSPARC-IIi
 * programmer's manual that mentions this even indirectly.
 */
static int sun4u_read_pci_cfg_host(struct pci_pbm_info *pbm,
				   unsigned char bus, unsigned int devfn,
				   int where, int size, u32 *value)
{
	u32 tmp32, *addr;
	u16 tmp16;
	u8 tmp8;

	addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
	if (!addr)
		return PCIBIOS_SUCCESSFUL;

	switch (size) {
	case 1:
		if (where < 8) {
			unsigned long align = (unsigned long) addr;

			align &= ~1;
			pci_config_read16((u16 *)align, &tmp16);
			if (where & 1)
				*value = tmp16 >> 8;
			else
				*value = tmp16 & 0xff;
		} else {
			pci_config_read8((u8 *)addr, &tmp8);
			*value = (u32) tmp8;
		}
		break;

	case 2:
		if (where < 8) {
			pci_config_read16((u16 *)addr, &tmp16);
			*value = (u32) tmp16;
		} else {
			pci_config_read8((u8 *)addr, &tmp8);
			*value = (u32) tmp8;
			pci_config_read8(((u8 *)addr) + 1, &tmp8);
			*value |= ((u32) tmp8) << 8;
		}
		break;

	case 4:
		tmp32 = 0xffffffff;
		sun4u_read_pci_cfg_host(pbm, bus, devfn,
					where, 2, &tmp32);
		*value = tmp32;

		tmp32 = 0xffffffff;
		sun4u_read_pci_cfg_host(pbm, bus, devfn,
					where + 2, 2, &tmp32);
		*value |= tmp32 << 16;
		break;
	}
	return PCIBIOS_SUCCESSFUL;
}

static int sun4u_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
			      int where, int size, u32 *value)
{
	struct pci_pbm_info *pbm = bus_dev->sysdata;
	unsigned char bus = bus_dev->number;
	u32 *addr;
	u16 tmp16;
	u8 tmp8;

	switch (size) {
	case 1:
		*value = 0xff;
		break;
	case 2:
		*value = 0xffff;
		break;
	case 4:
		*value = 0xffffffff;
		break;
	}

	if (!bus_dev->number && !PCI_SLOT(devfn))
		return sun4u_read_pci_cfg_host(pbm, bus, devfn, where,
					       size, value);

	addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
	if (!addr)
		return PCIBIOS_SUCCESSFUL;

	switch (size) {
	case 1:
		pci_config_read8((u8 *)addr, &tmp8);
		*value = (u32) tmp8;
		break;

	case 2:
		if (where & 0x01) {
			printk("pci_read_config_word: misaligned reg [%x]\n",
			       where);
			return PCIBIOS_SUCCESSFUL;
		}
		pci_config_read16((u16 *)addr, &tmp16);
		*value = (u32) tmp16;
		break;

	case 4:
		if (where & 0x03) {
			printk("pci_read_config_dword: misaligned reg [%x]\n",
			       where);
			return PCIBIOS_SUCCESSFUL;
		}
		pci_config_read32(addr, value);
		break;
	}
	return PCIBIOS_SUCCESSFUL;
}

static int sun4u_write_pci_cfg_host(struct pci_pbm_info *pbm,
				    unsigned char bus, unsigned int devfn,
				    int where, int size, u32 value)
{
	u32 *addr;

	addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
	if (!addr)
		return PCIBIOS_SUCCESSFUL;

	switch (size) {
	case 1:
		if (where < 8) {
			unsigned long align = (unsigned long) addr;
			u16 tmp16;

			align &= ~1;
			pci_config_read16((u16 *)align, &tmp16);
			if (where & 1) {
				tmp16 &= 0x00ff;
				tmp16 |= value << 8;
			} else {
				tmp16 &= 0xff00;
				tmp16 |= value;
			}
			pci_config_write16((u16 *)align, tmp16);
		} else
			pci_config_write8((u8 *)addr, value);
		break;
	case 2:
		if (where < 8) {
			pci_config_write16((u16 *)addr, value);
		} else {
			pci_config_write8((u8 *)addr, value & 0xff);
			pci_config_write8(((u8 *)addr) + 1, value >> 8);
		}
		break;
	case 4:
		sun4u_write_pci_cfg_host(pbm, bus, devfn,
					 where, 2, value & 0xffff);
		sun4u_write_pci_cfg_host(pbm, bus, devfn,
					 where + 2, 2, value >> 16);
		break;
	}
	return PCIBIOS_SUCCESSFUL;
}

static int sun4u_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
			       int where, int size, u32 value)
{
	struct pci_pbm_info *pbm = bus_dev->sysdata;
	unsigned char bus = bus_dev->number;
	u32 *addr;

	if (!bus_dev->number && !PCI_SLOT(devfn))
		return sun4u_write_pci_cfg_host(pbm, bus, devfn, where,
						size, value);

	addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
	if (!addr)
		return PCIBIOS_SUCCESSFUL;

	switch (size) {
	case 1:
		pci_config_write8((u8 *)addr, value);
		break;

	case 2:
		if (where & 0x01) {
			printk("pci_write_config_word: misaligned reg [%x]\n",
			       where);
			return PCIBIOS_SUCCESSFUL;
		}
		pci_config_write16((u16 *)addr, value);
		break;

	case 4:
		if (where & 0x03) {
			printk("pci_write_config_dword: misaligned reg [%x]\n",
			       where);
			return PCIBIOS_SUCCESSFUL;
		}
		pci_config_write32(addr, value);
	}
	return PCIBIOS_SUCCESSFUL;
}

struct pci_ops sun4u_pci_ops = {
	.read =		sun4u_read_pci_cfg,
	.write =	sun4u_write_pci_cfg,
};

static int sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
			      int where, int size, u32 *value)
{
	struct pci_pbm_info *pbm = bus_dev->sysdata;
	u32 devhandle = pbm->devhandle;
	unsigned int bus = bus_dev->number;
	unsigned int device = PCI_SLOT(devfn);
	unsigned int func = PCI_FUNC(devfn);
	unsigned long ret;

	if (config_out_of_range(pbm, bus, devfn, where)) {
		ret = ~0UL;
	} else {
		ret = pci_sun4v_config_get(devhandle,
				HV_PCI_DEVICE_BUILD(bus, device, func),
				where, size);
	}
	switch (size) {
	case 1:
		*value = ret & 0xff;
		break;
	case 2:
		*value = ret & 0xffff;
		break;
	case 4:
		*value = ret & 0xffffffff;
		break;
	}


	return PCIBIOS_SUCCESSFUL;
}

static int sun4v_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
			       int where, int size, u32 value)
{
	struct pci_pbm_info *pbm = bus_dev->sysdata;
	u32 devhandle = pbm->devhandle;
	unsigned int bus = bus_dev->number;
	unsigned int device = PCI_SLOT(devfn);
	unsigned int func = PCI_FUNC(devfn);

	if (config_out_of_range(pbm, bus, devfn, where)) {
		/* Do nothing. */
	} else {
		/* We don't check for hypervisor errors here, but perhaps
		 * we should and influence our return value depending upon
		 * what kind of error is thrown.
		 */
		pci_sun4v_config_put(devhandle,
				     HV_PCI_DEVICE_BUILD(bus, device, func),
				     where, size, value);
	}
	return PCIBIOS_SUCCESSFUL;
}

struct pci_ops sun4v_pci_ops = {
	.read =		sun4v_read_pci_cfg,
	.write =	sun4v_write_pci_cfg,
};

void pci_get_pbm_props(struct pci_pbm_info *pbm)
{
	const u32 *val = of_get_property(pbm->op->dev.of_node, "bus-range", NULL);

	pbm->pci_first_busno = val[0];
	pbm->pci_last_busno = val[1];

	val = of_get_property(pbm->op->dev.of_node, "ino-bitmap", NULL);
	if (val) {
		pbm->ino_bitmap = (((u64)val[1] << 32UL) |
				   ((u64)val[0] <<  0UL));
	}
}

static void pci_register_iommu_region(struct pci_pbm_info *pbm)
{
	const u32 *vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma",
					  NULL);

	if (vdma) {
		struct resource *rp = kzalloc(sizeof(*rp), GFP_KERNEL);

		if (!rp) {
			pr_info("%s: Cannot allocate IOMMU resource.\n",
				pbm->name);
			return;
		}
		rp->name = "IOMMU";
		rp->start = pbm->mem_space.start + (unsigned long) vdma[0];
		rp->end = rp->start + (unsigned long) vdma[1] - 1UL;
		rp->flags = IORESOURCE_BUSY;
		if (request_resource(&pbm->mem_space, rp)) {
			pr_info("%s: Unable to request IOMMU resource.\n",
				pbm->name);
			kfree(rp);
		}
	}
}

void pci_determine_mem_io_space(struct pci_pbm_info *pbm)
{
	const struct linux_prom_pci_ranges *pbm_ranges;
	int i, saw_mem, saw_io;
	int num_pbm_ranges;

	/* Corresponding generic code in of_pci_get_host_bridge_resources() */

	saw_mem = saw_io = 0;
	pbm_ranges = of_get_property(pbm->op->dev.of_node, "ranges", &i);
	if (!pbm_ranges) {
		prom_printf("PCI: Fatal error, missing PBM ranges property "
			    " for %s\n",
			    pbm->name);
		prom_halt();
	}

	num_pbm_ranges = i / sizeof(*pbm_ranges);
	memset(&pbm->mem64_space, 0, sizeof(struct resource));

	for (i = 0; i < num_pbm_ranges; i++) {
		const struct linux_prom_pci_ranges *pr = &pbm_ranges[i];
		unsigned long a, size, region_a;
		u32 parent_phys_hi, parent_phys_lo;
		u32 child_phys_mid, child_phys_lo;
		u32 size_hi, size_lo;
		int type;

		parent_phys_hi = pr->parent_phys_hi;
		parent_phys_lo = pr->parent_phys_lo;
		child_phys_mid = pr->child_phys_mid;
		child_phys_lo = pr->child_phys_lo;
		if (tlb_type == hypervisor)
			parent_phys_hi &= 0x0fffffff;

		size_hi = pr->size_hi;
		size_lo = pr->size_lo;

		type = (pr->child_phys_hi >> 24) & 0x3;
		a = (((unsigned long)parent_phys_hi << 32UL) |
		     ((unsigned long)parent_phys_lo  <<  0UL));
		region_a = (((unsigned long)child_phys_mid << 32UL) |
		     ((unsigned long)child_phys_lo  <<  0UL));
		size = (((unsigned long)size_hi << 32UL) |
			((unsigned long)size_lo  <<  0UL));

		switch (type) {
		case 0:
			/* PCI config space, 16MB */
			pbm->config_space = a;
			break;

		case 1:
			/* 16-bit IO space, 16MB */
			pbm->io_space.start = a;
			pbm->io_space.end = a + size - 1UL;
			pbm->io_space.flags = IORESOURCE_IO;
			pbm->io_offset = a - region_a;
			saw_io = 1;
			break;

		case 2:
			/* 32-bit MEM space, 2GB */
			pbm->mem_space.start = a;
			pbm->mem_space.end = a + size - 1UL;
			pbm->mem_space.flags = IORESOURCE_MEM;
			pbm->mem_offset = a - region_a;
			saw_mem = 1;
			break;

		case 3:
			/* 64-bit MEM handling */
			pbm->mem64_space.start = a;
			pbm->mem64_space.end = a + size - 1UL;
			pbm->mem64_space.flags = IORESOURCE_MEM;
			pbm->mem64_offset = a - region_a;
			saw_mem = 1;
			break;

		default:
			break;
		}
	}

	if (!saw_io || !saw_mem) {
		prom_printf("%s: Fatal error, missing %s PBM range.\n",
			    pbm->name,
			    (!saw_io ? "IO" : "MEM"));
		prom_halt();
	}

	if (pbm->io_space.flags)
		printk("%s: PCI IO %pR offset %llx\n",
		       pbm->name, &pbm->io_space, pbm->io_offset);
	if (pbm->mem_space.flags)
		printk("%s: PCI MEM %pR offset %llx\n",
		       pbm->name, &pbm->mem_space, pbm->mem_offset);
	if (pbm->mem64_space.flags && pbm->mem_space.flags) {
		if (pbm->mem64_space.start <= pbm->mem_space.end)
			pbm->mem64_space.start = pbm->mem_space.end + 1;
		if (pbm->mem64_space.start > pbm->mem64_space.end)
			pbm->mem64_space.flags = 0;
	}

	if (pbm->mem64_space.flags)
		printk("%s: PCI MEM64 %pR offset %llx\n",
		       pbm->name, &pbm->mem64_space, pbm->mem64_offset);

	pbm->io_space.name = pbm->mem_space.name = pbm->name;
	pbm->mem64_space.name = pbm->name;

	request_resource(&ioport_resource, &pbm->io_space);
	request_resource(&iomem_resource, &pbm->mem_space);
	if (pbm->mem64_space.flags)
		request_resource(&iomem_resource, &pbm->mem64_space);

	pci_register_iommu_region(pbm);
}

/* Generic helper routines for PCI error reporting. */
void pci_scan_for_target_abort(struct pci_pbm_info *pbm,
			       struct pci_bus *pbus)
{
	struct pci_dev *pdev;
	struct pci_bus *bus;

	list_for_each_entry(pdev, &pbus->devices, bus_list) {
		u16 status, error_bits;

		pci_read_config_word(pdev, PCI_STATUS, &status);
		error_bits =
			(status & (PCI_STATUS_SIG_TARGET_ABORT |
				   PCI_STATUS_REC_TARGET_ABORT));
		if (error_bits) {
			pci_write_config_word(pdev, PCI_STATUS, error_bits);
			pci_info(pdev, "%s: Device saw Target Abort [%016x]\n",
				 pbm->name, status);
		}
	}

	list_for_each_entry(bus, &pbus->children, node)
		pci_scan_for_target_abort(pbm, bus);
}

void pci_scan_for_master_abort(struct pci_pbm_info *pbm,
			       struct pci_bus *pbus)
{
	struct pci_dev *pdev;
	struct pci_bus *bus;

	list_for_each_entry(pdev, &pbus->devices, bus_list) {
		u16 status, error_bits;

		pci_read_config_word(pdev, PCI_STATUS, &status);
		error_bits =
			(status & (PCI_STATUS_REC_MASTER_ABORT));
		if (error_bits) {
			pci_write_config_word(pdev, PCI_STATUS, error_bits);
			pci_info(pdev, "%s: Device received Master Abort "
				 "[%016x]\n", pbm->name, status);
		}
	}

	list_for_each_entry(bus, &pbus->children, node)
		pci_scan_for_master_abort(pbm, bus);
}

void pci_scan_for_parity_error(struct pci_pbm_info *pbm,
			       struct pci_bus *pbus)
{
	struct pci_dev *pdev;
	struct pci_bus *bus;

	list_for_each_entry(pdev, &pbus->devices, bus_list) {
		u16 status, error_bits;

		pci_read_config_word(pdev, PCI_STATUS, &status);
		error_bits =
			(status & (PCI_STATUS_PARITY |
				   PCI_STATUS_DETECTED_PARITY));
		if (error_bits) {
			pci_write_config_word(pdev, PCI_STATUS, error_bits);
			pci_info(pdev, "%s: Device saw Parity Error [%016x]\n",
				 pbm->name, status);
		}
	}

	list_for_each_entry(bus, &pbus->children, node)
		pci_scan_for_parity_error(pbm, bus);
}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
9fd8b647	2	/* pci_common.c: PCI controller common support.
1da177e4	3	*
9fd8b647	4	* Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net)
1da177e4 LT	5	*/
	6
	7	#include <linux/string.h>
	8	#include <linux/slab.h>
cf69eab2 FMDN	9	#include <linux/pci.h>
cf69eab2 FMDN	10	#include <linux/device.h>
263291fa RH	11	#include <linux/of.h>
263291fa RH	12	#include <linux/platform_device.h>
1da177e4	13
de8d28b1	14	#include <asm/prom.h>
c57c2ffb	15	#include <asm/oplib.h>
de8d28b1 DM	16
de8d28b1 DM	17	#include "pci_impl.h"
ca3dd88e DM	18	#include "pci_sun4v.h"
	19
	20	static int config_out_of_range(struct pci_pbm_info *pbm,
	21	unsigned long bus,
	22	unsigned long devfn,
	23	unsigned long reg)
	24	{
	25	if (bus < pbm->pci_first_busno \|\|
	26	bus > pbm->pci_last_busno)
	27	return 1;
	28	return 0;
	29	}
	30
	31	static void sun4u_config_mkaddr(struct pci_pbm_info pbm,
	32	unsigned long bus,
	33	unsigned long devfn,
	34	unsigned long reg)
	35	{
	36	unsigned long rbits = pbm->config_space_reg_bits;
	37
	38	if (config_out_of_range(pbm, bus, devfn, reg))
	39	return NULL;
	40
	41	reg = (reg & ((1 << rbits) - 1));
	42	devfn <<= rbits;
	43	bus <<= rbits + 8;
	44
	45	return (void *) (pbm->config_space \| bus \| devfn \| reg);
	46	}
	47
a2d6ea01 DM	48	/* At least on Sabre, it is necessary to access all PCI host controller
	49	* registers at their natural size, otherwise zeros are returned.
	50	* Strange but true, and I see no language in the UltraSPARC-IIi
	51	* programmer's manual that mentions this even indirectly.
	52	*/
	53	static int sun4u_read_pci_cfg_host(struct pci_pbm_info *pbm,
	54	unsigned char bus, unsigned int devfn,
	55	int where, int size, u32 *value)
	56	{
	57	u32 tmp32, *addr;
	58	u16 tmp16;
	59	u8 tmp8;
	60
	61	addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
	62	if (!addr)
	63	return PCIBIOS_SUCCESSFUL;
	64
	65	switch (size) {
	66	case 1:
	67	if (where < 8) {
	68	unsigned long align = (unsigned long) addr;
	69
	70	align &= ~1;
	71	pci_config_read16((u16 *)align, &tmp16);
	72	if (where & 1)
	73	*value = tmp16 >> 8;
	74	else
	75	*value = tmp16 & 0xff;
	76	} else {
	77	pci_config_read8((u8 *)addr, &tmp8);
	78	*value = (u32) tmp8;
	79	}
	80	break;
	81
	82	case 2:
	83	if (where < 8) {
	84	pci_config_read16((u16 *)addr, &tmp16);
	85	*value = (u32) tmp16;
	86	} else {
	87	pci_config_read8((u8 *)addr, &tmp8);
	88	*value = (u32) tmp8;
	89	pci_config_read8(((u8 *)addr) + 1, &tmp8);
	90	*value \|= ((u32) tmp8) << 8;
	91	}
	92	break;
	93
	94	case 4:
	95	tmp32 = 0xffffffff;
	96	sun4u_read_pci_cfg_host(pbm, bus, devfn,
	97	where, 2, &tmp32);
	98	*value = tmp32;
	99
	100	tmp32 = 0xffffffff;
	101	sun4u_read_pci_cfg_host(pbm, bus, devfn,
	102	where + 2, 2, &tmp32);
	103	*value \|= tmp32 << 16;
	104	break;
	105	}
	106	return PCIBIOS_SUCCESSFUL;
	107	}
	108
ca3dd88e DM	109	static int sun4u_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
	110	int where, int size, u32 *value)
	111	{
	112	struct pci_pbm_info *pbm = bus_dev->sysdata;
	113	unsigned char bus = bus_dev->number;
	114	u32 *addr;
	115	u16 tmp16;
	116	u8 tmp8;
	117
ca3dd88e DM	118	switch (size) {
	119	case 1:
	120	*value = 0xff;
	121	break;
	122	case 2:
	123	*value = 0xffff;
	124	break;
	125	case 4:
	126	*value = 0xffffffff;
	127	break;
	128	}
	129
a2d6ea01 DM	130	if (!bus_dev->number && !PCI_SLOT(devfn))
	131	return sun4u_read_pci_cfg_host(pbm, bus, devfn, where,
	132	size, value);
	133
ca3dd88e DM	134	addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
	135	if (!addr)
	136	return PCIBIOS_SUCCESSFUL;
	137
	138	switch (size) {
	139	case 1:
	140	pci_config_read8((u8 *)addr, &tmp8);
	141	*value = (u32) tmp8;
	142	break;
	143
	144	case 2:
	145	if (where & 0x01) {
	146	printk("pci_read_config_word: misaligned reg [%x]\n",
	147	where);
	148	return PCIBIOS_SUCCESSFUL;
	149	}
	150	pci_config_read16((u16 *)addr, &tmp16);
	151	*value = (u32) tmp16;
	152	break;
	153
	154	case 4:
	155	if (where & 0x03) {
	156	printk("pci_read_config_dword: misaligned reg [%x]\n",
	157	where);
	158	return PCIBIOS_SUCCESSFUL;
	159	}
	160	pci_config_read32(addr, value);
	161	break;
	162	}
	163	return PCIBIOS_SUCCESSFUL;
	164	}
	165
a2d6ea01 DM	166	static int sun4u_write_pci_cfg_host(struct pci_pbm_info *pbm,
	167	unsigned char bus, unsigned int devfn,
	168	int where, int size, u32 value)
	169	{
	170	u32 *addr;
	171
	172	addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
	173	if (!addr)
	174	return PCIBIOS_SUCCESSFUL;
	175
	176	switch (size) {
	177	case 1:
	178	if (where < 8) {
	179	unsigned long align = (unsigned long) addr;
	180	u16 tmp16;
	181
	182	align &= ~1;
	183	pci_config_read16((u16 *)align, &tmp16);
	184	if (where & 1) {
	185	tmp16 &= 0x00ff;
	186	tmp16 \|= value << 8;
	187	} else {
	188	tmp16 &= 0xff00;
	189	tmp16 \|= value;
	190	}
	191	pci_config_write16((u16 *)align, tmp16);
	192	} else
	193	pci_config_write8((u8 *)addr, value);
	194	break;
	195	case 2:
	196	if (where < 8) {
	197	pci_config_write16((u16 *)addr, value);
	198	} else {
	199	pci_config_write8((u8 *)addr, value & 0xff);
	200	pci_config_write8(((u8 *)addr) + 1, value >> 8);
	201	}
	202	break;
	203	case 4:
	204	sun4u_write_pci_cfg_host(pbm, bus, devfn,
	205	where, 2, value & 0xffff);
	206	sun4u_write_pci_cfg_host(pbm, bus, devfn,
	207	where + 2, 2, value >> 16);
	208	break;
	209	}
	210	return PCIBIOS_SUCCESSFUL;
	211	}
	212
ca3dd88e DM	213	static int sun4u_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
	214	int where, int size, u32 value)
	215	{
	216	struct pci_pbm_info *pbm = bus_dev->sysdata;
	217	unsigned char bus = bus_dev->number;
	218	u32 *addr;
	219
a2d6ea01 DM	220	if (!bus_dev->number && !PCI_SLOT(devfn))
	221	return sun4u_write_pci_cfg_host(pbm, bus, devfn, where,
	222	size, value);
	223
ca3dd88e DM	224	addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
	225	if (!addr)
	226	return PCIBIOS_SUCCESSFUL;
	227
	228	switch (size) {
	229	case 1:
	230	pci_config_write8((u8 *)addr, value);
	231	break;
	232
	233	case 2:
	234	if (where & 0x01) {
	235	printk("pci_write_config_word: misaligned reg [%x]\n",
	236	where);
	237	return PCIBIOS_SUCCESSFUL;
	238	}
	239	pci_config_write16((u16 *)addr, value);
	240	break;
	241
	242	case 4:
	243	if (where & 0x03) {
	244	printk("pci_write_config_dword: misaligned reg [%x]\n",
	245	where);
	246	return PCIBIOS_SUCCESSFUL;
	247	}
	248	pci_config_write32(addr, value);
	249	}
	250	return PCIBIOS_SUCCESSFUL;
	251	}
	252
	253	struct pci_ops sun4u_pci_ops = {
	254	.read = sun4u_read_pci_cfg,
	255	.write = sun4u_write_pci_cfg,
	256	};
	257
	258	static int sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
	259	int where, int size, u32 *value)
	260	{
	261	struct pci_pbm_info *pbm = bus_dev->sysdata;
	262	u32 devhandle = pbm->devhandle;
	263	unsigned int bus = bus_dev->number;
	264	unsigned int device = PCI_SLOT(devfn);
	265	unsigned int func = PCI_FUNC(devfn);
	266	unsigned long ret;
	267
ca3dd88e DM	268	if (config_out_of_range(pbm, bus, devfn, where)) {
	269	ret = ~0UL;
	270	} else {
	271	ret = pci_sun4v_config_get(devhandle,
	272	HV_PCI_DEVICE_BUILD(bus, device, func),
	273	where, size);
	274	}
	275	switch (size) {
	276	case 1:
	277	*value = ret & 0xff;
	278	break;
	279	case 2:
	280	*value = ret & 0xffff;
	281	break;
	282	case 4:
	283	*value = ret & 0xffffffff;
	284	break;
6cb79b3f	285	}
ca3dd88e DM	286
	287
	288	return PCIBIOS_SUCCESSFUL;
	289	}
	290
	291	static int sun4v_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
	292	int where, int size, u32 value)
	293	{
	294	struct pci_pbm_info *pbm = bus_dev->sysdata;
	295	u32 devhandle = pbm->devhandle;
	296	unsigned int bus = bus_dev->number;
	297	unsigned int device = PCI_SLOT(devfn);
	298	unsigned int func = PCI_FUNC(devfn);
ca3dd88e	299
ca3dd88e DM	300	if (config_out_of_range(pbm, bus, devfn, where)) {
	301	/* Do nothing. */
	302	} else {
c6fee081 DM	303	/* We don't check for hypervisor errors here, but perhaps
	304	* we should and influence our return value depending upon
	305	* what kind of error is thrown.
	306	*/
	307	pci_sun4v_config_put(devhandle,
	308	HV_PCI_DEVICE_BUILD(bus, device, func),
	309	where, size, value);
ca3dd88e DM	310	}
	311	return PCIBIOS_SUCCESSFUL;
	312	}
	313
	314	struct pci_ops sun4v_pci_ops = {
	315	.read = sun4v_read_pci_cfg,
	316	.write = sun4v_write_pci_cfg,
	317	};
1da177e4	318
cfa0652c DM	319	void pci_get_pbm_props(struct pci_pbm_info *pbm)
cfa0652c DM	320	{
61c7a080	321	const u32 *val = of_get_property(pbm->op->dev.of_node, "bus-range", NULL);
cfa0652c DM	322
	323	pbm->pci_first_busno = val[0];
	324	pbm->pci_last_busno = val[1];
	325
61c7a080	326	val = of_get_property(pbm->op->dev.of_node, "ino-bitmap", NULL);
cfa0652c DM	327	if (val) {
	328	pbm->ino_bitmap = (((u64)val[1] << 32UL) \|
	329	((u64)val[0] << 0UL));
	330	}
	331	}
	332
9fd8b647 DM	333	static void pci_register_iommu_region(struct pci_pbm_info *pbm)
9fd8b647 DM	334	{
61c7a080 GL	335	const u32 *vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma",
61c7a080 GL	336	NULL);
9fd8b647 DM	337
9fd8b647 DM	338	if (vdma) {
192d7a46	339	struct resource rp = kzalloc(sizeof(rp), GFP_KERNEL);
9fd8b647 DM	340
9fd8b647 DM	341	if (!rp) {
e182c77c DM	342	pr_info("%s: Cannot allocate IOMMU resource.\n",
	343	pbm->name);
	344	return;
9fd8b647 DM	345	}
	346	rp->name = "IOMMU";
	347	rp->start = pbm->mem_space.start + (unsigned long) vdma[0];
	348	rp->end = rp->start + (unsigned long) vdma[1] - 1UL;
	349	rp->flags = IORESOURCE_BUSY;
e182c77c DM	350	if (request_resource(&pbm->mem_space, rp)) {
	351	pr_info("%s: Unable to request IOMMU resource.\n",
	352	pbm->name);
	353	kfree(rp);
	354	}
9fd8b647 DM	355	}
	356	}
	357
	358	void pci_determine_mem_io_space(struct pci_pbm_info *pbm)
	359	{
a165b420	360	const struct linux_prom_pci_ranges *pbm_ranges;
9fd8b647	361	int i, saw_mem, saw_io;
3487a1f9	362	int num_pbm_ranges;
9fd8b647	363
b4a30448 YL	364	/* Corresponding generic code in of_pci_get_host_bridge_resources() */
b4a30448 YL	365
9fd8b647	366	saw_mem = saw_io = 0;
61c7a080	367	pbm_ranges = of_get_property(pbm->op->dev.of_node, "ranges", &i);
4209ab09 DM	368	if (!pbm_ranges) {
	369	prom_printf("PCI: Fatal error, missing PBM ranges property "
	370	" for %s\n",
	371	pbm->name);
	372	prom_halt();
	373	}
	374
3487a1f9	375	num_pbm_ranges = i / sizeof(*pbm_ranges);
af86fa40	376	memset(&pbm->mem64_space, 0, sizeof(struct resource));
3487a1f9 DM	377
3487a1f9 DM	378	for (i = 0; i < num_pbm_ranges; i++) {
a165b420	379	const struct linux_prom_pci_ranges *pr = &pbm_ranges[i];
b4a30448	380	unsigned long a, size, region_a;
3487a1f9	381	u32 parent_phys_hi, parent_phys_lo;
b4a30448	382	u32 child_phys_mid, child_phys_lo;
56f5c0bd	383	u32 size_hi, size_lo;
9fd8b647 DM	384	int type;
9fd8b647 DM	385
3487a1f9 DM	386	parent_phys_hi = pr->parent_phys_hi;
3487a1f9 DM	387	parent_phys_lo = pr->parent_phys_lo;
b4a30448 YL	388	child_phys_mid = pr->child_phys_mid;
b4a30448 YL	389	child_phys_lo = pr->child_phys_lo;
3487a1f9 DM	390	if (tlb_type == hypervisor)
	391	parent_phys_hi &= 0x0fffffff;
	392
56f5c0bd DM	393	size_hi = pr->size_hi;
	394	size_lo = pr->size_lo;
	395
9fd8b647	396	type = (pr->child_phys_hi >> 24) & 0x3;
3487a1f9 DM	397	a = (((unsigned long)parent_phys_hi << 32UL) \|
3487a1f9 DM	398	((unsigned long)parent_phys_lo << 0UL));
b4a30448 YL	399	region_a = (((unsigned long)child_phys_mid << 32UL) \|
b4a30448 YL	400	((unsigned long)child_phys_lo << 0UL));
56f5c0bd DM	401	size = (((unsigned long)size_hi << 32UL) \|
56f5c0bd DM	402	((unsigned long)size_lo << 0UL));
9fd8b647 DM	403
	404	switch (type) {
	405	case 0:
	406	/* PCI config space, 16MB */
	407	pbm->config_space = a;
	408	break;
	409
	410	case 1:
	411	/* 16-bit IO space, 16MB */
	412	pbm->io_space.start = a;
56f5c0bd	413	pbm->io_space.end = a + size - 1UL;
9fd8b647	414	pbm->io_space.flags = IORESOURCE_IO;
b4a30448	415	pbm->io_offset = a - region_a;
9fd8b647 DM	416	saw_io = 1;
	417	break;
	418
	419	case 2:
	420	/* 32-bit MEM space, 2GB */
	421	pbm->mem_space.start = a;
56f5c0bd	422	pbm->mem_space.end = a + size - 1UL;
9fd8b647	423	pbm->mem_space.flags = IORESOURCE_MEM;
b4a30448	424	pbm->mem_offset = a - region_a;
9fd8b647 DM	425	saw_mem = 1;
	426	break;
	427
	428	case 3:
af86fa40 YL	429	/* 64-bit MEM handling */
	430	pbm->mem64_space.start = a;
	431	pbm->mem64_space.end = a + size - 1UL;
	432	pbm->mem64_space.flags = IORESOURCE_MEM;
b4a30448	433	pbm->mem64_offset = a - region_a;
af86fa40 YL	434	saw_mem = 1;
af86fa40 YL	435	break;
9fd8b647 DM	436
	437	default:
	438	break;
6cb79b3f	439	}
9fd8b647 DM	440	}
	441
	442	if (!saw_io \|\| !saw_mem) {
	443	prom_printf("%s: Fatal error, missing %s PBM range.\n",
	444	pbm->name,
	445	(!saw_io ? "IO" : "MEM"));
	446	prom_halt();
	447	}
	448
b4a30448 YL	449	if (pbm->io_space.flags)
	450	printk("%s: PCI IO %pR offset %llx\n",
	451	pbm->name, &pbm->io_space, pbm->io_offset);
	452	if (pbm->mem_space.flags)
	453	printk("%s: PCI MEM %pR offset %llx\n",
	454	pbm->name, &pbm->mem_space, pbm->mem_offset);
	455	if (pbm->mem64_space.flags && pbm->mem_space.flags) {
	456	if (pbm->mem64_space.start <= pbm->mem_space.end)
	457	pbm->mem64_space.start = pbm->mem_space.end + 1;
	458	if (pbm->mem64_space.start > pbm->mem64_space.end)
	459	pbm->mem64_space.flags = 0;
	460	}
	461
af86fa40	462	if (pbm->mem64_space.flags)
b4a30448 YL	463	printk("%s: PCI MEM64 %pR offset %llx\n",
b4a30448 YL	464	pbm->name, &pbm->mem64_space, pbm->mem64_offset);
9fd8b647 DM	465
9fd8b647 DM	466	pbm->io_space.name = pbm->mem_space.name = pbm->name;
af86fa40	467	pbm->mem64_space.name = pbm->name;
9fd8b647 DM	468
	469	request_resource(&ioport_resource, &pbm->io_space);
	470	request_resource(&iomem_resource, &pbm->mem_space);
af86fa40 YL	471	if (pbm->mem64_space.flags)
af86fa40 YL	472	request_resource(&iomem_resource, &pbm->mem64_space);
9fd8b647	473
9fd8b647 DM	474	pci_register_iommu_region(pbm);
	475	}
	476
1da177e4	477	/* Generic helper routines for PCI error reporting. */
6c108f12	478	void pci_scan_for_target_abort(struct pci_pbm_info *pbm,
1da177e4 LT	479	struct pci_bus *pbus)
	480	{
	481	struct pci_dev *pdev;
	482	struct pci_bus *bus;
	483
	484	list_for_each_entry(pdev, &pbus->devices, bus_list) {
	485	u16 status, error_bits;
	486
	487	pci_read_config_word(pdev, PCI_STATUS, &status);
	488	error_bits =
	489	(status & (PCI_STATUS_SIG_TARGET_ABORT \|
	490	PCI_STATUS_REC_TARGET_ABORT));
	491	if (error_bits) {
	492	pci_write_config_word(pdev, PCI_STATUS, error_bits);
adedc05e BH	493	pci_info(pdev, "%s: Device saw Target Abort [%016x]\n",
adedc05e BH	494	pbm->name, status);
1da177e4 LT	495	}
	496	}
	497
	498	list_for_each_entry(bus, &pbus->children, node)
6c108f12	499	pci_scan_for_target_abort(pbm, bus);
1da177e4 LT	500	}
1da177e4 LT	501
6c108f12	502	void pci_scan_for_master_abort(struct pci_pbm_info *pbm,
1da177e4 LT	503	struct pci_bus *pbus)
	504	{
	505	struct pci_dev *pdev;
	506	struct pci_bus *bus;
	507
	508	list_for_each_entry(pdev, &pbus->devices, bus_list) {
	509	u16 status, error_bits;
	510
	511	pci_read_config_word(pdev, PCI_STATUS, &status);
	512	error_bits =
	513	(status & (PCI_STATUS_REC_MASTER_ABORT));
	514	if (error_bits) {
	515	pci_write_config_word(pdev, PCI_STATUS, error_bits);
adedc05e BH	516	pci_info(pdev, "%s: Device received Master Abort "
adedc05e BH	517	"[%016x]\n", pbm->name, status);
1da177e4 LT	518	}
	519	}
	520
	521	list_for_each_entry(bus, &pbus->children, node)
6c108f12	522	pci_scan_for_master_abort(pbm, bus);
1da177e4 LT	523	}
1da177e4 LT	524
6c108f12	525	void pci_scan_for_parity_error(struct pci_pbm_info *pbm,
1da177e4 LT	526	struct pci_bus *pbus)
	527	{
	528	struct pci_dev *pdev;
	529	struct pci_bus *bus;
	530
	531	list_for_each_entry(pdev, &pbus->devices, bus_list) {
	532	u16 status, error_bits;
	533
	534	pci_read_config_word(pdev, PCI_STATUS, &status);
	535	error_bits =
	536	(status & (PCI_STATUS_PARITY \|
	537	PCI_STATUS_DETECTED_PARITY));
	538	if (error_bits) {
	539	pci_write_config_word(pdev, PCI_STATUS, error_bits);
adedc05e BH	540	pci_info(pdev, "%s: Device saw Parity Error [%016x]\n",
adedc05e BH	541	pbm->name, status);
1da177e4 LT	542	}
	543	}
	544
	545	list_for_each_entry(bus, &pbus->children, node)
6c108f12	546	pci_scan_for_parity_error(pbm, bus);
1da177e4	547	}