[linux-2.6-block.git] / arch / sparc / kernel / pci_common.c

/* pci_common.c: PCI controller common support.
 *
 * Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net)
 */

#include <linux/string.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/device.h>
#include <linux/of_device.h>

#include <asm/prom.h>
#include <asm/oplib.h>

#include "pci_impl.h"
#include "pci_sun4v.h"

static int config_out_of_range(struct pci_pbm_info *pbm,
			       unsigned long bus,
			       unsigned long devfn,
			       unsigned long reg)
{
	if (bus < pbm->pci_first_busno ||
	    bus > pbm->pci_last_busno)
		return 1;
	return 0;
}

static void *sun4u_config_mkaddr(struct pci_pbm_info *pbm,
				 unsigned long bus,
				 unsigned long devfn,
				 unsigned long reg)
{
	unsigned long rbits = pbm->config_space_reg_bits;

	if (config_out_of_range(pbm, bus, devfn, reg))
		return NULL;

	reg = (reg & ((1 << rbits) - 1));
	devfn <<= rbits;
	bus <<= rbits + 8;

	return (void *)	(pbm->config_space | bus | devfn | reg);
}

/* At least on Sabre, it is necessary to access all PCI host controller
 * registers at their natural size, otherwise zeros are returned.
 * Strange but true, and I see no language in the UltraSPARC-IIi
 * programmer's manual that mentions this even indirectly.
 */
static int sun4u_read_pci_cfg_host(struct pci_pbm_info *pbm,
				   unsigned char bus, unsigned int devfn,
				   int where, int size, u32 *value)
{
	u32 tmp32, *addr;
	u16 tmp16;
	u8 tmp8;

	addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
	if (!addr)
		return PCIBIOS_SUCCESSFUL;

	switch (size) {
	case 1:
		if (where < 8) {
			unsigned long align = (unsigned long) addr;

			align &= ~1;
			pci_config_read16((u16 *)align, &tmp16);
			if (where & 1)
				*value = tmp16 >> 8;
			else
				*value = tmp16 & 0xff;
		} else {
			pci_config_read8((u8 *)addr, &tmp8);
			*value = (u32) tmp8;
		}
		break;

	case 2:
		if (where < 8) {
			pci_config_read16((u16 *)addr, &tmp16);
			*value = (u32) tmp16;
		} else {
			pci_config_read8((u8 *)addr, &tmp8);
			*value = (u32) tmp8;
			pci_config_read8(((u8 *)addr) + 1, &tmp8);
			*value |= ((u32) tmp8) << 8;
		}
		break;

	case 4:
		tmp32 = 0xffffffff;
		sun4u_read_pci_cfg_host(pbm, bus, devfn,
					where, 2, &tmp32);
		*value = tmp32;

		tmp32 = 0xffffffff;
		sun4u_read_pci_cfg_host(pbm, bus, devfn,
					where + 2, 2, &tmp32);
		*value |= tmp32 << 16;
		break;
	}
	return PCIBIOS_SUCCESSFUL;
}

static int sun4u_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
			      int where, int size, u32 *value)
{
	struct pci_pbm_info *pbm = bus_dev->sysdata;
	unsigned char bus = bus_dev->number;
	u32 *addr;
	u16 tmp16;
	u8 tmp8;

	switch (size) {
	case 1:
		*value = 0xff;
		break;
	case 2:
		*value = 0xffff;
		break;
	case 4:
		*value = 0xffffffff;
		break;
	}

	if (!bus_dev->number && !PCI_SLOT(devfn))
		return sun4u_read_pci_cfg_host(pbm, bus, devfn, where,
					       size, value);

	addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
	if (!addr)
		return PCIBIOS_SUCCESSFUL;

	switch (size) {
	case 1:
		pci_config_read8((u8 *)addr, &tmp8);
		*value = (u32) tmp8;
		break;

	case 2:
		if (where & 0x01) {
			printk("pci_read_config_word: misaligned reg [%x]\n",
			       where);
			return PCIBIOS_SUCCESSFUL;
		}
		pci_config_read16((u16 *)addr, &tmp16);
		*value = (u32) tmp16;
		break;

	case 4:
		if (where & 0x03) {
			printk("pci_read_config_dword: misaligned reg [%x]\n",
			       where);
			return PCIBIOS_SUCCESSFUL;
		}
		pci_config_read32(addr, value);
		break;
	}
	return PCIBIOS_SUCCESSFUL;
}

static int sun4u_write_pci_cfg_host(struct pci_pbm_info *pbm,
				    unsigned char bus, unsigned int devfn,
				    int where, int size, u32 value)
{
	u32 *addr;

	addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
	if (!addr)
		return PCIBIOS_SUCCESSFUL;

	switch (size) {
	case 1:
		if (where < 8) {
			unsigned long align = (unsigned long) addr;
			u16 tmp16;

			align &= ~1;
			pci_config_read16((u16 *)align, &tmp16);
			if (where & 1) {
				tmp16 &= 0x00ff;
				tmp16 |= value << 8;
			} else {
				tmp16 &= 0xff00;
				tmp16 |= value;
			}
			pci_config_write16((u16 *)align, tmp16);
		} else
			pci_config_write8((u8 *)addr, value);
		break;
	case 2:
		if (where < 8) {
			pci_config_write16((u16 *)addr, value);
		} else {
			pci_config_write8((u8 *)addr, value & 0xff);
			pci_config_write8(((u8 *)addr) + 1, value >> 8);
		}
		break;
	case 4:
		sun4u_write_pci_cfg_host(pbm, bus, devfn,
					 where, 2, value & 0xffff);
		sun4u_write_pci_cfg_host(pbm, bus, devfn,
					 where + 2, 2, value >> 16);
		break;
	}
	return PCIBIOS_SUCCESSFUL;
}

static int sun4u_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
			       int where, int size, u32 value)
{
	struct pci_pbm_info *pbm = bus_dev->sysdata;
	unsigned char bus = bus_dev->number;
	u32 *addr;

	if (!bus_dev->number && !PCI_SLOT(devfn))
		return sun4u_write_pci_cfg_host(pbm, bus, devfn, where,
						size, value);

	addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
	if (!addr)
		return PCIBIOS_SUCCESSFUL;

	switch (size) {
	case 1:
		pci_config_write8((u8 *)addr, value);
		break;

	case 2:
		if (where & 0x01) {
			printk("pci_write_config_word: misaligned reg [%x]\n",
			       where);
			return PCIBIOS_SUCCESSFUL;
		}
		pci_config_write16((u16 *)addr, value);
		break;

	case 4:
		if (where & 0x03) {
			printk("pci_write_config_dword: misaligned reg [%x]\n",
			       where);
			return PCIBIOS_SUCCESSFUL;
		}
		pci_config_write32(addr, value);
	}
	return PCIBIOS_SUCCESSFUL;
}

struct pci_ops sun4u_pci_ops = {
	.read =		sun4u_read_pci_cfg,
	.write =	sun4u_write_pci_cfg,
};

static int sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
			      int where, int size, u32 *value)
{
	struct pci_pbm_info *pbm = bus_dev->sysdata;
	u32 devhandle = pbm->devhandle;
	unsigned int bus = bus_dev->number;
	unsigned int device = PCI_SLOT(devfn);
	unsigned int func = PCI_FUNC(devfn);
	unsigned long ret;

	if (config_out_of_range(pbm, bus, devfn, where)) {
		ret = ~0UL;
	} else {
		ret = pci_sun4v_config_get(devhandle,
				HV_PCI_DEVICE_BUILD(bus, device, func),
				where, size);
	}
	switch (size) {
	case 1:
		*value = ret & 0xff;
		break;
	case 2:
		*value = ret & 0xffff;
		break;
	case 4:
		*value = ret & 0xffffffff;
		break;
	}


	return PCIBIOS_SUCCESSFUL;
}

static int sun4v_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
			       int where, int size, u32 value)
{
	struct pci_pbm_info *pbm = bus_dev->sysdata;
	u32 devhandle = pbm->devhandle;
	unsigned int bus = bus_dev->number;
	unsigned int device = PCI_SLOT(devfn);
	unsigned int func = PCI_FUNC(devfn);

	if (config_out_of_range(pbm, bus, devfn, where)) {
		/* Do nothing. */
	} else {
		/* We don't check for hypervisor errors here, but perhaps
		 * we should and influence our return value depending upon
		 * what kind of error is thrown.
		 */
		pci_sun4v_config_put(devhandle,
				     HV_PCI_DEVICE_BUILD(bus, device, func),
				     where, size, value);
	}
	return PCIBIOS_SUCCESSFUL;
}

struct pci_ops sun4v_pci_ops = {
	.read =		sun4v_read_pci_cfg,
	.write =	sun4v_write_pci_cfg,
};

void pci_get_pbm_props(struct pci_pbm_info *pbm)
{
	const u32 *val = of_get_property(pbm->op->dev.of_node, "bus-range", NULL);

	pbm->pci_first_busno = val[0];
	pbm->pci_last_busno = val[1];

	val = of_get_property(pbm->op->dev.of_node, "ino-bitmap", NULL);
	if (val) {
		pbm->ino_bitmap = (((u64)val[1] << 32UL) |
				   ((u64)val[0] <<  0UL));
	}
}

static void pci_register_legacy_regions(struct resource *io_res,
					struct resource *mem_res)
{
	struct resource *p;

	/* VGA Video RAM. */
	p = kzalloc(sizeof(*p), GFP_KERNEL);
	if (!p)
		return;

	p->name = "Video RAM area";
	p->start = mem_res->start + 0xa0000UL;
	p->end = p->start + 0x1ffffUL;
	p->flags = IORESOURCE_BUSY;
	request_resource(mem_res, p);

	p = kzalloc(sizeof(*p), GFP_KERNEL);
	if (!p)
		return;

	p->name = "System ROM";
	p->start = mem_res->start + 0xf0000UL;
	p->end = p->start + 0xffffUL;
	p->flags = IORESOURCE_BUSY;
	request_resource(mem_res, p);

	p = kzalloc(sizeof(*p), GFP_KERNEL);
	if (!p)
		return;

	p->name = "Video ROM";
	p->start = mem_res->start + 0xc0000UL;
	p->end = p->start + 0x7fffUL;
	p->flags = IORESOURCE_BUSY;
	request_resource(mem_res, p);
}

static void pci_register_iommu_region(struct pci_pbm_info *pbm)
{
	const u32 *vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma",
					  NULL);

	if (vdma) {
		struct resource *rp = kzalloc(sizeof(*rp), GFP_KERNEL);

		if (!rp) {
			pr_info("%s: Cannot allocate IOMMU resource.\n",
				pbm->name);
			return;
		}
		rp->name = "IOMMU";
		rp->start = pbm->mem_space.start + (unsigned long) vdma[0];
		rp->end = rp->start + (unsigned long) vdma[1] - 1UL;
		rp->flags = IORESOURCE_BUSY;
		if (request_resource(&pbm->mem_space, rp)) {
			pr_info("%s: Unable to request IOMMU resource.\n",
				pbm->name);
			kfree(rp);
		}
	}
}

void pci_determine_mem_io_space(struct pci_pbm_info *pbm)
{
	const struct linux_prom_pci_ranges *pbm_ranges;
	int i, saw_mem, saw_io;
	int num_pbm_ranges;

	saw_mem = saw_io = 0;
	pbm_ranges = of_get_property(pbm->op->dev.of_node, "ranges", &i);
	if (!pbm_ranges) {
		prom_printf("PCI: Fatal error, missing PBM ranges property "
			    " for %s\n",
			    pbm->name);
		prom_halt();
	}

	num_pbm_ranges = i / sizeof(*pbm_ranges);

	for (i = 0; i < num_pbm_ranges; i++) {
		const struct linux_prom_pci_ranges *pr = &pbm_ranges[i];
		unsigned long a, size;
		u32 parent_phys_hi, parent_phys_lo;
		u32 size_hi, size_lo;
		int type;

		parent_phys_hi = pr->parent_phys_hi;
		parent_phys_lo = pr->parent_phys_lo;
		if (tlb_type == hypervisor)
			parent_phys_hi &= 0x0fffffff;

		size_hi = pr->size_hi;
		size_lo = pr->size_lo;

		type = (pr->child_phys_hi >> 24) & 0x3;
		a = (((unsigned long)parent_phys_hi << 32UL) |
		     ((unsigned long)parent_phys_lo  <<  0UL));
		size = (((unsigned long)size_hi << 32UL) |
			((unsigned long)size_lo  <<  0UL));

		switch (type) {
		case 0:
			/* PCI config space, 16MB */
			pbm->config_space = a;
			break;

		case 1:
			/* 16-bit IO space, 16MB */
			pbm->io_space.start = a;
			pbm->io_space.end = a + size - 1UL;
			pbm->io_space.flags = IORESOURCE_IO;
			saw_io = 1;
			break;

		case 2:
			/* 32-bit MEM space, 2GB */
			pbm->mem_space.start = a;
			pbm->mem_space.end = a + size - 1UL;
			pbm->mem_space.flags = IORESOURCE_MEM;
			saw_mem = 1;
			break;

		case 3:
			/* XXX 64-bit MEM handling XXX */

		default:
			break;
		}
	}

	if (!saw_io || !saw_mem) {
		prom_printf("%s: Fatal error, missing %s PBM range.\n",
			    pbm->name,
			    (!saw_io ? "IO" : "MEM"));
		prom_halt();
	}

	printk("%s: PCI IO[%llx] MEM[%llx]\n",
	       pbm->name,
	       pbm->io_space.start,
	       pbm->mem_space.start);

	pbm->io_space.name = pbm->mem_space.name = pbm->name;

	request_resource(&ioport_resource, &pbm->io_space);
	request_resource(&iomem_resource, &pbm->mem_space);

	pci_register_legacy_regions(&pbm->io_space,
				    &pbm->mem_space);
	pci_register_iommu_region(pbm);
}

/* Generic helper routines for PCI error reporting. */
void pci_scan_for_target_abort(struct pci_pbm_info *pbm,
			       struct pci_bus *pbus)
{
	struct pci_dev *pdev;
	struct pci_bus *bus;

	list_for_each_entry(pdev, &pbus->devices, bus_list) {
		u16 status, error_bits;

		pci_read_config_word(pdev, PCI_STATUS, &status);
		error_bits =
			(status & (PCI_STATUS_SIG_TARGET_ABORT |
				   PCI_STATUS_REC_TARGET_ABORT));
		if (error_bits) {
			pci_write_config_word(pdev, PCI_STATUS, error_bits);
			printk("%s: Device %s saw Target Abort [%016x]\n",
			       pbm->name, pci_name(pdev), status);
		}
	}

	list_for_each_entry(bus, &pbus->children, node)
		pci_scan_for_target_abort(pbm, bus);
}

void pci_scan_for_master_abort(struct pci_pbm_info *pbm,
			       struct pci_bus *pbus)
{
	struct pci_dev *pdev;
	struct pci_bus *bus;

	list_for_each_entry(pdev, &pbus->devices, bus_list) {
		u16 status, error_bits;

		pci_read_config_word(pdev, PCI_STATUS, &status);
		error_bits =
			(status & (PCI_STATUS_REC_MASTER_ABORT));
		if (error_bits) {
			pci_write_config_word(pdev, PCI_STATUS, error_bits);
			printk("%s: Device %s received Master Abort [%016x]\n",
			       pbm->name, pci_name(pdev), status);
		}
	}

	list_for_each_entry(bus, &pbus->children, node)
		pci_scan_for_master_abort(pbm, bus);
}

void pci_scan_for_parity_error(struct pci_pbm_info *pbm,
			       struct pci_bus *pbus)
{
	struct pci_dev *pdev;
	struct pci_bus *bus;

	list_for_each_entry(pdev, &pbus->devices, bus_list) {
		u16 status, error_bits;

		pci_read_config_word(pdev, PCI_STATUS, &status);
		error_bits =
			(status & (PCI_STATUS_PARITY |
				   PCI_STATUS_DETECTED_PARITY));
		if (error_bits) {
			pci_write_config_word(pdev, PCI_STATUS, error_bits);
			printk("%s: Device %s saw Parity Error [%016x]\n",
			       pbm->name, pci_name(pdev), status);
		}
	}

	list_for_each_entry(bus, &pbus->children, node)
		pci_scan_for_parity_error(pbm, bus);
}
Commit	Line	Data
9fd8b647	1	/* pci_common.c: PCI controller common support.
1da177e4	2	*
9fd8b647	3	* Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net)
1da177e4 LT	4	*/
	5
	6	#include <linux/string.h>
	7	#include <linux/slab.h>
cf69eab2 FMDN	8	#include <linux/pci.h>
cf69eab2 FMDN	9	#include <linux/device.h>
764f2579	10	#include <linux/of_device.h>
1da177e4	11
de8d28b1	12	#include <asm/prom.h>
c57c2ffb	13	#include <asm/oplib.h>
de8d28b1 DM	14
de8d28b1 DM	15	#include "pci_impl.h"
ca3dd88e DM	16	#include "pci_sun4v.h"
	17
	18	static int config_out_of_range(struct pci_pbm_info *pbm,
	19	unsigned long bus,
	20	unsigned long devfn,
	21	unsigned long reg)
	22	{
	23	if (bus < pbm->pci_first_busno \|\|
	24	bus > pbm->pci_last_busno)
	25	return 1;
	26	return 0;
	27	}
	28
	29	static void sun4u_config_mkaddr(struct pci_pbm_info pbm,
	30	unsigned long bus,
	31	unsigned long devfn,
	32	unsigned long reg)
	33	{
	34	unsigned long rbits = pbm->config_space_reg_bits;
	35
	36	if (config_out_of_range(pbm, bus, devfn, reg))
	37	return NULL;
	38
	39	reg = (reg & ((1 << rbits) - 1));
	40	devfn <<= rbits;
	41	bus <<= rbits + 8;
	42
	43	return (void *) (pbm->config_space \| bus \| devfn \| reg);
	44	}
	45
a2d6ea01 DM	46	/* At least on Sabre, it is necessary to access all PCI host controller
	47	* registers at their natural size, otherwise zeros are returned.
	48	* Strange but true, and I see no language in the UltraSPARC-IIi
	49	* programmer's manual that mentions this even indirectly.
	50	*/
	51	static int sun4u_read_pci_cfg_host(struct pci_pbm_info *pbm,
	52	unsigned char bus, unsigned int devfn,
	53	int where, int size, u32 *value)
	54	{
	55	u32 tmp32, *addr;
	56	u16 tmp16;
	57	u8 tmp8;
	58
	59	addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
	60	if (!addr)
	61	return PCIBIOS_SUCCESSFUL;
	62
	63	switch (size) {
	64	case 1:
	65	if (where < 8) {
	66	unsigned long align = (unsigned long) addr;
	67
	68	align &= ~1;
	69	pci_config_read16((u16 *)align, &tmp16);
	70	if (where & 1)
	71	*value = tmp16 >> 8;
	72	else
	73	*value = tmp16 & 0xff;
	74	} else {
	75	pci_config_read8((u8 *)addr, &tmp8);
	76	*value = (u32) tmp8;
	77	}
	78	break;
	79
	80	case 2:
	81	if (where < 8) {
	82	pci_config_read16((u16 *)addr, &tmp16);
	83	*value = (u32) tmp16;
	84	} else {
	85	pci_config_read8((u8 *)addr, &tmp8);
	86	*value = (u32) tmp8;
	87	pci_config_read8(((u8 *)addr) + 1, &tmp8);
	88	*value \|= ((u32) tmp8) << 8;
	89	}
	90	break;
	91
	92	case 4:
	93	tmp32 = 0xffffffff;
	94	sun4u_read_pci_cfg_host(pbm, bus, devfn,
	95	where, 2, &tmp32);
	96	*value = tmp32;
	97
	98	tmp32 = 0xffffffff;
	99	sun4u_read_pci_cfg_host(pbm, bus, devfn,
	100	where + 2, 2, &tmp32);
	101	*value \|= tmp32 << 16;
	102	break;
	103	}
	104	return PCIBIOS_SUCCESSFUL;
	105	}
	106
ca3dd88e DM	107	static int sun4u_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
	108	int where, int size, u32 *value)
	109	{
	110	struct pci_pbm_info *pbm = bus_dev->sysdata;
	111	unsigned char bus = bus_dev->number;
	112	u32 *addr;
	113	u16 tmp16;
	114	u8 tmp8;
	115
ca3dd88e DM	116	switch (size) {
	117	case 1:
	118	*value = 0xff;
	119	break;
	120	case 2:
	121	*value = 0xffff;
	122	break;
	123	case 4:
	124	*value = 0xffffffff;
	125	break;
	126	}
	127
a2d6ea01 DM	128	if (!bus_dev->number && !PCI_SLOT(devfn))
	129	return sun4u_read_pci_cfg_host(pbm, bus, devfn, where,
	130	size, value);
	131
ca3dd88e DM	132	addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
	133	if (!addr)
	134	return PCIBIOS_SUCCESSFUL;
	135
	136	switch (size) {
	137	case 1:
	138	pci_config_read8((u8 *)addr, &tmp8);
	139	*value = (u32) tmp8;
	140	break;
	141
	142	case 2:
	143	if (where & 0x01) {
	144	printk("pci_read_config_word: misaligned reg [%x]\n",
	145	where);
	146	return PCIBIOS_SUCCESSFUL;
	147	}
	148	pci_config_read16((u16 *)addr, &tmp16);
	149	*value = (u32) tmp16;
	150	break;
	151
	152	case 4:
	153	if (where & 0x03) {
	154	printk("pci_read_config_dword: misaligned reg [%x]\n",
	155	where);
	156	return PCIBIOS_SUCCESSFUL;
	157	}
	158	pci_config_read32(addr, value);
	159	break;
	160	}
	161	return PCIBIOS_SUCCESSFUL;
	162	}
	163
a2d6ea01 DM	164	static int sun4u_write_pci_cfg_host(struct pci_pbm_info *pbm,
	165	unsigned char bus, unsigned int devfn,
	166	int where, int size, u32 value)
	167	{
	168	u32 *addr;
	169
	170	addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
	171	if (!addr)
	172	return PCIBIOS_SUCCESSFUL;
	173
	174	switch (size) {
	175	case 1:
	176	if (where < 8) {
	177	unsigned long align = (unsigned long) addr;
	178	u16 tmp16;
	179
	180	align &= ~1;
	181	pci_config_read16((u16 *)align, &tmp16);
	182	if (where & 1) {
	183	tmp16 &= 0x00ff;
	184	tmp16 \|= value << 8;
	185	} else {
	186	tmp16 &= 0xff00;
	187	tmp16 \|= value;
	188	}
	189	pci_config_write16((u16 *)align, tmp16);
	190	} else
	191	pci_config_write8((u8 *)addr, value);
	192	break;
	193	case 2:
	194	if (where < 8) {
	195	pci_config_write16((u16 *)addr, value);
	196	} else {
	197	pci_config_write8((u8 *)addr, value & 0xff);
	198	pci_config_write8(((u8 *)addr) + 1, value >> 8);
	199	}
	200	break;
	201	case 4:
	202	sun4u_write_pci_cfg_host(pbm, bus, devfn,
	203	where, 2, value & 0xffff);
	204	sun4u_write_pci_cfg_host(pbm, bus, devfn,
	205	where + 2, 2, value >> 16);
	206	break;
	207	}
	208	return PCIBIOS_SUCCESSFUL;
	209	}
	210
ca3dd88e DM	211	static int sun4u_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
	212	int where, int size, u32 value)
	213	{
	214	struct pci_pbm_info *pbm = bus_dev->sysdata;
	215	unsigned char bus = bus_dev->number;
	216	u32 *addr;
	217
a2d6ea01 DM	218	if (!bus_dev->number && !PCI_SLOT(devfn))
	219	return sun4u_write_pci_cfg_host(pbm, bus, devfn, where,
	220	size, value);
	221
ca3dd88e DM	222	addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
	223	if (!addr)
	224	return PCIBIOS_SUCCESSFUL;
	225
	226	switch (size) {
	227	case 1:
	228	pci_config_write8((u8 *)addr, value);
	229	break;
	230
	231	case 2:
	232	if (where & 0x01) {
	233	printk("pci_write_config_word: misaligned reg [%x]\n",
	234	where);
	235	return PCIBIOS_SUCCESSFUL;
	236	}
	237	pci_config_write16((u16 *)addr, value);
	238	break;
	239
	240	case 4:
	241	if (where & 0x03) {
	242	printk("pci_write_config_dword: misaligned reg [%x]\n",
	243	where);
	244	return PCIBIOS_SUCCESSFUL;
	245	}
	246	pci_config_write32(addr, value);
	247	}
	248	return PCIBIOS_SUCCESSFUL;
	249	}
	250
	251	struct pci_ops sun4u_pci_ops = {
	252	.read = sun4u_read_pci_cfg,
	253	.write = sun4u_write_pci_cfg,
	254	};
	255
	256	static int sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
	257	int where, int size, u32 *value)
	258	{
	259	struct pci_pbm_info *pbm = bus_dev->sysdata;
	260	u32 devhandle = pbm->devhandle;
	261	unsigned int bus = bus_dev->number;
	262	unsigned int device = PCI_SLOT(devfn);
	263	unsigned int func = PCI_FUNC(devfn);
	264	unsigned long ret;
	265
ca3dd88e DM	266	if (config_out_of_range(pbm, bus, devfn, where)) {
	267	ret = ~0UL;
	268	} else {
	269	ret = pci_sun4v_config_get(devhandle,
	270	HV_PCI_DEVICE_BUILD(bus, device, func),
	271	where, size);
	272	}
	273	switch (size) {
	274	case 1:
	275	*value = ret & 0xff;
	276	break;
	277	case 2:
	278	*value = ret & 0xffff;
	279	break;
	280	case 4:
	281	*value = ret & 0xffffffff;
	282	break;
6cb79b3f	283	}
ca3dd88e DM	284
	285
	286	return PCIBIOS_SUCCESSFUL;
	287	}
	288
	289	static int sun4v_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
	290	int where, int size, u32 value)
	291	{
	292	struct pci_pbm_info *pbm = bus_dev->sysdata;
	293	u32 devhandle = pbm->devhandle;
	294	unsigned int bus = bus_dev->number;
	295	unsigned int device = PCI_SLOT(devfn);
	296	unsigned int func = PCI_FUNC(devfn);
ca3dd88e	297
ca3dd88e DM	298	if (config_out_of_range(pbm, bus, devfn, where)) {
	299	/* Do nothing. */
	300	} else {
c6fee081 DM	301	/* We don't check for hypervisor errors here, but perhaps
	302	* we should and influence our return value depending upon
	303	* what kind of error is thrown.
	304	*/
	305	pci_sun4v_config_put(devhandle,
	306	HV_PCI_DEVICE_BUILD(bus, device, func),
	307	where, size, value);
ca3dd88e DM	308	}
	309	return PCIBIOS_SUCCESSFUL;
	310	}
	311
	312	struct pci_ops sun4v_pci_ops = {
	313	.read = sun4v_read_pci_cfg,
	314	.write = sun4v_write_pci_cfg,
	315	};
1da177e4	316
cfa0652c DM	317	void pci_get_pbm_props(struct pci_pbm_info *pbm)
cfa0652c DM	318	{
61c7a080	319	const u32 *val = of_get_property(pbm->op->dev.of_node, "bus-range", NULL);
cfa0652c DM	320
	321	pbm->pci_first_busno = val[0];
	322	pbm->pci_last_busno = val[1];
	323
61c7a080	324	val = of_get_property(pbm->op->dev.of_node, "ino-bitmap", NULL);
cfa0652c DM	325	if (val) {
	326	pbm->ino_bitmap = (((u64)val[1] << 32UL) \|
	327	((u64)val[0] << 0UL));
	328	}
	329	}
	330
9fd8b647 DM	331	static void pci_register_legacy_regions(struct resource *io_res,
9fd8b647 DM	332	struct resource *mem_res)
1da177e4 LT	333	{
	334	struct resource *p;
	335
	336	/* VGA Video RAM. */
9132983a	337	p = kzalloc(sizeof(*p), GFP_KERNEL);
1da177e4 LT	338	if (!p)
	339	return;
	340
1da177e4 LT	341	p->name = "Video RAM area";
	342	p->start = mem_res->start + 0xa0000UL;
	343	p->end = p->start + 0x1ffffUL;
	344	p->flags = IORESOURCE_BUSY;
	345	request_resource(mem_res, p);
	346
9132983a	347	p = kzalloc(sizeof(*p), GFP_KERNEL);
1da177e4 LT	348	if (!p)
	349	return;
	350
1da177e4 LT	351	p->name = "System ROM";
	352	p->start = mem_res->start + 0xf0000UL;
	353	p->end = p->start + 0xffffUL;
	354	p->flags = IORESOURCE_BUSY;
	355	request_resource(mem_res, p);
	356
9132983a	357	p = kzalloc(sizeof(*p), GFP_KERNEL);
1da177e4 LT	358	if (!p)
	359	return;
	360
1da177e4 LT	361	p->name = "Video ROM";
	362	p->start = mem_res->start + 0xc0000UL;
	363	p->end = p->start + 0x7fffUL;
	364	p->flags = IORESOURCE_BUSY;
	365	request_resource(mem_res, p);
	366	}
	367
9fd8b647 DM	368	static void pci_register_iommu_region(struct pci_pbm_info *pbm)
9fd8b647 DM	369	{
61c7a080 GL	370	const u32 *vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma",
61c7a080 GL	371	NULL);
9fd8b647 DM	372
9fd8b647 DM	373	if (vdma) {
192d7a46	374	struct resource rp = kzalloc(sizeof(rp), GFP_KERNEL);
9fd8b647 DM	375
9fd8b647 DM	376	if (!rp) {
e182c77c DM	377	pr_info("%s: Cannot allocate IOMMU resource.\n",
	378	pbm->name);
	379	return;
9fd8b647 DM	380	}
	381	rp->name = "IOMMU";
	382	rp->start = pbm->mem_space.start + (unsigned long) vdma[0];
	383	rp->end = rp->start + (unsigned long) vdma[1] - 1UL;
	384	rp->flags = IORESOURCE_BUSY;
e182c77c DM	385	if (request_resource(&pbm->mem_space, rp)) {
	386	pr_info("%s: Unable to request IOMMU resource.\n",
	387	pbm->name);
	388	kfree(rp);
	389	}
9fd8b647 DM	390	}
	391	}
	392
	393	void pci_determine_mem_io_space(struct pci_pbm_info *pbm)
	394	{
a165b420	395	const struct linux_prom_pci_ranges *pbm_ranges;
9fd8b647	396	int i, saw_mem, saw_io;
3487a1f9	397	int num_pbm_ranges;
9fd8b647 DM	398
9fd8b647 DM	399	saw_mem = saw_io = 0;
61c7a080	400	pbm_ranges = of_get_property(pbm->op->dev.of_node, "ranges", &i);
4209ab09 DM	401	if (!pbm_ranges) {
	402	prom_printf("PCI: Fatal error, missing PBM ranges property "
	403	" for %s\n",
	404	pbm->name);
	405	prom_halt();
	406	}
	407
3487a1f9 DM	408	num_pbm_ranges = i / sizeof(*pbm_ranges);
	409
	410	for (i = 0; i < num_pbm_ranges; i++) {
a165b420	411	const struct linux_prom_pci_ranges *pr = &pbm_ranges[i];
56f5c0bd	412	unsigned long a, size;
3487a1f9	413	u32 parent_phys_hi, parent_phys_lo;
56f5c0bd	414	u32 size_hi, size_lo;
9fd8b647 DM	415	int type;
9fd8b647 DM	416
3487a1f9 DM	417	parent_phys_hi = pr->parent_phys_hi;
	418	parent_phys_lo = pr->parent_phys_lo;
	419	if (tlb_type == hypervisor)
	420	parent_phys_hi &= 0x0fffffff;
	421
56f5c0bd DM	422	size_hi = pr->size_hi;
	423	size_lo = pr->size_lo;
	424
9fd8b647	425	type = (pr->child_phys_hi >> 24) & 0x3;
3487a1f9 DM	426	a = (((unsigned long)parent_phys_hi << 32UL) \|
3487a1f9 DM	427	((unsigned long)parent_phys_lo << 0UL));
56f5c0bd DM	428	size = (((unsigned long)size_hi << 32UL) \|
56f5c0bd DM	429	((unsigned long)size_lo << 0UL));
9fd8b647 DM	430
	431	switch (type) {
	432	case 0:
	433	/* PCI config space, 16MB */
	434	pbm->config_space = a;
	435	break;
	436
	437	case 1:
	438	/* 16-bit IO space, 16MB */
	439	pbm->io_space.start = a;
56f5c0bd	440	pbm->io_space.end = a + size - 1UL;
9fd8b647 DM	441	pbm->io_space.flags = IORESOURCE_IO;
	442	saw_io = 1;
	443	break;
	444
	445	case 2:
	446	/* 32-bit MEM space, 2GB */
	447	pbm->mem_space.start = a;
56f5c0bd	448	pbm->mem_space.end = a + size - 1UL;
9fd8b647 DM	449	pbm->mem_space.flags = IORESOURCE_MEM;
	450	saw_mem = 1;
	451	break;
	452
	453	case 3:
	454	/* XXX 64-bit MEM handling XXX */
	455
	456	default:
	457	break;
6cb79b3f	458	}
9fd8b647 DM	459	}
	460
	461	if (!saw_io \|\| !saw_mem) {
	462	prom_printf("%s: Fatal error, missing %s PBM range.\n",
	463	pbm->name,
	464	(!saw_io ? "IO" : "MEM"));
	465	prom_halt();
	466	}
	467
90181136	468	printk("%s: PCI IO[%llx] MEM[%llx]\n",
9fd8b647 DM	469	pbm->name,
	470	pbm->io_space.start,
	471	pbm->mem_space.start);
	472
	473	pbm->io_space.name = pbm->mem_space.name = pbm->name;
	474
	475	request_resource(&ioport_resource, &pbm->io_space);
	476	request_resource(&iomem_resource, &pbm->mem_space);
	477
	478	pci_register_legacy_regions(&pbm->io_space,
	479	&pbm->mem_space);
	480	pci_register_iommu_region(pbm);
	481	}
	482
1da177e4	483	/* Generic helper routines for PCI error reporting. */
6c108f12	484	void pci_scan_for_target_abort(struct pci_pbm_info *pbm,
1da177e4 LT	485	struct pci_bus *pbus)
	486	{
	487	struct pci_dev *pdev;
	488	struct pci_bus *bus;
	489
	490	list_for_each_entry(pdev, &pbus->devices, bus_list) {
	491	u16 status, error_bits;
	492
	493	pci_read_config_word(pdev, PCI_STATUS, &status);
	494	error_bits =
	495	(status & (PCI_STATUS_SIG_TARGET_ABORT \|
	496	PCI_STATUS_REC_TARGET_ABORT));
	497	if (error_bits) {
	498	pci_write_config_word(pdev, PCI_STATUS, error_bits);
6c108f12 DM	499	printk("%s: Device %s saw Target Abort [%016x]\n",
6c108f12 DM	500	pbm->name, pci_name(pdev), status);
1da177e4 LT	501	}
	502	}
	503
	504	list_for_each_entry(bus, &pbus->children, node)
6c108f12	505	pci_scan_for_target_abort(pbm, bus);
1da177e4 LT	506	}
1da177e4 LT	507
6c108f12	508	void pci_scan_for_master_abort(struct pci_pbm_info *pbm,
1da177e4 LT	509	struct pci_bus *pbus)
	510	{
	511	struct pci_dev *pdev;
	512	struct pci_bus *bus;
	513
	514	list_for_each_entry(pdev, &pbus->devices, bus_list) {
	515	u16 status, error_bits;
	516
	517	pci_read_config_word(pdev, PCI_STATUS, &status);
	518	error_bits =
	519	(status & (PCI_STATUS_REC_MASTER_ABORT));
	520	if (error_bits) {
	521	pci_write_config_word(pdev, PCI_STATUS, error_bits);
6c108f12 DM	522	printk("%s: Device %s received Master Abort [%016x]\n",
6c108f12 DM	523	pbm->name, pci_name(pdev), status);
1da177e4 LT	524	}
	525	}
	526
	527	list_for_each_entry(bus, &pbus->children, node)
6c108f12	528	pci_scan_for_master_abort(pbm, bus);
1da177e4 LT	529	}
1da177e4 LT	530
6c108f12	531	void pci_scan_for_parity_error(struct pci_pbm_info *pbm,
1da177e4 LT	532	struct pci_bus *pbus)
	533	{
	534	struct pci_dev *pdev;
	535	struct pci_bus *bus;
	536
	537	list_for_each_entry(pdev, &pbus->devices, bus_list) {
	538	u16 status, error_bits;
	539
	540	pci_read_config_word(pdev, PCI_STATUS, &status);
	541	error_bits =
	542	(status & (PCI_STATUS_PARITY \|
	543	PCI_STATUS_DETECTED_PARITY));
	544	if (error_bits) {
	545	pci_write_config_word(pdev, PCI_STATUS, error_bits);
6c108f12 DM	546	printk("%s: Device %s saw Parity Error [%016x]\n",
6c108f12 DM	547	pbm->name, pci_name(pdev), status);
1da177e4 LT	548	}
	549	}
	550
	551	list_for_each_entry(bus, &pbus->children, node)
6c108f12	552	pci_scan_for_parity_error(pbm, bus);
1da177e4	553	}