Commit | Line | Data |
---|---|---|
a2fb23af | 1 | /* pci.c: UltraSparc PCI controller support. |
1da177e4 LT |
2 | * |
3 | * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com) | |
4 | * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be) | |
5 | * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz) | |
a2fb23af DM |
6 | * |
7 | * OF tree based PCI bus probing taken from the PowerPC port | |
8 | * with minor modifications, see there for credits. | |
1da177e4 LT |
9 | */ |
10 | ||
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/kernel.h> | |
13 | #include <linux/string.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/capability.h> | |
16 | #include <linux/errno.h> | |
c57c2ffb | 17 | #include <linux/pci.h> |
35a17eb6 DM |
18 | #include <linux/msi.h> |
19 | #include <linux/irq.h> | |
1da177e4 | 20 | #include <linux/init.h> |
356d1647 DM |
21 | #include <linux/of.h> |
22 | #include <linux/of_device.h> | |
1da177e4 LT |
23 | |
24 | #include <asm/uaccess.h> | |
1da177e4 LT |
25 | #include <asm/pgtable.h> |
26 | #include <asm/irq.h> | |
e87dc350 | 27 | #include <asm/prom.h> |
01f94c4a | 28 | #include <asm/apb.h> |
1da177e4 | 29 | |
1e8a8cc5 DM |
30 | #include "pci_impl.h" |
31 | ||
1da177e4 | 32 | /* List of all PCI controllers found in the system. */ |
34768bc8 | 33 | struct pci_pbm_info *pci_pbm_root = NULL; |
1da177e4 | 34 | |
6c108f12 DM |
35 | /* Each PBM found gets a unique index. */ |
36 | int pci_num_pbms = 0; | |
1da177e4 | 37 | |
1da177e4 LT |
38 | volatile int pci_poke_in_progress; |
39 | volatile int pci_poke_cpu = -1; | |
40 | volatile int pci_poke_faulted; | |
41 | ||
42 | static DEFINE_SPINLOCK(pci_poke_lock); | |
43 | ||
44 | void pci_config_read8(u8 *addr, u8 *ret) | |
45 | { | |
46 | unsigned long flags; | |
47 | u8 byte; | |
48 | ||
49 | spin_lock_irqsave(&pci_poke_lock, flags); | |
50 | pci_poke_cpu = smp_processor_id(); | |
51 | pci_poke_in_progress = 1; | |
52 | pci_poke_faulted = 0; | |
53 | __asm__ __volatile__("membar #Sync\n\t" | |
54 | "lduba [%1] %2, %0\n\t" | |
55 | "membar #Sync" | |
56 | : "=r" (byte) | |
57 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
58 | : "memory"); | |
59 | pci_poke_in_progress = 0; | |
60 | pci_poke_cpu = -1; | |
61 | if (!pci_poke_faulted) | |
62 | *ret = byte; | |
63 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
64 | } | |
65 | ||
66 | void pci_config_read16(u16 *addr, u16 *ret) | |
67 | { | |
68 | unsigned long flags; | |
69 | u16 word; | |
70 | ||
71 | spin_lock_irqsave(&pci_poke_lock, flags); | |
72 | pci_poke_cpu = smp_processor_id(); | |
73 | pci_poke_in_progress = 1; | |
74 | pci_poke_faulted = 0; | |
75 | __asm__ __volatile__("membar #Sync\n\t" | |
76 | "lduha [%1] %2, %0\n\t" | |
77 | "membar #Sync" | |
78 | : "=r" (word) | |
79 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
80 | : "memory"); | |
81 | pci_poke_in_progress = 0; | |
82 | pci_poke_cpu = -1; | |
83 | if (!pci_poke_faulted) | |
84 | *ret = word; | |
85 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
86 | } | |
87 | ||
88 | void pci_config_read32(u32 *addr, u32 *ret) | |
89 | { | |
90 | unsigned long flags; | |
91 | u32 dword; | |
92 | ||
93 | spin_lock_irqsave(&pci_poke_lock, flags); | |
94 | pci_poke_cpu = smp_processor_id(); | |
95 | pci_poke_in_progress = 1; | |
96 | pci_poke_faulted = 0; | |
97 | __asm__ __volatile__("membar #Sync\n\t" | |
98 | "lduwa [%1] %2, %0\n\t" | |
99 | "membar #Sync" | |
100 | : "=r" (dword) | |
101 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
102 | : "memory"); | |
103 | pci_poke_in_progress = 0; | |
104 | pci_poke_cpu = -1; | |
105 | if (!pci_poke_faulted) | |
106 | *ret = dword; | |
107 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
108 | } | |
109 | ||
110 | void pci_config_write8(u8 *addr, u8 val) | |
111 | { | |
112 | unsigned long flags; | |
113 | ||
114 | spin_lock_irqsave(&pci_poke_lock, flags); | |
115 | pci_poke_cpu = smp_processor_id(); | |
116 | pci_poke_in_progress = 1; | |
117 | pci_poke_faulted = 0; | |
118 | __asm__ __volatile__("membar #Sync\n\t" | |
119 | "stba %0, [%1] %2\n\t" | |
120 | "membar #Sync" | |
121 | : /* no outputs */ | |
122 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
123 | : "memory"); | |
124 | pci_poke_in_progress = 0; | |
125 | pci_poke_cpu = -1; | |
126 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
127 | } | |
128 | ||
129 | void pci_config_write16(u16 *addr, u16 val) | |
130 | { | |
131 | unsigned long flags; | |
132 | ||
133 | spin_lock_irqsave(&pci_poke_lock, flags); | |
134 | pci_poke_cpu = smp_processor_id(); | |
135 | pci_poke_in_progress = 1; | |
136 | pci_poke_faulted = 0; | |
137 | __asm__ __volatile__("membar #Sync\n\t" | |
138 | "stha %0, [%1] %2\n\t" | |
139 | "membar #Sync" | |
140 | : /* no outputs */ | |
141 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
142 | : "memory"); | |
143 | pci_poke_in_progress = 0; | |
144 | pci_poke_cpu = -1; | |
145 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
146 | } | |
147 | ||
148 | void pci_config_write32(u32 *addr, u32 val) | |
149 | { | |
150 | unsigned long flags; | |
151 | ||
152 | spin_lock_irqsave(&pci_poke_lock, flags); | |
153 | pci_poke_cpu = smp_processor_id(); | |
154 | pci_poke_in_progress = 1; | |
155 | pci_poke_faulted = 0; | |
156 | __asm__ __volatile__("membar #Sync\n\t" | |
157 | "stwa %0, [%1] %2\n\t" | |
158 | "membar #Sync" | |
159 | : /* no outputs */ | |
160 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
161 | : "memory"); | |
162 | pci_poke_in_progress = 0; | |
163 | pci_poke_cpu = -1; | |
164 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
165 | } | |
166 | ||
5840fc66 DM |
167 | static int ofpci_verbose; |
168 | ||
169 | static int __init ofpci_debug(char *str) | |
170 | { | |
171 | int val = 0; | |
172 | ||
173 | get_option(&str, &val); | |
174 | if (val) | |
175 | ofpci_verbose = 1; | |
176 | return 1; | |
177 | } | |
178 | ||
179 | __setup("ofpci_debug=", ofpci_debug); | |
180 | ||
a2fb23af DM |
181 | static unsigned long pci_parse_of_flags(u32 addr0) |
182 | { | |
183 | unsigned long flags = 0; | |
184 | ||
185 | if (addr0 & 0x02000000) { | |
186 | flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY; | |
187 | flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64; | |
188 | flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M; | |
189 | if (addr0 & 0x40000000) | |
190 | flags |= IORESOURCE_PREFETCH | |
191 | | PCI_BASE_ADDRESS_MEM_PREFETCH; | |
192 | } else if (addr0 & 0x01000000) | |
193 | flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO; | |
194 | return flags; | |
195 | } | |
196 | ||
197 | /* The of_device layer has translated all of the assigned-address properties | |
198 | * into physical address resources, we only have to figure out the register | |
199 | * mapping. | |
200 | */ | |
201 | static void pci_parse_of_addrs(struct of_device *op, | |
202 | struct device_node *node, | |
203 | struct pci_dev *dev) | |
204 | { | |
205 | struct resource *op_res; | |
206 | const u32 *addrs; | |
207 | int proplen; | |
208 | ||
209 | addrs = of_get_property(node, "assigned-addresses", &proplen); | |
210 | if (!addrs) | |
211 | return; | |
5840fc66 DM |
212 | if (ofpci_verbose) |
213 | printk(" parse addresses (%d bytes) @ %p\n", | |
214 | proplen, addrs); | |
a2fb23af DM |
215 | op_res = &op->resource[0]; |
216 | for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) { | |
217 | struct resource *res; | |
218 | unsigned long flags; | |
219 | int i; | |
220 | ||
221 | flags = pci_parse_of_flags(addrs[0]); | |
222 | if (!flags) | |
223 | continue; | |
224 | i = addrs[0] & 0xff; | |
5840fc66 | 225 | if (ofpci_verbose) |
90181136 | 226 | printk(" start: %llx, end: %llx, i: %x\n", |
5840fc66 | 227 | op_res->start, op_res->end, i); |
a2fb23af DM |
228 | |
229 | if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) { | |
230 | res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2]; | |
231 | } else if (i == dev->rom_base_reg) { | |
232 | res = &dev->resource[PCI_ROM_RESOURCE]; | |
233 | flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE; | |
234 | } else { | |
235 | printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i); | |
236 | continue; | |
237 | } | |
238 | res->start = op_res->start; | |
239 | res->end = op_res->end; | |
240 | res->flags = flags; | |
241 | res->name = pci_name(dev); | |
242 | } | |
243 | } | |
244 | ||
77d10d0e DM |
245 | static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm, |
246 | struct device_node *node, | |
247 | struct pci_bus *bus, int devfn) | |
a2fb23af DM |
248 | { |
249 | struct dev_archdata *sd; | |
172d2d00 | 250 | struct pci_slot *slot; |
ae05f87e | 251 | struct of_device *op; |
a2fb23af DM |
252 | struct pci_dev *dev; |
253 | const char *type; | |
01f94c4a | 254 | u32 class; |
a2fb23af | 255 | |
26e6385f | 256 | dev = alloc_pci_dev(); |
a2fb23af DM |
257 | if (!dev) |
258 | return NULL; | |
259 | ||
260 | sd = &dev->dev.archdata; | |
261 | sd->iommu = pbm->iommu; | |
262 | sd->stc = &pbm->stc; | |
263 | sd->host_controller = pbm; | |
264 | sd->prom_node = node; | |
ae05f87e | 265 | sd->op = op = of_find_device_by_node(node); |
c1b1a5f1 | 266 | sd->numa_node = pbm->numa_node; |
a2fb23af | 267 | |
ae05f87e | 268 | sd = &op->dev.archdata; |
ad7ad57c DM |
269 | sd->iommu = pbm->iommu; |
270 | sd->stc = &pbm->stc; | |
c1b1a5f1 | 271 | sd->numa_node = pbm->numa_node; |
ad7ad57c | 272 | |
ae05f87e DM |
273 | if (!strcmp(node->name, "ebus")) |
274 | of_propagate_archdata(op); | |
275 | ||
a2fb23af DM |
276 | type = of_get_property(node, "device_type", NULL); |
277 | if (type == NULL) | |
278 | type = ""; | |
279 | ||
5840fc66 DM |
280 | if (ofpci_verbose) |
281 | printk(" create device, devfn: %x, type: %s\n", | |
282 | devfn, type); | |
a2fb23af DM |
283 | |
284 | dev->bus = bus; | |
285 | dev->sysdata = node; | |
286 | dev->dev.parent = bus->bridge; | |
287 | dev->dev.bus = &pci_bus_type; | |
288 | dev->devfn = devfn; | |
289 | dev->multifunction = 0; /* maybe a lie? */ | |
172d2d00 DM |
290 | set_pcie_port_type(dev); |
291 | ||
292 | list_for_each_entry(slot, &dev->bus->slots, list) | |
293 | if (PCI_SLOT(dev->devfn) == slot->number) | |
294 | dev->slot = slot; | |
a2fb23af | 295 | |
c26d3c01 DM |
296 | dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff); |
297 | dev->device = of_getintprop_default(node, "device-id", 0xffff); | |
298 | dev->subsystem_vendor = | |
299 | of_getintprop_default(node, "subsystem-vendor-id", 0); | |
300 | dev->subsystem_device = | |
301 | of_getintprop_default(node, "subsystem-id", 0); | |
302 | ||
303 | dev->cfg_size = pci_cfg_space_size(dev); | |
304 | ||
305 | /* We can't actually use the firmware value, we have | |
306 | * to read what is in the register right now. One | |
307 | * reason is that in the case of IDE interfaces the | |
308 | * firmware can sample the value before the the IDE | |
309 | * interface is programmed into native mode. | |
310 | */ | |
311 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); | |
312 | dev->class = class >> 8; | |
313 | dev->revision = class & 0xff; | |
314 | ||
2222c313 | 315 | dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus), |
c26d3c01 | 316 | dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); |
28f57e77 | 317 | |
5840fc66 DM |
318 | if (ofpci_verbose) |
319 | printk(" class: 0x%x device name: %s\n", | |
320 | dev->class, pci_name(dev)); | |
a2fb23af | 321 | |
861fe906 DM |
322 | /* I have seen IDE devices which will not respond to |
323 | * the bmdma simplex check reads if bus mastering is | |
324 | * disabled. | |
325 | */ | |
326 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) | |
327 | pci_set_master(dev); | |
328 | ||
a2fb23af DM |
329 | dev->current_state = 4; /* unknown power state */ |
330 | dev->error_state = pci_channel_io_normal; | |
172d2d00 | 331 | dev->dma_mask = 0xffffffff; |
a2fb23af | 332 | |
44b50e5a | 333 | if (!strcmp(node->name, "pci")) { |
c26d3c01 | 334 | /* a PCI-PCI bridge */ |
a2fb23af DM |
335 | dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; |
336 | dev->rom_base_reg = PCI_ROM_ADDRESS1; | |
c26d3c01 DM |
337 | } else if (!strcmp(type, "cardbus")) { |
338 | dev->hdr_type = PCI_HEADER_TYPE_CARDBUS; | |
a2fb23af | 339 | } else { |
c26d3c01 DM |
340 | dev->hdr_type = PCI_HEADER_TYPE_NORMAL; |
341 | dev->rom_base_reg = PCI_ROM_ADDRESS; | |
a2fb23af | 342 | |
c26d3c01 DM |
343 | dev->irq = sd->op->irqs[0]; |
344 | if (dev->irq == 0xffffffff) | |
345 | dev->irq = PCI_IRQ_NONE; | |
a2fb23af | 346 | } |
c26d3c01 | 347 | |
a2fb23af DM |
348 | pci_parse_of_addrs(sd->op, node, dev); |
349 | ||
5840fc66 DM |
350 | if (ofpci_verbose) |
351 | printk(" adding to system ...\n"); | |
a2fb23af DM |
352 | |
353 | pci_device_add(dev, bus); | |
354 | ||
355 | return dev; | |
356 | } | |
357 | ||
a6009dda | 358 | static void __devinit apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p) |
01f94c4a DM |
359 | { |
360 | u32 idx, first, last; | |
361 | ||
362 | first = 8; | |
363 | last = 0; | |
364 | for (idx = 0; idx < 8; idx++) { | |
365 | if ((map & (1 << idx)) != 0) { | |
366 | if (first > idx) | |
367 | first = idx; | |
368 | if (last < idx) | |
369 | last = idx; | |
370 | } | |
371 | } | |
372 | ||
373 | *first_p = first; | |
374 | *last_p = last; | |
375 | } | |
376 | ||
f16537ba DM |
377 | static void pci_resource_adjust(struct resource *res, |
378 | struct resource *root) | |
0bae5f81 DM |
379 | { |
380 | res->start += root->start; | |
381 | res->end += root->start; | |
382 | } | |
383 | ||
8c2786cf DM |
384 | /* For PCI bus devices which lack a 'ranges' property we interrogate |
385 | * the config space values to set the resources, just like the generic | |
386 | * Linux PCI probing code does. | |
387 | */ | |
388 | static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev, | |
389 | struct pci_bus *bus, | |
390 | struct pci_pbm_info *pbm) | |
391 | { | |
392 | struct resource *res; | |
393 | u8 io_base_lo, io_limit_lo; | |
394 | u16 mem_base_lo, mem_limit_lo; | |
395 | unsigned long base, limit; | |
396 | ||
397 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); | |
398 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); | |
399 | base = (io_base_lo & PCI_IO_RANGE_MASK) << 8; | |
400 | limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8; | |
401 | ||
402 | if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { | |
403 | u16 io_base_hi, io_limit_hi; | |
404 | ||
405 | pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); | |
406 | pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); | |
407 | base |= (io_base_hi << 16); | |
408 | limit |= (io_limit_hi << 16); | |
409 | } | |
410 | ||
411 | res = bus->resource[0]; | |
412 | if (base <= limit) { | |
413 | res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; | |
414 | if (!res->start) | |
415 | res->start = base; | |
416 | if (!res->end) | |
417 | res->end = limit + 0xfff; | |
418 | pci_resource_adjust(res, &pbm->io_space); | |
419 | } | |
420 | ||
421 | pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); | |
422 | pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); | |
423 | base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
424 | limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
425 | ||
426 | res = bus->resource[1]; | |
427 | if (base <= limit) { | |
428 | res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | | |
429 | IORESOURCE_MEM); | |
430 | res->start = base; | |
431 | res->end = limit + 0xfffff; | |
432 | pci_resource_adjust(res, &pbm->mem_space); | |
433 | } | |
434 | ||
435 | pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); | |
436 | pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); | |
437 | base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; | |
438 | limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; | |
439 | ||
440 | if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { | |
441 | u32 mem_base_hi, mem_limit_hi; | |
442 | ||
443 | pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); | |
444 | pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); | |
445 | ||
446 | /* | |
447 | * Some bridges set the base > limit by default, and some | |
448 | * (broken) BIOSes do not initialize them. If we find | |
449 | * this, just assume they are not being used. | |
450 | */ | |
451 | if (mem_base_hi <= mem_limit_hi) { | |
452 | base |= ((long) mem_base_hi) << 32; | |
453 | limit |= ((long) mem_limit_hi) << 32; | |
454 | } | |
455 | } | |
456 | ||
457 | res = bus->resource[2]; | |
458 | if (base <= limit) { | |
459 | res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | | |
460 | IORESOURCE_MEM | IORESOURCE_PREFETCH); | |
461 | res->start = base; | |
462 | res->end = limit + 0xfffff; | |
463 | pci_resource_adjust(res, &pbm->mem_space); | |
464 | } | |
465 | } | |
466 | ||
01f94c4a DM |
467 | /* Cook up fake bus resources for SUNW,simba PCI bridges which lack |
468 | * a proper 'ranges' property. | |
469 | */ | |
a6009dda DM |
470 | static void __devinit apb_fake_ranges(struct pci_dev *dev, |
471 | struct pci_bus *bus, | |
472 | struct pci_pbm_info *pbm) | |
01f94c4a DM |
473 | { |
474 | struct resource *res; | |
475 | u32 first, last; | |
476 | u8 map; | |
477 | ||
478 | pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map); | |
479 | apb_calc_first_last(map, &first, &last); | |
480 | res = bus->resource[0]; | |
481 | res->start = (first << 21); | |
482 | res->end = (last << 21) + ((1 << 21) - 1); | |
483 | res->flags = IORESOURCE_IO; | |
0bae5f81 | 484 | pci_resource_adjust(res, &pbm->io_space); |
01f94c4a DM |
485 | |
486 | pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map); | |
487 | apb_calc_first_last(map, &first, &last); | |
488 | res = bus->resource[1]; | |
489 | res->start = (first << 21); | |
490 | res->end = (last << 21) + ((1 << 21) - 1); | |
491 | res->flags = IORESOURCE_MEM; | |
0bae5f81 | 492 | pci_resource_adjust(res, &pbm->mem_space); |
01f94c4a DM |
493 | } |
494 | ||
a6009dda DM |
495 | static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm, |
496 | struct device_node *node, | |
497 | struct pci_bus *bus); | |
a2fb23af DM |
498 | |
499 | #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1]) | |
500 | ||
a6009dda DM |
501 | static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm, |
502 | struct device_node *node, | |
503 | struct pci_dev *dev) | |
a2fb23af DM |
504 | { |
505 | struct pci_bus *bus; | |
506 | const u32 *busrange, *ranges; | |
01f94c4a | 507 | int len, i, simba; |
a2fb23af DM |
508 | struct resource *res; |
509 | unsigned int flags; | |
510 | u64 size; | |
511 | ||
5840fc66 DM |
512 | if (ofpci_verbose) |
513 | printk("of_scan_pci_bridge(%s)\n", node->full_name); | |
a2fb23af DM |
514 | |
515 | /* parse bus-range property */ | |
516 | busrange = of_get_property(node, "bus-range", &len); | |
517 | if (busrange == NULL || len != 8) { | |
518 | printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n", | |
519 | node->full_name); | |
520 | return; | |
521 | } | |
522 | ranges = of_get_property(node, "ranges", &len); | |
01f94c4a | 523 | simba = 0; |
a2fb23af | 524 | if (ranges == NULL) { |
a165b420 | 525 | const char *model = of_get_property(node, "model", NULL); |
8c2786cf | 526 | if (model && !strcmp(model, "SUNW,simba")) |
01f94c4a | 527 | simba = 1; |
a2fb23af DM |
528 | } |
529 | ||
530 | bus = pci_add_new_bus(dev->bus, dev, busrange[0]); | |
531 | if (!bus) { | |
532 | printk(KERN_ERR "Failed to create pci bus for %s\n", | |
533 | node->full_name); | |
534 | return; | |
535 | } | |
536 | ||
537 | bus->primary = dev->bus->number; | |
538 | bus->subordinate = busrange[1]; | |
539 | bus->bridge_ctl = 0; | |
540 | ||
01f94c4a | 541 | /* parse ranges property, or cook one up by hand for Simba */ |
a2fb23af DM |
542 | /* PCI #address-cells == 3 and #size-cells == 2 always */ |
543 | res = &dev->resource[PCI_BRIDGE_RESOURCES]; | |
544 | for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) { | |
545 | res->flags = 0; | |
546 | bus->resource[i] = res; | |
547 | ++res; | |
548 | } | |
01f94c4a DM |
549 | if (simba) { |
550 | apb_fake_ranges(dev, bus, pbm); | |
8c2786cf DM |
551 | goto after_ranges; |
552 | } else if (ranges == NULL) { | |
553 | pci_cfg_fake_ranges(dev, bus, pbm); | |
554 | goto after_ranges; | |
01f94c4a | 555 | } |
a2fb23af DM |
556 | i = 1; |
557 | for (; len >= 32; len -= 32, ranges += 8) { | |
558 | struct resource *root; | |
559 | ||
560 | flags = pci_parse_of_flags(ranges[0]); | |
561 | size = GET_64BIT(ranges, 6); | |
562 | if (flags == 0 || size == 0) | |
563 | continue; | |
564 | if (flags & IORESOURCE_IO) { | |
565 | res = bus->resource[0]; | |
566 | if (res->flags) { | |
567 | printk(KERN_ERR "PCI: ignoring extra I/O range" | |
568 | " for bridge %s\n", node->full_name); | |
569 | continue; | |
570 | } | |
571 | root = &pbm->io_space; | |
572 | } else { | |
573 | if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) { | |
574 | printk(KERN_ERR "PCI: too many memory ranges" | |
575 | " for bridge %s\n", node->full_name); | |
576 | continue; | |
577 | } | |
578 | res = bus->resource[i]; | |
579 | ++i; | |
580 | root = &pbm->mem_space; | |
581 | } | |
582 | ||
583 | res->start = GET_64BIT(ranges, 1); | |
584 | res->end = res->start + size - 1; | |
585 | res->flags = flags; | |
586 | ||
587 | /* Another way to implement this would be to add an of_device | |
588 | * layer routine that can calculate a resource for a given | |
589 | * range property value in a PCI device. | |
590 | */ | |
0bae5f81 | 591 | pci_resource_adjust(res, root); |
a2fb23af | 592 | } |
8c2786cf | 593 | after_ranges: |
a2fb23af DM |
594 | sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus), |
595 | bus->number); | |
5840fc66 DM |
596 | if (ofpci_verbose) |
597 | printk(" bus name: %s\n", bus->name); | |
a2fb23af DM |
598 | |
599 | pci_of_scan_bus(pbm, node, bus); | |
600 | } | |
601 | ||
a6009dda DM |
602 | static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm, |
603 | struct device_node *node, | |
604 | struct pci_bus *bus) | |
a2fb23af DM |
605 | { |
606 | struct device_node *child; | |
607 | const u32 *reg; | |
2cc7345f | 608 | int reglen, devfn, prev_devfn; |
a2fb23af DM |
609 | struct pci_dev *dev; |
610 | ||
5840fc66 DM |
611 | if (ofpci_verbose) |
612 | printk("PCI: scan_bus[%s] bus no %d\n", | |
613 | node->full_name, bus->number); | |
a2fb23af DM |
614 | |
615 | child = NULL; | |
2cc7345f | 616 | prev_devfn = -1; |
a2fb23af | 617 | while ((child = of_get_next_child(node, child)) != NULL) { |
5840fc66 DM |
618 | if (ofpci_verbose) |
619 | printk(" * %s\n", child->full_name); | |
a2fb23af DM |
620 | reg = of_get_property(child, "reg", ®len); |
621 | if (reg == NULL || reglen < 20) | |
622 | continue; | |
2cc7345f | 623 | |
a2fb23af DM |
624 | devfn = (reg[0] >> 8) & 0xff; |
625 | ||
2cc7345f DM |
626 | /* This is a workaround for some device trees |
627 | * which list PCI devices twice. On the V100 | |
628 | * for example, device number 3 is listed twice. | |
629 | * Once as "pm" and once again as "lomp". | |
630 | */ | |
631 | if (devfn == prev_devfn) | |
632 | continue; | |
633 | prev_devfn = devfn; | |
634 | ||
a2fb23af | 635 | /* create a new pci_dev for this device */ |
c26d3c01 | 636 | dev = of_create_pci_dev(pbm, child, bus, devfn); |
a2fb23af DM |
637 | if (!dev) |
638 | continue; | |
5840fc66 DM |
639 | if (ofpci_verbose) |
640 | printk("PCI: dev header type: %x\n", | |
641 | dev->hdr_type); | |
a2fb23af DM |
642 | |
643 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
644 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
645 | of_scan_pci_bridge(pbm, child, dev); | |
646 | } | |
647 | } | |
648 | ||
649 | static ssize_t | |
650 | show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf) | |
651 | { | |
652 | struct pci_dev *pdev; | |
653 | struct device_node *dp; | |
654 | ||
655 | pdev = to_pci_dev(dev); | |
656 | dp = pdev->dev.archdata.prom_node; | |
657 | ||
658 | return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name); | |
659 | } | |
660 | ||
661 | static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL); | |
662 | ||
663 | static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus) | |
664 | { | |
665 | struct pci_dev *dev; | |
a378fd0e | 666 | struct pci_bus *child_bus; |
a2fb23af DM |
667 | int err; |
668 | ||
669 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
670 | /* we don't really care if we can create this file or | |
671 | * not, but we need to assign the result of the call | |
672 | * or the world will fall under alien invasion and | |
673 | * everybody will be frozen on a spaceship ready to be | |
674 | * eaten on alpha centauri by some green and jelly | |
675 | * humanoid. | |
676 | */ | |
677 | err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr); | |
678 | } | |
a378fd0e DM |
679 | list_for_each_entry(child_bus, &bus->children, node) |
680 | pci_bus_register_of_sysfs(child_bus); | |
a2fb23af DM |
681 | } |
682 | ||
e822358a DM |
683 | struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm, |
684 | struct device *parent) | |
a2fb23af | 685 | { |
22fecbae | 686 | struct device_node *node = pbm->op->node; |
a2fb23af DM |
687 | struct pci_bus *bus; |
688 | ||
689 | printk("PCI: Scanning PBM %s\n", node->full_name); | |
690 | ||
e822358a | 691 | bus = pci_create_bus(parent, pbm->pci_first_busno, pbm->pci_ops, pbm); |
a2fb23af DM |
692 | if (!bus) { |
693 | printk(KERN_ERR "Failed to create bus for %s\n", | |
694 | node->full_name); | |
695 | return NULL; | |
696 | } | |
697 | bus->secondary = pbm->pci_first_busno; | |
698 | bus->subordinate = pbm->pci_last_busno; | |
699 | ||
700 | bus->resource[0] = &pbm->io_space; | |
701 | bus->resource[1] = &pbm->mem_space; | |
702 | ||
703 | pci_of_scan_bus(pbm, node, bus); | |
704 | pci_bus_add_devices(bus); | |
705 | pci_bus_register_of_sysfs(bus); | |
706 | ||
707 | return bus; | |
708 | } | |
709 | ||
f6b45da1 | 710 | void __devinit pcibios_fixup_bus(struct pci_bus *pbus) |
1da177e4 LT |
711 | { |
712 | struct pci_pbm_info *pbm = pbus->sysdata; | |
713 | ||
714 | /* Generic PCI bus probing sets these to point at | |
715 | * &io{port,mem}_resouce which is wrong for us. | |
716 | */ | |
717 | pbus->resource[0] = &pbm->io_space; | |
718 | pbus->resource[1] = &pbm->mem_space; | |
719 | } | |
720 | ||
1da177e4 LT |
721 | void pcibios_update_irq(struct pci_dev *pdev, int irq) |
722 | { | |
723 | } | |
724 | ||
725 | void pcibios_align_resource(void *data, struct resource *res, | |
e31dd6e4 | 726 | resource_size_t size, resource_size_t align) |
1da177e4 LT |
727 | { |
728 | } | |
729 | ||
a2fb23af | 730 | int pcibios_enable_device(struct pci_dev *dev, int mask) |
1da177e4 | 731 | { |
a2fb23af DM |
732 | u16 cmd, oldcmd; |
733 | int i; | |
734 | ||
735 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
736 | oldcmd = cmd; | |
737 | ||
738 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
739 | struct resource *res = &dev->resource[i]; | |
740 | ||
741 | /* Only set up the requested stuff */ | |
742 | if (!(mask & (1<<i))) | |
743 | continue; | |
744 | ||
745 | if (res->flags & IORESOURCE_IO) | |
746 | cmd |= PCI_COMMAND_IO; | |
747 | if (res->flags & IORESOURCE_MEM) | |
748 | cmd |= PCI_COMMAND_MEMORY; | |
749 | } | |
750 | ||
751 | if (cmd != oldcmd) { | |
752 | printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n", | |
753 | pci_name(dev), cmd); | |
754 | /* Enable the appropriate bits in the PCI command register. */ | |
755 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
756 | } | |
1da177e4 LT |
757 | return 0; |
758 | } | |
759 | ||
760 | void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region, | |
761 | struct resource *res) | |
762 | { | |
763 | struct pci_pbm_info *pbm = pdev->bus->sysdata; | |
764 | struct resource zero_res, *root; | |
765 | ||
766 | zero_res.start = 0; | |
767 | zero_res.end = 0; | |
768 | zero_res.flags = res->flags; | |
769 | ||
770 | if (res->flags & IORESOURCE_IO) | |
771 | root = &pbm->io_space; | |
772 | else | |
773 | root = &pbm->mem_space; | |
774 | ||
0bae5f81 | 775 | pci_resource_adjust(&zero_res, root); |
1da177e4 LT |
776 | |
777 | region->start = res->start - zero_res.start; | |
778 | region->end = res->end - zero_res.start; | |
779 | } | |
5fdfd42e | 780 | EXPORT_SYMBOL(pcibios_resource_to_bus); |
1da177e4 LT |
781 | |
782 | void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res, | |
783 | struct pci_bus_region *region) | |
784 | { | |
785 | struct pci_pbm_info *pbm = pdev->bus->sysdata; | |
786 | struct resource *root; | |
787 | ||
788 | res->start = region->start; | |
789 | res->end = region->end; | |
790 | ||
791 | if (res->flags & IORESOURCE_IO) | |
792 | root = &pbm->io_space; | |
793 | else | |
794 | root = &pbm->mem_space; | |
795 | ||
0bae5f81 | 796 | pci_resource_adjust(res, root); |
1da177e4 | 797 | } |
41290c14 | 798 | EXPORT_SYMBOL(pcibios_bus_to_resource); |
1da177e4 | 799 | |
f6b45da1 | 800 | char * __devinit pcibios_setup(char *str) |
1da177e4 | 801 | { |
1da177e4 LT |
802 | return str; |
803 | } | |
804 | ||
805 | /* Platform support for /proc/bus/pci/X/Y mmap()s. */ | |
806 | ||
807 | /* If the user uses a host-bridge as the PCI device, he may use | |
808 | * this to perform a raw mmap() of the I/O or MEM space behind | |
809 | * that controller. | |
810 | * | |
811 | * This can be useful for execution of x86 PCI bios initialization code | |
812 | * on a PCI card, like the xfree86 int10 stuff does. | |
813 | */ | |
814 | static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma, | |
815 | enum pci_mmap_state mmap_state) | |
816 | { | |
a2fb23af | 817 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
1da177e4 LT |
818 | unsigned long space_size, user_offset, user_size; |
819 | ||
3875c5c0 DM |
820 | if (mmap_state == pci_mmap_io) { |
821 | space_size = (pbm->io_space.end - | |
822 | pbm->io_space.start) + 1; | |
1da177e4 | 823 | } else { |
3875c5c0 DM |
824 | space_size = (pbm->mem_space.end - |
825 | pbm->mem_space.start) + 1; | |
1da177e4 LT |
826 | } |
827 | ||
828 | /* Make sure the request is in range. */ | |
829 | user_offset = vma->vm_pgoff << PAGE_SHIFT; | |
830 | user_size = vma->vm_end - vma->vm_start; | |
831 | ||
832 | if (user_offset >= space_size || | |
833 | (user_offset + user_size) > space_size) | |
834 | return -EINVAL; | |
835 | ||
3875c5c0 DM |
836 | if (mmap_state == pci_mmap_io) { |
837 | vma->vm_pgoff = (pbm->io_space.start + | |
838 | user_offset) >> PAGE_SHIFT; | |
1da177e4 | 839 | } else { |
3875c5c0 DM |
840 | vma->vm_pgoff = (pbm->mem_space.start + |
841 | user_offset) >> PAGE_SHIFT; | |
1da177e4 LT |
842 | } |
843 | ||
844 | return 0; | |
845 | } | |
846 | ||
bbe0b5eb DM |
847 | /* Adjust vm_pgoff of VMA such that it is the physical page offset |
848 | * corresponding to the 32-bit pci bus offset for DEV requested by the user. | |
1da177e4 LT |
849 | * |
850 | * Basically, the user finds the base address for his device which he wishes | |
851 | * to mmap. They read the 32-bit value from the config space base register, | |
852 | * add whatever PAGE_SIZE multiple offset they wish, and feed this into the | |
853 | * offset parameter of mmap on /proc/bus/pci/XXX for that device. | |
854 | * | |
855 | * Returns negative error code on failure, zero on success. | |
856 | */ | |
bbe0b5eb DM |
857 | static int __pci_mmap_make_offset(struct pci_dev *pdev, |
858 | struct vm_area_struct *vma, | |
1da177e4 LT |
859 | enum pci_mmap_state mmap_state) |
860 | { | |
bbe0b5eb DM |
861 | unsigned long user_paddr, user_size; |
862 | int i, err; | |
1da177e4 | 863 | |
bbe0b5eb DM |
864 | /* First compute the physical address in vma->vm_pgoff, |
865 | * making sure the user offset is within range in the | |
866 | * appropriate PCI space. | |
867 | */ | |
868 | err = __pci_mmap_make_offset_bus(pdev, vma, mmap_state); | |
869 | if (err) | |
870 | return err; | |
871 | ||
872 | /* If this is a mapping on a host bridge, any address | |
873 | * is OK. | |
874 | */ | |
875 | if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST) | |
876 | return err; | |
877 | ||
878 | /* Otherwise make sure it's in the range for one of the | |
879 | * device's resources. | |
880 | */ | |
881 | user_paddr = vma->vm_pgoff << PAGE_SHIFT; | |
882 | user_size = vma->vm_end - vma->vm_start; | |
1da177e4 | 883 | |
1da177e4 | 884 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { |
bbe0b5eb | 885 | struct resource *rp = &pdev->resource[i]; |
5769907a | 886 | resource_size_t aligned_end; |
1da177e4 LT |
887 | |
888 | /* Active? */ | |
889 | if (!rp->flags) | |
890 | continue; | |
891 | ||
892 | /* Same type? */ | |
893 | if (i == PCI_ROM_RESOURCE) { | |
894 | if (mmap_state != pci_mmap_mem) | |
895 | continue; | |
896 | } else { | |
897 | if ((mmap_state == pci_mmap_io && | |
898 | (rp->flags & IORESOURCE_IO) == 0) || | |
899 | (mmap_state == pci_mmap_mem && | |
900 | (rp->flags & IORESOURCE_MEM) == 0)) | |
901 | continue; | |
902 | } | |
903 | ||
5769907a MD |
904 | /* Align the resource end to the next page address. |
905 | * PAGE_SIZE intentionally added instead of (PAGE_SIZE - 1), | |
906 | * because actually we need the address of the next byte | |
907 | * after rp->end. | |
908 | */ | |
909 | aligned_end = (rp->end + PAGE_SIZE) & PAGE_MASK; | |
910 | ||
bbe0b5eb | 911 | if ((rp->start <= user_paddr) && |
5769907a | 912 | (user_paddr + user_size) <= aligned_end) |
bbe0b5eb | 913 | break; |
1da177e4 LT |
914 | } |
915 | ||
bbe0b5eb | 916 | if (i > PCI_ROM_RESOURCE) |
1da177e4 LT |
917 | return -EINVAL; |
918 | ||
1da177e4 LT |
919 | return 0; |
920 | } | |
921 | ||
922 | /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device | |
923 | * mapping. | |
924 | */ | |
925 | static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma, | |
926 | enum pci_mmap_state mmap_state) | |
927 | { | |
928 | vma->vm_flags |= (VM_IO | VM_RESERVED); | |
929 | } | |
930 | ||
931 | /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci | |
932 | * device mapping. | |
933 | */ | |
934 | static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma, | |
935 | enum pci_mmap_state mmap_state) | |
936 | { | |
a7a6cac2 | 937 | /* Our io_remap_pfn_range takes care of this, do nothing. */ |
1da177e4 LT |
938 | } |
939 | ||
940 | /* Perform the actual remap of the pages for a PCI device mapping, as appropriate | |
941 | * for this architecture. The region in the process to map is described by vm_start | |
942 | * and vm_end members of VMA, the base physical address is found in vm_pgoff. | |
943 | * The pci device structure is provided so that architectures may make mapping | |
944 | * decisions on a per-device or per-bus basis. | |
945 | * | |
946 | * Returns a negative error code on failure, zero on success. | |
947 | */ | |
948 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | |
949 | enum pci_mmap_state mmap_state, | |
950 | int write_combine) | |
951 | { | |
952 | int ret; | |
953 | ||
954 | ret = __pci_mmap_make_offset(dev, vma, mmap_state); | |
955 | if (ret < 0) | |
956 | return ret; | |
957 | ||
958 | __pci_mmap_set_flags(dev, vma, mmap_state); | |
959 | __pci_mmap_set_pgprot(dev, vma, mmap_state); | |
960 | ||
14778d90 | 961 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
1da177e4 LT |
962 | ret = io_remap_pfn_range(vma, vma->vm_start, |
963 | vma->vm_pgoff, | |
964 | vma->vm_end - vma->vm_start, | |
965 | vma->vm_page_prot); | |
966 | if (ret) | |
967 | return ret; | |
968 | ||
1da177e4 LT |
969 | return 0; |
970 | } | |
971 | ||
c1b1a5f1 DM |
972 | #ifdef CONFIG_NUMA |
973 | int pcibus_to_node(struct pci_bus *pbus) | |
974 | { | |
975 | struct pci_pbm_info *pbm = pbus->sysdata; | |
976 | ||
977 | return pbm->numa_node; | |
978 | } | |
979 | EXPORT_SYMBOL(pcibus_to_node); | |
980 | #endif | |
981 | ||
d3ae4b5b | 982 | /* Return the domain number for this pci bus */ |
1da177e4 LT |
983 | |
984 | int pci_domain_nr(struct pci_bus *pbus) | |
985 | { | |
986 | struct pci_pbm_info *pbm = pbus->sysdata; | |
987 | int ret; | |
988 | ||
d3ae4b5b | 989 | if (!pbm) { |
1da177e4 LT |
990 | ret = -ENXIO; |
991 | } else { | |
6c108f12 | 992 | ret = pbm->index; |
1da177e4 LT |
993 | } |
994 | ||
995 | return ret; | |
996 | } | |
997 | EXPORT_SYMBOL(pci_domain_nr); | |
998 | ||
35a17eb6 DM |
999 | #ifdef CONFIG_PCI_MSI |
1000 | int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) | |
1001 | { | |
a2fb23af | 1002 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
77d10d0e | 1003 | unsigned int virt_irq; |
35a17eb6 | 1004 | |
e9870c4c | 1005 | if (!pbm->setup_msi_irq) |
35a17eb6 DM |
1006 | return -EINVAL; |
1007 | ||
e9870c4c | 1008 | return pbm->setup_msi_irq(&virt_irq, pdev, desc); |
35a17eb6 DM |
1009 | } |
1010 | ||
1011 | void arch_teardown_msi_irq(unsigned int virt_irq) | |
1012 | { | |
abfd336c | 1013 | struct msi_desc *entry = get_irq_msi(virt_irq); |
35a17eb6 | 1014 | struct pci_dev *pdev = entry->dev; |
a2fb23af | 1015 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
35a17eb6 | 1016 | |
77d10d0e DM |
1017 | if (pbm->teardown_msi_irq) |
1018 | pbm->teardown_msi_irq(virt_irq, pdev); | |
35a17eb6 DM |
1019 | } |
1020 | #endif /* !(CONFIG_PCI_MSI) */ | |
1021 | ||
f6d0f9ea DM |
1022 | struct device_node *pci_device_to_OF_node(struct pci_dev *pdev) |
1023 | { | |
a2fb23af | 1024 | return pdev->dev.archdata.prom_node; |
f6d0f9ea DM |
1025 | } |
1026 | EXPORT_SYMBOL(pci_device_to_OF_node); | |
1027 | ||
ad7ad57c DM |
1028 | static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit) |
1029 | { | |
1030 | struct pci_dev *ali_isa_bridge; | |
1031 | u8 val; | |
1032 | ||
1033 | /* ALI sound chips generate 31-bits of DMA, a special register | |
1034 | * determines what bit 31 is emitted as. | |
1035 | */ | |
1036 | ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL, | |
1037 | PCI_DEVICE_ID_AL_M1533, | |
1038 | NULL); | |
1039 | ||
1040 | pci_read_config_byte(ali_isa_bridge, 0x7e, &val); | |
1041 | if (set_bit) | |
1042 | val |= 0x01; | |
1043 | else | |
1044 | val &= ~0x01; | |
1045 | pci_write_config_byte(ali_isa_bridge, 0x7e, val); | |
1046 | pci_dev_put(ali_isa_bridge); | |
1047 | } | |
1048 | ||
ee664a92 | 1049 | int pci64_dma_supported(struct pci_dev *pdev, u64 device_mask) |
ad7ad57c DM |
1050 | { |
1051 | u64 dma_addr_mask; | |
1052 | ||
1053 | if (pdev == NULL) { | |
1054 | dma_addr_mask = 0xffffffff; | |
1055 | } else { | |
1056 | struct iommu *iommu = pdev->dev.archdata.iommu; | |
1057 | ||
1058 | dma_addr_mask = iommu->dma_addr_mask; | |
1059 | ||
1060 | if (pdev->vendor == PCI_VENDOR_ID_AL && | |
1061 | pdev->device == PCI_DEVICE_ID_AL_M5451 && | |
1062 | device_mask == 0x7fffffff) { | |
1063 | ali_sound_dma_hack(pdev, | |
1064 | (dma_addr_mask & 0x80000000) != 0); | |
1065 | return 1; | |
1066 | } | |
1067 | } | |
1068 | ||
1069 | if (device_mask >= (1UL << 32UL)) | |
1070 | return 0; | |
1071 | ||
1072 | return (device_mask & dma_addr_mask) == dma_addr_mask; | |
1073 | } | |
1074 | ||
bcea1db1 DM |
1075 | void pci_resource_to_user(const struct pci_dev *pdev, int bar, |
1076 | const struct resource *rp, resource_size_t *start, | |
1077 | resource_size_t *end) | |
1078 | { | |
1079 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; | |
1080 | unsigned long offset; | |
1081 | ||
1082 | if (rp->flags & IORESOURCE_IO) | |
1083 | offset = pbm->io_space.start; | |
1084 | else | |
1085 | offset = pbm->mem_space.start; | |
1086 | ||
1087 | *start = rp->start - offset; | |
1088 | *end = rp->end - offset; | |
1089 | } | |
4c0eec7a TH |
1090 | |
1091 | static int __init pcibios_init(void) | |
1092 | { | |
1093 | pci_dfl_cache_line_size = 64 >> 2; | |
1094 | return 0; | |
1095 | } | |
1096 | subsys_initcall(pcibios_init); |