Commit | Line | Data |
---|---|---|
a2fb23af | 1 | /* pci.c: UltraSparc PCI controller support. |
1da177e4 LT |
2 | * |
3 | * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com) | |
4 | * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be) | |
5 | * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz) | |
a2fb23af DM |
6 | * |
7 | * OF tree based PCI bus probing taken from the PowerPC port | |
8 | * with minor modifications, see there for credits. | |
1da177e4 LT |
9 | */ |
10 | ||
066bcaca | 11 | #include <linux/export.h> |
1da177e4 LT |
12 | #include <linux/kernel.h> |
13 | #include <linux/string.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/capability.h> | |
16 | #include <linux/errno.h> | |
c57c2ffb | 17 | #include <linux/pci.h> |
35a17eb6 DM |
18 | #include <linux/msi.h> |
19 | #include <linux/irq.h> | |
1da177e4 | 20 | #include <linux/init.h> |
356d1647 DM |
21 | #include <linux/of.h> |
22 | #include <linux/of_device.h> | |
1da177e4 LT |
23 | |
24 | #include <asm/uaccess.h> | |
1da177e4 LT |
25 | #include <asm/pgtable.h> |
26 | #include <asm/irq.h> | |
e87dc350 | 27 | #include <asm/prom.h> |
01f94c4a | 28 | #include <asm/apb.h> |
1da177e4 | 29 | |
1e8a8cc5 DM |
30 | #include "pci_impl.h" |
31 | ||
1da177e4 | 32 | /* List of all PCI controllers found in the system. */ |
34768bc8 | 33 | struct pci_pbm_info *pci_pbm_root = NULL; |
1da177e4 | 34 | |
6c108f12 DM |
35 | /* Each PBM found gets a unique index. */ |
36 | int pci_num_pbms = 0; | |
1da177e4 | 37 | |
1da177e4 LT |
38 | volatile int pci_poke_in_progress; |
39 | volatile int pci_poke_cpu = -1; | |
40 | volatile int pci_poke_faulted; | |
41 | ||
42 | static DEFINE_SPINLOCK(pci_poke_lock); | |
43 | ||
44 | void pci_config_read8(u8 *addr, u8 *ret) | |
45 | { | |
46 | unsigned long flags; | |
47 | u8 byte; | |
48 | ||
49 | spin_lock_irqsave(&pci_poke_lock, flags); | |
50 | pci_poke_cpu = smp_processor_id(); | |
51 | pci_poke_in_progress = 1; | |
52 | pci_poke_faulted = 0; | |
53 | __asm__ __volatile__("membar #Sync\n\t" | |
54 | "lduba [%1] %2, %0\n\t" | |
55 | "membar #Sync" | |
56 | : "=r" (byte) | |
57 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
58 | : "memory"); | |
59 | pci_poke_in_progress = 0; | |
60 | pci_poke_cpu = -1; | |
61 | if (!pci_poke_faulted) | |
62 | *ret = byte; | |
63 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
64 | } | |
65 | ||
66 | void pci_config_read16(u16 *addr, u16 *ret) | |
67 | { | |
68 | unsigned long flags; | |
69 | u16 word; | |
70 | ||
71 | spin_lock_irqsave(&pci_poke_lock, flags); | |
72 | pci_poke_cpu = smp_processor_id(); | |
73 | pci_poke_in_progress = 1; | |
74 | pci_poke_faulted = 0; | |
75 | __asm__ __volatile__("membar #Sync\n\t" | |
76 | "lduha [%1] %2, %0\n\t" | |
77 | "membar #Sync" | |
78 | : "=r" (word) | |
79 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
80 | : "memory"); | |
81 | pci_poke_in_progress = 0; | |
82 | pci_poke_cpu = -1; | |
83 | if (!pci_poke_faulted) | |
84 | *ret = word; | |
85 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
86 | } | |
87 | ||
88 | void pci_config_read32(u32 *addr, u32 *ret) | |
89 | { | |
90 | unsigned long flags; | |
91 | u32 dword; | |
92 | ||
93 | spin_lock_irqsave(&pci_poke_lock, flags); | |
94 | pci_poke_cpu = smp_processor_id(); | |
95 | pci_poke_in_progress = 1; | |
96 | pci_poke_faulted = 0; | |
97 | __asm__ __volatile__("membar #Sync\n\t" | |
98 | "lduwa [%1] %2, %0\n\t" | |
99 | "membar #Sync" | |
100 | : "=r" (dword) | |
101 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
102 | : "memory"); | |
103 | pci_poke_in_progress = 0; | |
104 | pci_poke_cpu = -1; | |
105 | if (!pci_poke_faulted) | |
106 | *ret = dword; | |
107 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
108 | } | |
109 | ||
110 | void pci_config_write8(u8 *addr, u8 val) | |
111 | { | |
112 | unsigned long flags; | |
113 | ||
114 | spin_lock_irqsave(&pci_poke_lock, flags); | |
115 | pci_poke_cpu = smp_processor_id(); | |
116 | pci_poke_in_progress = 1; | |
117 | pci_poke_faulted = 0; | |
118 | __asm__ __volatile__("membar #Sync\n\t" | |
119 | "stba %0, [%1] %2\n\t" | |
120 | "membar #Sync" | |
121 | : /* no outputs */ | |
122 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
123 | : "memory"); | |
124 | pci_poke_in_progress = 0; | |
125 | pci_poke_cpu = -1; | |
126 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
127 | } | |
128 | ||
129 | void pci_config_write16(u16 *addr, u16 val) | |
130 | { | |
131 | unsigned long flags; | |
132 | ||
133 | spin_lock_irqsave(&pci_poke_lock, flags); | |
134 | pci_poke_cpu = smp_processor_id(); | |
135 | pci_poke_in_progress = 1; | |
136 | pci_poke_faulted = 0; | |
137 | __asm__ __volatile__("membar #Sync\n\t" | |
138 | "stha %0, [%1] %2\n\t" | |
139 | "membar #Sync" | |
140 | : /* no outputs */ | |
141 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
142 | : "memory"); | |
143 | pci_poke_in_progress = 0; | |
144 | pci_poke_cpu = -1; | |
145 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
146 | } | |
147 | ||
148 | void pci_config_write32(u32 *addr, u32 val) | |
149 | { | |
150 | unsigned long flags; | |
151 | ||
152 | spin_lock_irqsave(&pci_poke_lock, flags); | |
153 | pci_poke_cpu = smp_processor_id(); | |
154 | pci_poke_in_progress = 1; | |
155 | pci_poke_faulted = 0; | |
156 | __asm__ __volatile__("membar #Sync\n\t" | |
157 | "stwa %0, [%1] %2\n\t" | |
158 | "membar #Sync" | |
159 | : /* no outputs */ | |
160 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
161 | : "memory"); | |
162 | pci_poke_in_progress = 0; | |
163 | pci_poke_cpu = -1; | |
164 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
165 | } | |
166 | ||
5840fc66 DM |
167 | static int ofpci_verbose; |
168 | ||
169 | static int __init ofpci_debug(char *str) | |
170 | { | |
171 | int val = 0; | |
172 | ||
173 | get_option(&str, &val); | |
174 | if (val) | |
175 | ofpci_verbose = 1; | |
176 | return 1; | |
177 | } | |
178 | ||
179 | __setup("ofpci_debug=", ofpci_debug); | |
180 | ||
a2fb23af DM |
181 | static unsigned long pci_parse_of_flags(u32 addr0) |
182 | { | |
183 | unsigned long flags = 0; | |
184 | ||
185 | if (addr0 & 0x02000000) { | |
186 | flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY; | |
187 | flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64; | |
188 | flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M; | |
189 | if (addr0 & 0x40000000) | |
190 | flags |= IORESOURCE_PREFETCH | |
191 | | PCI_BASE_ADDRESS_MEM_PREFETCH; | |
192 | } else if (addr0 & 0x01000000) | |
193 | flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO; | |
194 | return flags; | |
195 | } | |
196 | ||
197 | /* The of_device layer has translated all of the assigned-address properties | |
198 | * into physical address resources, we only have to figure out the register | |
199 | * mapping. | |
200 | */ | |
cd4cd730 | 201 | static void pci_parse_of_addrs(struct platform_device *op, |
a2fb23af DM |
202 | struct device_node *node, |
203 | struct pci_dev *dev) | |
204 | { | |
205 | struct resource *op_res; | |
206 | const u32 *addrs; | |
207 | int proplen; | |
208 | ||
209 | addrs = of_get_property(node, "assigned-addresses", &proplen); | |
210 | if (!addrs) | |
211 | return; | |
5840fc66 DM |
212 | if (ofpci_verbose) |
213 | printk(" parse addresses (%d bytes) @ %p\n", | |
214 | proplen, addrs); | |
a2fb23af DM |
215 | op_res = &op->resource[0]; |
216 | for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) { | |
217 | struct resource *res; | |
218 | unsigned long flags; | |
219 | int i; | |
220 | ||
221 | flags = pci_parse_of_flags(addrs[0]); | |
222 | if (!flags) | |
223 | continue; | |
224 | i = addrs[0] & 0xff; | |
5840fc66 | 225 | if (ofpci_verbose) |
90181136 | 226 | printk(" start: %llx, end: %llx, i: %x\n", |
5840fc66 | 227 | op_res->start, op_res->end, i); |
a2fb23af DM |
228 | |
229 | if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) { | |
230 | res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2]; | |
231 | } else if (i == dev->rom_base_reg) { | |
232 | res = &dev->resource[PCI_ROM_RESOURCE]; | |
aad45644 KO |
233 | flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
234 | | IORESOURCE_SIZEALIGN; | |
a2fb23af DM |
235 | } else { |
236 | printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i); | |
237 | continue; | |
238 | } | |
239 | res->start = op_res->start; | |
240 | res->end = op_res->end; | |
241 | res->flags = flags; | |
242 | res->name = pci_name(dev); | |
243 | } | |
244 | } | |
245 | ||
77d10d0e DM |
246 | static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm, |
247 | struct device_node *node, | |
248 | struct pci_bus *bus, int devfn) | |
a2fb23af DM |
249 | { |
250 | struct dev_archdata *sd; | |
172d2d00 | 251 | struct pci_slot *slot; |
cd4cd730 | 252 | struct platform_device *op; |
a2fb23af DM |
253 | struct pci_dev *dev; |
254 | const char *type; | |
01f94c4a | 255 | u32 class; |
a2fb23af | 256 | |
26e6385f | 257 | dev = alloc_pci_dev(); |
a2fb23af DM |
258 | if (!dev) |
259 | return NULL; | |
260 | ||
261 | sd = &dev->dev.archdata; | |
262 | sd->iommu = pbm->iommu; | |
263 | sd->stc = &pbm->stc; | |
264 | sd->host_controller = pbm; | |
ae05f87e | 265 | sd->op = op = of_find_device_by_node(node); |
c1b1a5f1 | 266 | sd->numa_node = pbm->numa_node; |
a2fb23af | 267 | |
ae05f87e | 268 | sd = &op->dev.archdata; |
ad7ad57c DM |
269 | sd->iommu = pbm->iommu; |
270 | sd->stc = &pbm->stc; | |
c1b1a5f1 | 271 | sd->numa_node = pbm->numa_node; |
ad7ad57c | 272 | |
ae05f87e DM |
273 | if (!strcmp(node->name, "ebus")) |
274 | of_propagate_archdata(op); | |
275 | ||
a2fb23af DM |
276 | type = of_get_property(node, "device_type", NULL); |
277 | if (type == NULL) | |
278 | type = ""; | |
279 | ||
5840fc66 DM |
280 | if (ofpci_verbose) |
281 | printk(" create device, devfn: %x, type: %s\n", | |
282 | devfn, type); | |
a2fb23af DM |
283 | |
284 | dev->bus = bus; | |
285 | dev->sysdata = node; | |
286 | dev->dev.parent = bus->bridge; | |
287 | dev->dev.bus = &pci_bus_type; | |
98d9f30c | 288 | dev->dev.of_node = of_node_get(node); |
a2fb23af DM |
289 | dev->devfn = devfn; |
290 | dev->multifunction = 0; /* maybe a lie? */ | |
172d2d00 DM |
291 | set_pcie_port_type(dev); |
292 | ||
293 | list_for_each_entry(slot, &dev->bus->slots, list) | |
294 | if (PCI_SLOT(dev->devfn) == slot->number) | |
295 | dev->slot = slot; | |
a2fb23af | 296 | |
c26d3c01 DM |
297 | dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff); |
298 | dev->device = of_getintprop_default(node, "device-id", 0xffff); | |
299 | dev->subsystem_vendor = | |
300 | of_getintprop_default(node, "subsystem-vendor-id", 0); | |
301 | dev->subsystem_device = | |
302 | of_getintprop_default(node, "subsystem-id", 0); | |
303 | ||
304 | dev->cfg_size = pci_cfg_space_size(dev); | |
305 | ||
306 | /* We can't actually use the firmware value, we have | |
307 | * to read what is in the register right now. One | |
308 | * reason is that in the case of IDE interfaces the | |
309 | * firmware can sample the value before the the IDE | |
310 | * interface is programmed into native mode. | |
311 | */ | |
312 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); | |
313 | dev->class = class >> 8; | |
314 | dev->revision = class & 0xff; | |
315 | ||
2222c313 | 316 | dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus), |
c26d3c01 | 317 | dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); |
28f57e77 | 318 | |
5840fc66 DM |
319 | if (ofpci_verbose) |
320 | printk(" class: 0x%x device name: %s\n", | |
321 | dev->class, pci_name(dev)); | |
a2fb23af | 322 | |
861fe906 DM |
323 | /* I have seen IDE devices which will not respond to |
324 | * the bmdma simplex check reads if bus mastering is | |
325 | * disabled. | |
326 | */ | |
327 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) | |
328 | pci_set_master(dev); | |
329 | ||
a2fb23af DM |
330 | dev->current_state = 4; /* unknown power state */ |
331 | dev->error_state = pci_channel_io_normal; | |
172d2d00 | 332 | dev->dma_mask = 0xffffffff; |
a2fb23af | 333 | |
44b50e5a | 334 | if (!strcmp(node->name, "pci")) { |
c26d3c01 | 335 | /* a PCI-PCI bridge */ |
a2fb23af DM |
336 | dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; |
337 | dev->rom_base_reg = PCI_ROM_ADDRESS1; | |
c26d3c01 DM |
338 | } else if (!strcmp(type, "cardbus")) { |
339 | dev->hdr_type = PCI_HEADER_TYPE_CARDBUS; | |
a2fb23af | 340 | } else { |
c26d3c01 DM |
341 | dev->hdr_type = PCI_HEADER_TYPE_NORMAL; |
342 | dev->rom_base_reg = PCI_ROM_ADDRESS; | |
a2fb23af | 343 | |
1636f8ac | 344 | dev->irq = sd->op->archdata.irqs[0]; |
c26d3c01 DM |
345 | if (dev->irq == 0xffffffff) |
346 | dev->irq = PCI_IRQ_NONE; | |
a2fb23af | 347 | } |
c26d3c01 | 348 | |
a2fb23af DM |
349 | pci_parse_of_addrs(sd->op, node, dev); |
350 | ||
5840fc66 DM |
351 | if (ofpci_verbose) |
352 | printk(" adding to system ...\n"); | |
a2fb23af DM |
353 | |
354 | pci_device_add(dev, bus); | |
355 | ||
356 | return dev; | |
357 | } | |
358 | ||
a6009dda | 359 | static void __devinit apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p) |
01f94c4a DM |
360 | { |
361 | u32 idx, first, last; | |
362 | ||
363 | first = 8; | |
364 | last = 0; | |
365 | for (idx = 0; idx < 8; idx++) { | |
366 | if ((map & (1 << idx)) != 0) { | |
367 | if (first > idx) | |
368 | first = idx; | |
369 | if (last < idx) | |
370 | last = idx; | |
371 | } | |
372 | } | |
373 | ||
374 | *first_p = first; | |
375 | *last_p = last; | |
376 | } | |
377 | ||
8c2786cf DM |
378 | /* For PCI bus devices which lack a 'ranges' property we interrogate |
379 | * the config space values to set the resources, just like the generic | |
380 | * Linux PCI probing code does. | |
381 | */ | |
382 | static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev, | |
383 | struct pci_bus *bus, | |
384 | struct pci_pbm_info *pbm) | |
385 | { | |
a031589b BH |
386 | struct pci_bus_region region; |
387 | struct resource *res, res2; | |
8c2786cf DM |
388 | u8 io_base_lo, io_limit_lo; |
389 | u16 mem_base_lo, mem_limit_lo; | |
390 | unsigned long base, limit; | |
391 | ||
392 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); | |
393 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); | |
394 | base = (io_base_lo & PCI_IO_RANGE_MASK) << 8; | |
395 | limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8; | |
396 | ||
397 | if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { | |
398 | u16 io_base_hi, io_limit_hi; | |
399 | ||
400 | pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); | |
401 | pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); | |
402 | base |= (io_base_hi << 16); | |
403 | limit |= (io_limit_hi << 16); | |
404 | } | |
405 | ||
406 | res = bus->resource[0]; | |
407 | if (base <= limit) { | |
408 | res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; | |
a031589b BH |
409 | res2.flags = res->flags; |
410 | region.start = base; | |
411 | region.end = limit + 0xfff; | |
412 | pcibios_bus_to_resource(dev, &res2, ®ion); | |
8c2786cf | 413 | if (!res->start) |
a031589b | 414 | res->start = res2.start; |
8c2786cf | 415 | if (!res->end) |
a031589b | 416 | res->end = res2.end; |
8c2786cf DM |
417 | } |
418 | ||
419 | pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); | |
420 | pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); | |
421 | base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
422 | limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
423 | ||
424 | res = bus->resource[1]; | |
425 | if (base <= limit) { | |
426 | res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | | |
427 | IORESOURCE_MEM); | |
a031589b BH |
428 | region.start = base; |
429 | region.end = limit + 0xfffff; | |
430 | pcibios_bus_to_resource(dev, res, ®ion); | |
8c2786cf DM |
431 | } |
432 | ||
433 | pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); | |
434 | pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); | |
435 | base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; | |
436 | limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; | |
437 | ||
438 | if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { | |
439 | u32 mem_base_hi, mem_limit_hi; | |
440 | ||
441 | pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); | |
442 | pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); | |
443 | ||
444 | /* | |
445 | * Some bridges set the base > limit by default, and some | |
446 | * (broken) BIOSes do not initialize them. If we find | |
447 | * this, just assume they are not being used. | |
448 | */ | |
449 | if (mem_base_hi <= mem_limit_hi) { | |
450 | base |= ((long) mem_base_hi) << 32; | |
451 | limit |= ((long) mem_limit_hi) << 32; | |
452 | } | |
453 | } | |
454 | ||
455 | res = bus->resource[2]; | |
456 | if (base <= limit) { | |
457 | res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | | |
458 | IORESOURCE_MEM | IORESOURCE_PREFETCH); | |
a031589b BH |
459 | region.start = base; |
460 | region.end = limit + 0xfffff; | |
461 | pcibios_bus_to_resource(dev, res, ®ion); | |
8c2786cf DM |
462 | } |
463 | } | |
464 | ||
01f94c4a DM |
465 | /* Cook up fake bus resources for SUNW,simba PCI bridges which lack |
466 | * a proper 'ranges' property. | |
467 | */ | |
a6009dda DM |
468 | static void __devinit apb_fake_ranges(struct pci_dev *dev, |
469 | struct pci_bus *bus, | |
470 | struct pci_pbm_info *pbm) | |
01f94c4a | 471 | { |
a031589b | 472 | struct pci_bus_region region; |
01f94c4a DM |
473 | struct resource *res; |
474 | u32 first, last; | |
475 | u8 map; | |
476 | ||
477 | pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map); | |
478 | apb_calc_first_last(map, &first, &last); | |
479 | res = bus->resource[0]; | |
01f94c4a | 480 | res->flags = IORESOURCE_IO; |
a031589b BH |
481 | region.start = (first << 21); |
482 | region.end = (last << 21) + ((1 << 21) - 1); | |
483 | pcibios_bus_to_resource(dev, res, ®ion); | |
01f94c4a DM |
484 | |
485 | pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map); | |
486 | apb_calc_first_last(map, &first, &last); | |
487 | res = bus->resource[1]; | |
01f94c4a | 488 | res->flags = IORESOURCE_MEM; |
a031589b BH |
489 | region.start = (first << 21); |
490 | region.end = (last << 21) + ((1 << 21) - 1); | |
491 | pcibios_bus_to_resource(dev, res, ®ion); | |
01f94c4a DM |
492 | } |
493 | ||
a6009dda DM |
494 | static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm, |
495 | struct device_node *node, | |
496 | struct pci_bus *bus); | |
a2fb23af DM |
497 | |
498 | #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1]) | |
499 | ||
a6009dda DM |
500 | static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm, |
501 | struct device_node *node, | |
502 | struct pci_dev *dev) | |
a2fb23af DM |
503 | { |
504 | struct pci_bus *bus; | |
505 | const u32 *busrange, *ranges; | |
01f94c4a | 506 | int len, i, simba; |
a031589b | 507 | struct pci_bus_region region; |
a2fb23af DM |
508 | struct resource *res; |
509 | unsigned int flags; | |
510 | u64 size; | |
511 | ||
5840fc66 DM |
512 | if (ofpci_verbose) |
513 | printk("of_scan_pci_bridge(%s)\n", node->full_name); | |
a2fb23af DM |
514 | |
515 | /* parse bus-range property */ | |
516 | busrange = of_get_property(node, "bus-range", &len); | |
517 | if (busrange == NULL || len != 8) { | |
518 | printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n", | |
519 | node->full_name); | |
520 | return; | |
521 | } | |
522 | ranges = of_get_property(node, "ranges", &len); | |
01f94c4a | 523 | simba = 0; |
a2fb23af | 524 | if (ranges == NULL) { |
a165b420 | 525 | const char *model = of_get_property(node, "model", NULL); |
8c2786cf | 526 | if (model && !strcmp(model, "SUNW,simba")) |
01f94c4a | 527 | simba = 1; |
a2fb23af DM |
528 | } |
529 | ||
530 | bus = pci_add_new_bus(dev->bus, dev, busrange[0]); | |
531 | if (!bus) { | |
532 | printk(KERN_ERR "Failed to create pci bus for %s\n", | |
533 | node->full_name); | |
534 | return; | |
535 | } | |
536 | ||
537 | bus->primary = dev->bus->number; | |
b918c62e | 538 | bus->busn_res.end = busrange[1]; |
a2fb23af DM |
539 | bus->bridge_ctl = 0; |
540 | ||
01f94c4a | 541 | /* parse ranges property, or cook one up by hand for Simba */ |
a2fb23af DM |
542 | /* PCI #address-cells == 3 and #size-cells == 2 always */ |
543 | res = &dev->resource[PCI_BRIDGE_RESOURCES]; | |
544 | for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) { | |
545 | res->flags = 0; | |
546 | bus->resource[i] = res; | |
547 | ++res; | |
548 | } | |
01f94c4a DM |
549 | if (simba) { |
550 | apb_fake_ranges(dev, bus, pbm); | |
8c2786cf DM |
551 | goto after_ranges; |
552 | } else if (ranges == NULL) { | |
553 | pci_cfg_fake_ranges(dev, bus, pbm); | |
554 | goto after_ranges; | |
01f94c4a | 555 | } |
a2fb23af DM |
556 | i = 1; |
557 | for (; len >= 32; len -= 32, ranges += 8) { | |
a2fb23af DM |
558 | flags = pci_parse_of_flags(ranges[0]); |
559 | size = GET_64BIT(ranges, 6); | |
560 | if (flags == 0 || size == 0) | |
561 | continue; | |
562 | if (flags & IORESOURCE_IO) { | |
563 | res = bus->resource[0]; | |
564 | if (res->flags) { | |
565 | printk(KERN_ERR "PCI: ignoring extra I/O range" | |
566 | " for bridge %s\n", node->full_name); | |
567 | continue; | |
568 | } | |
a2fb23af DM |
569 | } else { |
570 | if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) { | |
571 | printk(KERN_ERR "PCI: too many memory ranges" | |
572 | " for bridge %s\n", node->full_name); | |
573 | continue; | |
574 | } | |
575 | res = bus->resource[i]; | |
576 | ++i; | |
a2fb23af DM |
577 | } |
578 | ||
a2fb23af | 579 | res->flags = flags; |
a031589b BH |
580 | region.start = GET_64BIT(ranges, 1); |
581 | region.end = region.start + size - 1; | |
582 | pcibios_bus_to_resource(dev, res, ®ion); | |
a2fb23af | 583 | } |
8c2786cf | 584 | after_ranges: |
a2fb23af DM |
585 | sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus), |
586 | bus->number); | |
5840fc66 DM |
587 | if (ofpci_verbose) |
588 | printk(" bus name: %s\n", bus->name); | |
a2fb23af DM |
589 | |
590 | pci_of_scan_bus(pbm, node, bus); | |
591 | } | |
592 | ||
a6009dda DM |
593 | static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm, |
594 | struct device_node *node, | |
595 | struct pci_bus *bus) | |
a2fb23af DM |
596 | { |
597 | struct device_node *child; | |
598 | const u32 *reg; | |
2cc7345f | 599 | int reglen, devfn, prev_devfn; |
a2fb23af DM |
600 | struct pci_dev *dev; |
601 | ||
5840fc66 DM |
602 | if (ofpci_verbose) |
603 | printk("PCI: scan_bus[%s] bus no %d\n", | |
604 | node->full_name, bus->number); | |
a2fb23af DM |
605 | |
606 | child = NULL; | |
2cc7345f | 607 | prev_devfn = -1; |
a2fb23af | 608 | while ((child = of_get_next_child(node, child)) != NULL) { |
5840fc66 DM |
609 | if (ofpci_verbose) |
610 | printk(" * %s\n", child->full_name); | |
a2fb23af DM |
611 | reg = of_get_property(child, "reg", ®len); |
612 | if (reg == NULL || reglen < 20) | |
613 | continue; | |
2cc7345f | 614 | |
a2fb23af DM |
615 | devfn = (reg[0] >> 8) & 0xff; |
616 | ||
2cc7345f DM |
617 | /* This is a workaround for some device trees |
618 | * which list PCI devices twice. On the V100 | |
619 | * for example, device number 3 is listed twice. | |
620 | * Once as "pm" and once again as "lomp". | |
621 | */ | |
622 | if (devfn == prev_devfn) | |
623 | continue; | |
624 | prev_devfn = devfn; | |
625 | ||
a2fb23af | 626 | /* create a new pci_dev for this device */ |
c26d3c01 | 627 | dev = of_create_pci_dev(pbm, child, bus, devfn); |
a2fb23af DM |
628 | if (!dev) |
629 | continue; | |
5840fc66 DM |
630 | if (ofpci_verbose) |
631 | printk("PCI: dev header type: %x\n", | |
632 | dev->hdr_type); | |
a2fb23af DM |
633 | |
634 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
635 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
636 | of_scan_pci_bridge(pbm, child, dev); | |
637 | } | |
638 | } | |
639 | ||
640 | static ssize_t | |
641 | show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf) | |
642 | { | |
643 | struct pci_dev *pdev; | |
644 | struct device_node *dp; | |
645 | ||
646 | pdev = to_pci_dev(dev); | |
61c7a080 | 647 | dp = pdev->dev.of_node; |
a2fb23af DM |
648 | |
649 | return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name); | |
650 | } | |
651 | ||
652 | static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL); | |
653 | ||
654 | static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus) | |
655 | { | |
656 | struct pci_dev *dev; | |
a378fd0e | 657 | struct pci_bus *child_bus; |
a2fb23af DM |
658 | int err; |
659 | ||
660 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
661 | /* we don't really care if we can create this file or | |
662 | * not, but we need to assign the result of the call | |
663 | * or the world will fall under alien invasion and | |
664 | * everybody will be frozen on a spaceship ready to be | |
665 | * eaten on alpha centauri by some green and jelly | |
666 | * humanoid. | |
667 | */ | |
668 | err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr); | |
c6fee081 | 669 | (void) err; |
a2fb23af | 670 | } |
a378fd0e DM |
671 | list_for_each_entry(child_bus, &bus->children, node) |
672 | pci_bus_register_of_sysfs(child_bus); | |
a2fb23af DM |
673 | } |
674 | ||
e822358a DM |
675 | struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm, |
676 | struct device *parent) | |
a2fb23af | 677 | { |
1a300107 | 678 | LIST_HEAD(resources); |
61c7a080 | 679 | struct device_node *node = pbm->op->dev.of_node; |
a2fb23af DM |
680 | struct pci_bus *bus; |
681 | ||
682 | printk("PCI: Scanning PBM %s\n", node->full_name); | |
683 | ||
ac1edcc5 BH |
684 | pci_add_resource_offset(&resources, &pbm->io_space, |
685 | pbm->io_space.start); | |
686 | pci_add_resource_offset(&resources, &pbm->mem_space, | |
687 | pbm->mem_space.start); | |
1a300107 BH |
688 | bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops, |
689 | pbm, &resources); | |
a2fb23af DM |
690 | if (!bus) { |
691 | printk(KERN_ERR "Failed to create bus for %s\n", | |
692 | node->full_name); | |
1a300107 | 693 | pci_free_resource_list(&resources); |
a2fb23af DM |
694 | return NULL; |
695 | } | |
b918c62e YL |
696 | bus->busn_res.start = pbm->pci_first_busno; |
697 | bus->busn_res.end = pbm->pci_last_busno; | |
a2fb23af | 698 | |
a2fb23af DM |
699 | pci_of_scan_bus(pbm, node, bus); |
700 | pci_bus_add_devices(bus); | |
701 | pci_bus_register_of_sysfs(bus); | |
702 | ||
703 | return bus; | |
704 | } | |
705 | ||
f6b45da1 | 706 | void __devinit pcibios_fixup_bus(struct pci_bus *pbus) |
1da177e4 | 707 | { |
1da177e4 LT |
708 | } |
709 | ||
1da177e4 LT |
710 | void pcibios_update_irq(struct pci_dev *pdev, int irq) |
711 | { | |
712 | } | |
713 | ||
3b7a17fc | 714 | resource_size_t pcibios_align_resource(void *data, const struct resource *res, |
b26b2d49 | 715 | resource_size_t size, resource_size_t align) |
1da177e4 | 716 | { |
b26b2d49 | 717 | return res->start; |
1da177e4 LT |
718 | } |
719 | ||
a2fb23af | 720 | int pcibios_enable_device(struct pci_dev *dev, int mask) |
1da177e4 | 721 | { |
a2fb23af DM |
722 | u16 cmd, oldcmd; |
723 | int i; | |
724 | ||
725 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
726 | oldcmd = cmd; | |
727 | ||
728 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
729 | struct resource *res = &dev->resource[i]; | |
730 | ||
731 | /* Only set up the requested stuff */ | |
732 | if (!(mask & (1<<i))) | |
733 | continue; | |
734 | ||
735 | if (res->flags & IORESOURCE_IO) | |
736 | cmd |= PCI_COMMAND_IO; | |
737 | if (res->flags & IORESOURCE_MEM) | |
738 | cmd |= PCI_COMMAND_MEMORY; | |
739 | } | |
740 | ||
741 | if (cmd != oldcmd) { | |
742 | printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n", | |
743 | pci_name(dev), cmd); | |
744 | /* Enable the appropriate bits in the PCI command register. */ | |
745 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
746 | } | |
1da177e4 LT |
747 | return 0; |
748 | } | |
749 | ||
f6b45da1 | 750 | char * __devinit pcibios_setup(char *str) |
1da177e4 | 751 | { |
1da177e4 LT |
752 | return str; |
753 | } | |
754 | ||
755 | /* Platform support for /proc/bus/pci/X/Y mmap()s. */ | |
756 | ||
757 | /* If the user uses a host-bridge as the PCI device, he may use | |
758 | * this to perform a raw mmap() of the I/O or MEM space behind | |
759 | * that controller. | |
760 | * | |
761 | * This can be useful for execution of x86 PCI bios initialization code | |
762 | * on a PCI card, like the xfree86 int10 stuff does. | |
763 | */ | |
764 | static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma, | |
765 | enum pci_mmap_state mmap_state) | |
766 | { | |
a2fb23af | 767 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
1da177e4 LT |
768 | unsigned long space_size, user_offset, user_size; |
769 | ||
3875c5c0 | 770 | if (mmap_state == pci_mmap_io) { |
28f65c11 | 771 | space_size = resource_size(&pbm->io_space); |
1da177e4 | 772 | } else { |
28f65c11 | 773 | space_size = resource_size(&pbm->mem_space); |
1da177e4 LT |
774 | } |
775 | ||
776 | /* Make sure the request is in range. */ | |
777 | user_offset = vma->vm_pgoff << PAGE_SHIFT; | |
778 | user_size = vma->vm_end - vma->vm_start; | |
779 | ||
780 | if (user_offset >= space_size || | |
781 | (user_offset + user_size) > space_size) | |
782 | return -EINVAL; | |
783 | ||
3875c5c0 DM |
784 | if (mmap_state == pci_mmap_io) { |
785 | vma->vm_pgoff = (pbm->io_space.start + | |
786 | user_offset) >> PAGE_SHIFT; | |
1da177e4 | 787 | } else { |
3875c5c0 DM |
788 | vma->vm_pgoff = (pbm->mem_space.start + |
789 | user_offset) >> PAGE_SHIFT; | |
1da177e4 LT |
790 | } |
791 | ||
792 | return 0; | |
793 | } | |
794 | ||
bbe0b5eb DM |
795 | /* Adjust vm_pgoff of VMA such that it is the physical page offset |
796 | * corresponding to the 32-bit pci bus offset for DEV requested by the user. | |
1da177e4 LT |
797 | * |
798 | * Basically, the user finds the base address for his device which he wishes | |
799 | * to mmap. They read the 32-bit value from the config space base register, | |
800 | * add whatever PAGE_SIZE multiple offset they wish, and feed this into the | |
801 | * offset parameter of mmap on /proc/bus/pci/XXX for that device. | |
802 | * | |
803 | * Returns negative error code on failure, zero on success. | |
804 | */ | |
bbe0b5eb DM |
805 | static int __pci_mmap_make_offset(struct pci_dev *pdev, |
806 | struct vm_area_struct *vma, | |
1da177e4 LT |
807 | enum pci_mmap_state mmap_state) |
808 | { | |
bbe0b5eb DM |
809 | unsigned long user_paddr, user_size; |
810 | int i, err; | |
1da177e4 | 811 | |
bbe0b5eb DM |
812 | /* First compute the physical address in vma->vm_pgoff, |
813 | * making sure the user offset is within range in the | |
814 | * appropriate PCI space. | |
815 | */ | |
816 | err = __pci_mmap_make_offset_bus(pdev, vma, mmap_state); | |
817 | if (err) | |
818 | return err; | |
819 | ||
820 | /* If this is a mapping on a host bridge, any address | |
821 | * is OK. | |
822 | */ | |
823 | if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST) | |
824 | return err; | |
825 | ||
826 | /* Otherwise make sure it's in the range for one of the | |
827 | * device's resources. | |
828 | */ | |
829 | user_paddr = vma->vm_pgoff << PAGE_SHIFT; | |
830 | user_size = vma->vm_end - vma->vm_start; | |
1da177e4 | 831 | |
1da177e4 | 832 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { |
bbe0b5eb | 833 | struct resource *rp = &pdev->resource[i]; |
5769907a | 834 | resource_size_t aligned_end; |
1da177e4 LT |
835 | |
836 | /* Active? */ | |
837 | if (!rp->flags) | |
838 | continue; | |
839 | ||
840 | /* Same type? */ | |
841 | if (i == PCI_ROM_RESOURCE) { | |
842 | if (mmap_state != pci_mmap_mem) | |
843 | continue; | |
844 | } else { | |
845 | if ((mmap_state == pci_mmap_io && | |
846 | (rp->flags & IORESOURCE_IO) == 0) || | |
847 | (mmap_state == pci_mmap_mem && | |
848 | (rp->flags & IORESOURCE_MEM) == 0)) | |
849 | continue; | |
850 | } | |
851 | ||
5769907a MD |
852 | /* Align the resource end to the next page address. |
853 | * PAGE_SIZE intentionally added instead of (PAGE_SIZE - 1), | |
854 | * because actually we need the address of the next byte | |
855 | * after rp->end. | |
856 | */ | |
857 | aligned_end = (rp->end + PAGE_SIZE) & PAGE_MASK; | |
858 | ||
bbe0b5eb | 859 | if ((rp->start <= user_paddr) && |
5769907a | 860 | (user_paddr + user_size) <= aligned_end) |
bbe0b5eb | 861 | break; |
1da177e4 LT |
862 | } |
863 | ||
bbe0b5eb | 864 | if (i > PCI_ROM_RESOURCE) |
1da177e4 LT |
865 | return -EINVAL; |
866 | ||
1da177e4 LT |
867 | return 0; |
868 | } | |
869 | ||
870 | /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device | |
871 | * mapping. | |
872 | */ | |
873 | static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma, | |
874 | enum pci_mmap_state mmap_state) | |
875 | { | |
876 | vma->vm_flags |= (VM_IO | VM_RESERVED); | |
877 | } | |
878 | ||
879 | /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci | |
880 | * device mapping. | |
881 | */ | |
882 | static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma, | |
883 | enum pci_mmap_state mmap_state) | |
884 | { | |
a7a6cac2 | 885 | /* Our io_remap_pfn_range takes care of this, do nothing. */ |
1da177e4 LT |
886 | } |
887 | ||
888 | /* Perform the actual remap of the pages for a PCI device mapping, as appropriate | |
889 | * for this architecture. The region in the process to map is described by vm_start | |
890 | * and vm_end members of VMA, the base physical address is found in vm_pgoff. | |
891 | * The pci device structure is provided so that architectures may make mapping | |
892 | * decisions on a per-device or per-bus basis. | |
893 | * | |
894 | * Returns a negative error code on failure, zero on success. | |
895 | */ | |
896 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | |
897 | enum pci_mmap_state mmap_state, | |
898 | int write_combine) | |
899 | { | |
900 | int ret; | |
901 | ||
902 | ret = __pci_mmap_make_offset(dev, vma, mmap_state); | |
903 | if (ret < 0) | |
904 | return ret; | |
905 | ||
906 | __pci_mmap_set_flags(dev, vma, mmap_state); | |
907 | __pci_mmap_set_pgprot(dev, vma, mmap_state); | |
908 | ||
14778d90 | 909 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
1da177e4 LT |
910 | ret = io_remap_pfn_range(vma, vma->vm_start, |
911 | vma->vm_pgoff, | |
912 | vma->vm_end - vma->vm_start, | |
913 | vma->vm_page_prot); | |
914 | if (ret) | |
915 | return ret; | |
916 | ||
1da177e4 LT |
917 | return 0; |
918 | } | |
919 | ||
c1b1a5f1 DM |
920 | #ifdef CONFIG_NUMA |
921 | int pcibus_to_node(struct pci_bus *pbus) | |
922 | { | |
923 | struct pci_pbm_info *pbm = pbus->sysdata; | |
924 | ||
925 | return pbm->numa_node; | |
926 | } | |
927 | EXPORT_SYMBOL(pcibus_to_node); | |
928 | #endif | |
929 | ||
d3ae4b5b | 930 | /* Return the domain number for this pci bus */ |
1da177e4 LT |
931 | |
932 | int pci_domain_nr(struct pci_bus *pbus) | |
933 | { | |
934 | struct pci_pbm_info *pbm = pbus->sysdata; | |
935 | int ret; | |
936 | ||
d3ae4b5b | 937 | if (!pbm) { |
1da177e4 LT |
938 | ret = -ENXIO; |
939 | } else { | |
6c108f12 | 940 | ret = pbm->index; |
1da177e4 LT |
941 | } |
942 | ||
943 | return ret; | |
944 | } | |
945 | EXPORT_SYMBOL(pci_domain_nr); | |
946 | ||
35a17eb6 DM |
947 | #ifdef CONFIG_PCI_MSI |
948 | int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) | |
949 | { | |
a2fb23af | 950 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
44ed3c0c | 951 | unsigned int irq; |
35a17eb6 | 952 | |
e9870c4c | 953 | if (!pbm->setup_msi_irq) |
35a17eb6 DM |
954 | return -EINVAL; |
955 | ||
44ed3c0c | 956 | return pbm->setup_msi_irq(&irq, pdev, desc); |
35a17eb6 DM |
957 | } |
958 | ||
44ed3c0c | 959 | void arch_teardown_msi_irq(unsigned int irq) |
35a17eb6 | 960 | { |
394d441b | 961 | struct msi_desc *entry = irq_get_msi_desc(irq); |
35a17eb6 | 962 | struct pci_dev *pdev = entry->dev; |
a2fb23af | 963 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
35a17eb6 | 964 | |
77d10d0e | 965 | if (pbm->teardown_msi_irq) |
44ed3c0c | 966 | pbm->teardown_msi_irq(irq, pdev); |
35a17eb6 DM |
967 | } |
968 | #endif /* !(CONFIG_PCI_MSI) */ | |
969 | ||
ad7ad57c DM |
970 | static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit) |
971 | { | |
972 | struct pci_dev *ali_isa_bridge; | |
973 | u8 val; | |
974 | ||
975 | /* ALI sound chips generate 31-bits of DMA, a special register | |
976 | * determines what bit 31 is emitted as. | |
977 | */ | |
978 | ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL, | |
979 | PCI_DEVICE_ID_AL_M1533, | |
980 | NULL); | |
981 | ||
982 | pci_read_config_byte(ali_isa_bridge, 0x7e, &val); | |
983 | if (set_bit) | |
984 | val |= 0x01; | |
985 | else | |
986 | val &= ~0x01; | |
987 | pci_write_config_byte(ali_isa_bridge, 0x7e, val); | |
988 | pci_dev_put(ali_isa_bridge); | |
989 | } | |
990 | ||
ee664a92 | 991 | int pci64_dma_supported(struct pci_dev *pdev, u64 device_mask) |
ad7ad57c DM |
992 | { |
993 | u64 dma_addr_mask; | |
994 | ||
995 | if (pdev == NULL) { | |
996 | dma_addr_mask = 0xffffffff; | |
997 | } else { | |
998 | struct iommu *iommu = pdev->dev.archdata.iommu; | |
999 | ||
1000 | dma_addr_mask = iommu->dma_addr_mask; | |
1001 | ||
1002 | if (pdev->vendor == PCI_VENDOR_ID_AL && | |
1003 | pdev->device == PCI_DEVICE_ID_AL_M5451 && | |
1004 | device_mask == 0x7fffffff) { | |
1005 | ali_sound_dma_hack(pdev, | |
1006 | (dma_addr_mask & 0x80000000) != 0); | |
1007 | return 1; | |
1008 | } | |
1009 | } | |
1010 | ||
1011 | if (device_mask >= (1UL << 32UL)) | |
1012 | return 0; | |
1013 | ||
1014 | return (device_mask & dma_addr_mask) == dma_addr_mask; | |
1015 | } | |
1016 | ||
bcea1db1 DM |
1017 | void pci_resource_to_user(const struct pci_dev *pdev, int bar, |
1018 | const struct resource *rp, resource_size_t *start, | |
1019 | resource_size_t *end) | |
1020 | { | |
1021 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; | |
1022 | unsigned long offset; | |
1023 | ||
1024 | if (rp->flags & IORESOURCE_IO) | |
1025 | offset = pbm->io_space.start; | |
1026 | else | |
1027 | offset = pbm->mem_space.start; | |
1028 | ||
1029 | *start = rp->start - offset; | |
1030 | *end = rp->end - offset; | |
1031 | } | |
4c0eec7a | 1032 | |
ba232a1f MS |
1033 | void pcibios_set_master(struct pci_dev *dev) |
1034 | { | |
1035 | /* No special bus mastering setup handling */ | |
1036 | } | |
1037 | ||
4c0eec7a TH |
1038 | static int __init pcibios_init(void) |
1039 | { | |
1040 | pci_dfl_cache_line_size = 64 >> 2; | |
1041 | return 0; | |
1042 | } | |
1043 | subsys_initcall(pcibios_init); | |
2ef2d747 DM |
1044 | |
1045 | #ifdef CONFIG_SYSFS | |
1046 | static void __devinit pci_bus_slot_names(struct device_node *node, | |
1047 | struct pci_bus *bus) | |
1048 | { | |
1049 | const struct pci_slot_names { | |
1050 | u32 slot_mask; | |
1051 | char names[0]; | |
1052 | } *prop; | |
1053 | const char *sp; | |
1054 | int len, i; | |
1055 | u32 mask; | |
1056 | ||
1057 | prop = of_get_property(node, "slot-names", &len); | |
1058 | if (!prop) | |
1059 | return; | |
1060 | ||
1061 | mask = prop->slot_mask; | |
1062 | sp = prop->names; | |
1063 | ||
1064 | if (ofpci_verbose) | |
1065 | printk("PCI: Making slots for [%s] mask[0x%02x]\n", | |
1066 | node->full_name, mask); | |
1067 | ||
1068 | i = 0; | |
1069 | while (mask) { | |
1070 | struct pci_slot *pci_slot; | |
1071 | u32 this_bit = 1 << i; | |
1072 | ||
1073 | if (!(mask & this_bit)) { | |
1074 | i++; | |
1075 | continue; | |
1076 | } | |
1077 | ||
1078 | if (ofpci_verbose) | |
1079 | printk("PCI: Making slot [%s]\n", sp); | |
1080 | ||
1081 | pci_slot = pci_create_slot(bus, i, sp, NULL); | |
1082 | if (IS_ERR(pci_slot)) | |
1083 | printk(KERN_ERR "PCI: pci_create_slot returned %ld\n", | |
1084 | PTR_ERR(pci_slot)); | |
1085 | ||
1086 | sp += strlen(sp) + 1; | |
1087 | mask &= ~this_bit; | |
1088 | i++; | |
1089 | } | |
1090 | } | |
1091 | ||
1092 | static int __init of_pci_slot_init(void) | |
1093 | { | |
1094 | struct pci_bus *pbus = NULL; | |
1095 | ||
1096 | while ((pbus = pci_find_next_bus(pbus)) != NULL) { | |
1097 | struct device_node *node; | |
1098 | ||
1099 | if (pbus->self) { | |
2ef2d747 | 1100 | /* PCI->PCI bridge */ |
61c7a080 | 1101 | node = pbus->self->dev.of_node; |
2ef2d747 DM |
1102 | } else { |
1103 | struct pci_pbm_info *pbm = pbus->sysdata; | |
1104 | ||
1105 | /* Host PCI controller */ | |
61c7a080 | 1106 | node = pbm->op->dev.of_node; |
2ef2d747 DM |
1107 | } |
1108 | ||
1109 | pci_bus_slot_names(node, pbus); | |
1110 | } | |
1111 | ||
1112 | return 0; | |
1113 | } | |
1114 | ||
1115 | module_init(of_pci_slot_init); | |
1116 | #endif |