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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
d8650106 DH |
2 | /* |
3 | * leon_pci_grpci1.c: GRPCI1 Host PCI driver | |
4 | * | |
5 | * Copyright (C) 2013 Aeroflex Gaisler AB | |
6 | * | |
7 | * This GRPCI1 driver does not support PCI interrupts taken from | |
8 | * GPIO pins. Interrupt generation at PCI parity and system error | |
9 | * detection is by default turned off since some GRPCI1 cores does | |
10 | * not support detection. It can be turned on from the bootloader | |
11 | * using the all_pci_errors property. | |
12 | * | |
13 | * Contributors: Daniel Hellstrom <daniel@gaisler.com> | |
14 | */ | |
15 | ||
16 | #include <linux/of_device.h> | |
17 | #include <linux/export.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/of_irq.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/pci.h> | |
22 | ||
23 | #include <asm/leon_pci.h> | |
24 | #include <asm/sections.h> | |
25 | #include <asm/vaddrs.h> | |
26 | #include <asm/leon.h> | |
27 | #include <asm/io.h> | |
28 | ||
29 | #include "irq.h" | |
30 | ||
31 | /* Enable/Disable Debugging Configuration Space Access */ | |
32 | #undef GRPCI1_DEBUG_CFGACCESS | |
33 | ||
34 | /* | |
35 | * GRPCI1 APB Register MAP | |
36 | */ | |
37 | struct grpci1_regs { | |
38 | unsigned int cfg_stat; /* 0x00 Configuration / Status */ | |
39 | unsigned int bar0; /* 0x04 BAR0 (RO) */ | |
40 | unsigned int page0; /* 0x08 PAGE0 (RO) */ | |
41 | unsigned int bar1; /* 0x0C BAR1 (RO) */ | |
42 | unsigned int page1; /* 0x10 PAGE1 */ | |
43 | unsigned int iomap; /* 0x14 IO Map */ | |
44 | unsigned int stat_cmd; /* 0x18 PCI Status & Command (RO) */ | |
45 | unsigned int irq; /* 0x1C Interrupt register */ | |
46 | }; | |
47 | ||
48 | #define REGLOAD(a) (be32_to_cpu(__raw_readl(&(a)))) | |
49 | #define REGSTORE(a, v) (__raw_writel(cpu_to_be32(v), &(a))) | |
50 | ||
51 | #define PAGE0_BTEN_BIT 0 | |
52 | #define PAGE0_BTEN (1 << PAGE0_BTEN_BIT) | |
53 | ||
54 | #define CFGSTAT_HOST_BIT 13 | |
55 | #define CFGSTAT_CTO_BIT 8 | |
56 | #define CFGSTAT_HOST (1 << CFGSTAT_HOST_BIT) | |
57 | #define CFGSTAT_CTO (1 << CFGSTAT_CTO_BIT) | |
58 | ||
59 | #define IRQ_DPE (1 << 9) | |
60 | #define IRQ_SSE (1 << 8) | |
61 | #define IRQ_RMA (1 << 7) | |
62 | #define IRQ_RTA (1 << 6) | |
63 | #define IRQ_STA (1 << 5) | |
64 | #define IRQ_DPED (1 << 4) | |
65 | #define IRQ_INTD (1 << 3) | |
66 | #define IRQ_INTC (1 << 2) | |
67 | #define IRQ_INTB (1 << 1) | |
68 | #define IRQ_INTA (1 << 0) | |
69 | #define IRQ_DEF_ERRORS (IRQ_RMA | IRQ_RTA | IRQ_STA) | |
70 | #define IRQ_ALL_ERRORS (IRQ_DPED | IRQ_DEF_ERRORS | IRQ_SSE | IRQ_DPE) | |
71 | #define IRQ_INTX (IRQ_INTA | IRQ_INTB | IRQ_INTC | IRQ_INTD) | |
72 | #define IRQ_MASK_BIT 16 | |
73 | ||
74 | #define DEF_PCI_ERRORS (PCI_STATUS_SIG_TARGET_ABORT | \ | |
75 | PCI_STATUS_REC_TARGET_ABORT | \ | |
76 | PCI_STATUS_REC_MASTER_ABORT) | |
77 | #define ALL_PCI_ERRORS (PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY | \ | |
78 | PCI_STATUS_SIG_SYSTEM_ERROR | DEF_PCI_ERRORS) | |
79 | ||
80 | #define TGT 256 | |
81 | ||
82 | struct grpci1_priv { | |
83 | struct leon_pci_info info; /* must be on top of this structure */ | |
d65f0cd3 | 84 | struct grpci1_regs __iomem *regs; /* GRPCI register map */ |
d8650106 DH |
85 | struct device *dev; |
86 | int pci_err_mask; /* STATUS register error mask */ | |
87 | int irq; /* LEON irqctrl GRPCI IRQ */ | |
88 | unsigned char irq_map[4]; /* GRPCI nexus PCI INTX# IRQs */ | |
89 | unsigned int irq_err; /* GRPCI nexus Virt Error IRQ */ | |
90 | ||
91 | /* AHB PCI Windows */ | |
92 | unsigned long pci_area; /* MEMORY */ | |
93 | unsigned long pci_area_end; | |
94 | unsigned long pci_io; /* I/O */ | |
95 | unsigned long pci_conf; /* CONFIGURATION */ | |
96 | unsigned long pci_conf_end; | |
97 | unsigned long pci_io_va; | |
98 | }; | |
99 | ||
100 | static struct grpci1_priv *grpci1priv; | |
101 | ||
102 | static int grpci1_cfg_w32(struct grpci1_priv *priv, unsigned int bus, | |
103 | unsigned int devfn, int where, u32 val); | |
104 | ||
d65f0cd3 | 105 | static int grpci1_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
d8650106 DH |
106 | { |
107 | struct grpci1_priv *priv = dev->bus->sysdata; | |
108 | int irq_group; | |
109 | ||
110 | /* Use default IRQ decoding on PCI BUS0 according slot numbering */ | |
111 | irq_group = slot & 0x3; | |
112 | pin = ((pin - 1) + irq_group) & 0x3; | |
113 | ||
114 | return priv->irq_map[pin]; | |
115 | } | |
116 | ||
117 | static int grpci1_cfg_r32(struct grpci1_priv *priv, unsigned int bus, | |
118 | unsigned int devfn, int where, u32 *val) | |
119 | { | |
120 | u32 *pci_conf, tmp, cfg; | |
121 | ||
122 | if (where & 0x3) | |
123 | return -EINVAL; | |
124 | ||
125 | if (bus == 0) { | |
126 | devfn += (0x8 * 6); /* start at AD16=Device0 */ | |
127 | } else if (bus == TGT) { | |
128 | bus = 0; | |
129 | devfn = 0; /* special case: bridge controller itself */ | |
130 | } | |
131 | ||
132 | /* Select bus */ | |
133 | cfg = REGLOAD(priv->regs->cfg_stat); | |
134 | REGSTORE(priv->regs->cfg_stat, (cfg & ~(0xf << 23)) | (bus << 23)); | |
135 | ||
136 | /* do read access */ | |
137 | pci_conf = (u32 *) (priv->pci_conf | (devfn << 8) | (where & 0xfc)); | |
138 | tmp = LEON3_BYPASS_LOAD_PA(pci_conf); | |
139 | ||
140 | /* check if master abort was received */ | |
141 | if (REGLOAD(priv->regs->cfg_stat) & CFGSTAT_CTO) { | |
142 | *val = 0xffffffff; | |
143 | /* Clear Master abort bit in PCI cfg space (is set) */ | |
144 | tmp = REGLOAD(priv->regs->stat_cmd); | |
145 | grpci1_cfg_w32(priv, TGT, 0, PCI_COMMAND, tmp); | |
146 | } else { | |
147 | /* Bus always little endian (unaffected by byte-swapping) */ | |
01c6505d | 148 | *val = swab32(tmp); |
d8650106 DH |
149 | } |
150 | ||
151 | return 0; | |
152 | } | |
153 | ||
154 | static int grpci1_cfg_r16(struct grpci1_priv *priv, unsigned int bus, | |
155 | unsigned int devfn, int where, u32 *val) | |
156 | { | |
157 | u32 v; | |
158 | int ret; | |
159 | ||
160 | if (where & 0x1) | |
161 | return -EINVAL; | |
162 | ret = grpci1_cfg_r32(priv, bus, devfn, where & ~0x3, &v); | |
163 | *val = 0xffff & (v >> (8 * (where & 0x3))); | |
164 | return ret; | |
165 | } | |
166 | ||
167 | static int grpci1_cfg_r8(struct grpci1_priv *priv, unsigned int bus, | |
168 | unsigned int devfn, int where, u32 *val) | |
169 | { | |
170 | u32 v; | |
171 | int ret; | |
172 | ||
173 | ret = grpci1_cfg_r32(priv, bus, devfn, where & ~0x3, &v); | |
174 | *val = 0xff & (v >> (8 * (where & 3))); | |
175 | ||
176 | return ret; | |
177 | } | |
178 | ||
179 | static int grpci1_cfg_w32(struct grpci1_priv *priv, unsigned int bus, | |
180 | unsigned int devfn, int where, u32 val) | |
181 | { | |
182 | unsigned int *pci_conf; | |
183 | u32 cfg; | |
184 | ||
185 | if (where & 0x3) | |
186 | return -EINVAL; | |
187 | ||
188 | if (bus == 0) { | |
189 | devfn += (0x8 * 6); /* start at AD16=Device0 */ | |
190 | } else if (bus == TGT) { | |
191 | bus = 0; | |
192 | devfn = 0; /* special case: bridge controller itself */ | |
193 | } | |
194 | ||
195 | /* Select bus */ | |
196 | cfg = REGLOAD(priv->regs->cfg_stat); | |
197 | REGSTORE(priv->regs->cfg_stat, (cfg & ~(0xf << 23)) | (bus << 23)); | |
198 | ||
199 | pci_conf = (unsigned int *) (priv->pci_conf | | |
200 | (devfn << 8) | (where & 0xfc)); | |
01c6505d | 201 | LEON3_BYPASS_STORE_PA(pci_conf, swab32(val)); |
d8650106 DH |
202 | |
203 | return 0; | |
204 | } | |
205 | ||
206 | static int grpci1_cfg_w16(struct grpci1_priv *priv, unsigned int bus, | |
207 | unsigned int devfn, int where, u32 val) | |
208 | { | |
209 | int ret; | |
210 | u32 v; | |
211 | ||
212 | if (where & 0x1) | |
213 | return -EINVAL; | |
214 | ret = grpci1_cfg_r32(priv, bus, devfn, where&~3, &v); | |
215 | if (ret) | |
216 | return ret; | |
217 | v = (v & ~(0xffff << (8 * (where & 0x3)))) | | |
218 | ((0xffff & val) << (8 * (where & 0x3))); | |
219 | return grpci1_cfg_w32(priv, bus, devfn, where & ~0x3, v); | |
220 | } | |
221 | ||
222 | static int grpci1_cfg_w8(struct grpci1_priv *priv, unsigned int bus, | |
223 | unsigned int devfn, int where, u32 val) | |
224 | { | |
225 | int ret; | |
226 | u32 v; | |
227 | ||
228 | ret = grpci1_cfg_r32(priv, bus, devfn, where & ~0x3, &v); | |
229 | if (ret != 0) | |
230 | return ret; | |
231 | v = (v & ~(0xff << (8 * (where & 0x3)))) | | |
232 | ((0xff & val) << (8 * (where & 0x3))); | |
233 | return grpci1_cfg_w32(priv, bus, devfn, where & ~0x3, v); | |
234 | } | |
235 | ||
236 | /* Read from Configuration Space. When entering here the PCI layer has taken | |
237 | * the pci_lock spinlock and IRQ is off. | |
238 | */ | |
239 | static int grpci1_read_config(struct pci_bus *bus, unsigned int devfn, | |
240 | int where, int size, u32 *val) | |
241 | { | |
242 | struct grpci1_priv *priv = grpci1priv; | |
243 | unsigned int busno = bus->number; | |
244 | int ret; | |
245 | ||
246 | if (PCI_SLOT(devfn) > 15 || busno > 15) { | |
247 | *val = ~0; | |
248 | return 0; | |
249 | } | |
250 | ||
251 | switch (size) { | |
252 | case 1: | |
253 | ret = grpci1_cfg_r8(priv, busno, devfn, where, val); | |
254 | break; | |
255 | case 2: | |
256 | ret = grpci1_cfg_r16(priv, busno, devfn, where, val); | |
257 | break; | |
258 | case 4: | |
259 | ret = grpci1_cfg_r32(priv, busno, devfn, where, val); | |
260 | break; | |
261 | default: | |
262 | ret = -EINVAL; | |
263 | break; | |
264 | } | |
265 | ||
266 | #ifdef GRPCI1_DEBUG_CFGACCESS | |
267 | printk(KERN_INFO | |
268 | "grpci1_read_config: [%02x:%02x:%x] ofs=%d val=%x size=%d\n", | |
269 | busno, PCI_SLOT(devfn), PCI_FUNC(devfn), where, *val, size); | |
270 | #endif | |
271 | ||
272 | return ret; | |
273 | } | |
274 | ||
275 | /* Write to Configuration Space. When entering here the PCI layer has taken | |
276 | * the pci_lock spinlock and IRQ is off. | |
277 | */ | |
278 | static int grpci1_write_config(struct pci_bus *bus, unsigned int devfn, | |
279 | int where, int size, u32 val) | |
280 | { | |
281 | struct grpci1_priv *priv = grpci1priv; | |
282 | unsigned int busno = bus->number; | |
283 | ||
284 | if (PCI_SLOT(devfn) > 15 || busno > 15) | |
285 | return 0; | |
286 | ||
287 | #ifdef GRPCI1_DEBUG_CFGACCESS | |
288 | printk(KERN_INFO | |
289 | "grpci1_write_config: [%02x:%02x:%x] ofs=%d size=%d val=%x\n", | |
290 | busno, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val); | |
291 | #endif | |
292 | ||
293 | switch (size) { | |
294 | default: | |
295 | return -EINVAL; | |
296 | case 1: | |
297 | return grpci1_cfg_w8(priv, busno, devfn, where, val); | |
298 | case 2: | |
299 | return grpci1_cfg_w16(priv, busno, devfn, where, val); | |
300 | case 4: | |
301 | return grpci1_cfg_w32(priv, busno, devfn, where, val); | |
302 | } | |
303 | } | |
304 | ||
305 | static struct pci_ops grpci1_ops = { | |
306 | .read = grpci1_read_config, | |
307 | .write = grpci1_write_config, | |
308 | }; | |
309 | ||
310 | /* GENIRQ IRQ chip implementation for grpci1 irqmode=0..2. In configuration | |
311 | * 3 where all PCI Interrupts has a separate IRQ on the system IRQ controller | |
312 | * this is not needed and the standard IRQ controller can be used. | |
313 | */ | |
314 | ||
315 | static void grpci1_mask_irq(struct irq_data *data) | |
316 | { | |
317 | u32 irqidx; | |
318 | struct grpci1_priv *priv = grpci1priv; | |
319 | ||
320 | irqidx = (u32)data->chip_data - 1; | |
321 | if (irqidx > 3) /* only mask PCI interrupts here */ | |
322 | return; | |
323 | irqidx += IRQ_MASK_BIT; | |
324 | ||
325 | REGSTORE(priv->regs->irq, REGLOAD(priv->regs->irq) & ~(1 << irqidx)); | |
326 | } | |
327 | ||
328 | static void grpci1_unmask_irq(struct irq_data *data) | |
329 | { | |
330 | u32 irqidx; | |
331 | struct grpci1_priv *priv = grpci1priv; | |
332 | ||
333 | irqidx = (u32)data->chip_data - 1; | |
334 | if (irqidx > 3) /* only unmask PCI interrupts here */ | |
335 | return; | |
336 | irqidx += IRQ_MASK_BIT; | |
337 | ||
338 | REGSTORE(priv->regs->irq, REGLOAD(priv->regs->irq) | (1 << irqidx)); | |
339 | } | |
340 | ||
341 | static unsigned int grpci1_startup_irq(struct irq_data *data) | |
342 | { | |
343 | grpci1_unmask_irq(data); | |
344 | return 0; | |
345 | } | |
346 | ||
347 | static void grpci1_shutdown_irq(struct irq_data *data) | |
348 | { | |
349 | grpci1_mask_irq(data); | |
350 | } | |
351 | ||
352 | static struct irq_chip grpci1_irq = { | |
353 | .name = "grpci1", | |
354 | .irq_startup = grpci1_startup_irq, | |
355 | .irq_shutdown = grpci1_shutdown_irq, | |
356 | .irq_mask = grpci1_mask_irq, | |
357 | .irq_unmask = grpci1_unmask_irq, | |
358 | }; | |
359 | ||
360 | /* Handle one or multiple IRQs from the PCI core */ | |
bd0b9ac4 | 361 | static void grpci1_pci_flow_irq(struct irq_desc *desc) |
d8650106 DH |
362 | { |
363 | struct grpci1_priv *priv = grpci1priv; | |
364 | int i, ack = 0; | |
365 | unsigned int irqreg; | |
366 | ||
367 | irqreg = REGLOAD(priv->regs->irq); | |
368 | irqreg = (irqreg >> IRQ_MASK_BIT) & irqreg; | |
369 | ||
370 | /* Error Interrupt? */ | |
371 | if (irqreg & IRQ_ALL_ERRORS) { | |
372 | generic_handle_irq(priv->irq_err); | |
373 | ack = 1; | |
374 | } | |
375 | ||
376 | /* PCI Interrupt? */ | |
377 | if (irqreg & IRQ_INTX) { | |
378 | /* Call respective PCI Interrupt handler */ | |
379 | for (i = 0; i < 4; i++) { | |
380 | if (irqreg & (1 << i)) | |
381 | generic_handle_irq(priv->irq_map[i]); | |
382 | } | |
383 | ack = 1; | |
384 | } | |
385 | ||
386 | /* | |
387 | * Call "first level" IRQ chip end-of-irq handler. It will ACK LEON IRQ | |
388 | * Controller, this must be done after IRQ sources have been handled to | |
389 | * avoid double IRQ generation | |
390 | */ | |
391 | if (ack) | |
392 | desc->irq_data.chip->irq_eoi(&desc->irq_data); | |
393 | } | |
394 | ||
395 | /* Create a virtual IRQ */ | |
396 | static unsigned int grpci1_build_device_irq(unsigned int irq) | |
397 | { | |
398 | unsigned int virq = 0, pil; | |
399 | ||
400 | pil = 1 << 8; | |
401 | virq = irq_alloc(irq, pil); | |
402 | if (virq == 0) | |
403 | goto out; | |
404 | ||
405 | irq_set_chip_and_handler_name(virq, &grpci1_irq, handle_simple_irq, | |
406 | "pcilvl"); | |
407 | irq_set_chip_data(virq, (void *)irq); | |
408 | ||
409 | out: | |
410 | return virq; | |
411 | } | |
412 | ||
413 | /* | |
414 | * Initialize mappings AMBA<->PCI, clear IRQ state, setup PCI interface | |
415 | * | |
416 | * Target BARs: | |
417 | * BAR0: unused in this implementation | |
418 | * BAR1: peripheral DMA to host's memory (size at least 256MByte) | |
419 | * BAR2..BAR5: not implemented in hardware | |
420 | */ | |
d65f0cd3 | 421 | static void grpci1_hw_init(struct grpci1_priv *priv) |
d8650106 DH |
422 | { |
423 | u32 ahbadr, bar_sz, data, pciadr; | |
d65f0cd3 | 424 | struct grpci1_regs __iomem *regs = priv->regs; |
d8650106 DH |
425 | |
426 | /* set 1:1 mapping between AHB -> PCI memory space */ | |
427 | REGSTORE(regs->cfg_stat, priv->pci_area & 0xf0000000); | |
428 | ||
429 | /* map PCI accesses to target BAR1 to Linux kernel memory 1:1 */ | |
430 | ahbadr = 0xf0000000 & (u32)__pa(PAGE_ALIGN((unsigned long) &_end)); | |
431 | REGSTORE(regs->page1, ahbadr); | |
432 | ||
433 | /* translate I/O accesses to 0, I/O Space always @ PCI low 64Kbytes */ | |
434 | REGSTORE(regs->iomap, REGLOAD(regs->iomap) & 0x0000ffff); | |
435 | ||
436 | /* disable and clear pending interrupts */ | |
437 | REGSTORE(regs->irq, 0); | |
438 | ||
439 | /* Setup BAR0 outside access range so that it does not conflict with | |
440 | * peripheral DMA. There is no need to set up the PAGE0 register. | |
441 | */ | |
442 | grpci1_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0, 0xffffffff); | |
443 | grpci1_cfg_r32(priv, TGT, 0, PCI_BASE_ADDRESS_0, &bar_sz); | |
444 | bar_sz = ~bar_sz + 1; | |
445 | pciadr = priv->pci_area - bar_sz; | |
446 | grpci1_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0, pciadr); | |
447 | ||
448 | /* | |
449 | * Setup the Host's PCI Target BAR1 for other peripherals to access, | |
450 | * and do DMA to the host's memory. | |
451 | */ | |
452 | grpci1_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_1, ahbadr); | |
453 | ||
454 | /* | |
455 | * Setup Latency Timer and cache line size. Default cache line | |
456 | * size will result in poor performance (256 word fetches), 0xff | |
457 | * will set it according to the max size of the PCI FIFO. | |
458 | */ | |
459 | grpci1_cfg_w8(priv, TGT, 0, PCI_CACHE_LINE_SIZE, 0xff); | |
460 | grpci1_cfg_w8(priv, TGT, 0, PCI_LATENCY_TIMER, 0x40); | |
461 | ||
462 | /* set as bus master, enable pci memory responses, clear status bits */ | |
463 | grpci1_cfg_r32(priv, TGT, 0, PCI_COMMAND, &data); | |
464 | data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
465 | grpci1_cfg_w32(priv, TGT, 0, PCI_COMMAND, data); | |
466 | } | |
467 | ||
468 | static irqreturn_t grpci1_jump_interrupt(int irq, void *arg) | |
469 | { | |
470 | struct grpci1_priv *priv = arg; | |
471 | dev_err(priv->dev, "Jump IRQ happened\n"); | |
472 | return IRQ_NONE; | |
473 | } | |
474 | ||
475 | /* Handle GRPCI1 Error Interrupt */ | |
476 | static irqreturn_t grpci1_err_interrupt(int irq, void *arg) | |
477 | { | |
478 | struct grpci1_priv *priv = arg; | |
479 | u32 status; | |
480 | ||
481 | grpci1_cfg_r16(priv, TGT, 0, PCI_STATUS, &status); | |
482 | status &= priv->pci_err_mask; | |
483 | ||
484 | if (status == 0) | |
485 | return IRQ_NONE; | |
486 | ||
487 | if (status & PCI_STATUS_PARITY) | |
488 | dev_err(priv->dev, "Data Parity Error\n"); | |
489 | ||
490 | if (status & PCI_STATUS_SIG_TARGET_ABORT) | |
491 | dev_err(priv->dev, "Signalled Target Abort\n"); | |
492 | ||
493 | if (status & PCI_STATUS_REC_TARGET_ABORT) | |
494 | dev_err(priv->dev, "Received Target Abort\n"); | |
495 | ||
496 | if (status & PCI_STATUS_REC_MASTER_ABORT) | |
497 | dev_err(priv->dev, "Received Master Abort\n"); | |
498 | ||
499 | if (status & PCI_STATUS_SIG_SYSTEM_ERROR) | |
500 | dev_err(priv->dev, "Signalled System Error\n"); | |
501 | ||
502 | if (status & PCI_STATUS_DETECTED_PARITY) | |
503 | dev_err(priv->dev, "Parity Error\n"); | |
504 | ||
505 | /* Clear handled INT TYPE IRQs */ | |
506 | grpci1_cfg_w16(priv, TGT, 0, PCI_STATUS, status); | |
507 | ||
508 | return IRQ_HANDLED; | |
509 | } | |
510 | ||
511 | static int grpci1_of_probe(struct platform_device *ofdev) | |
512 | { | |
d65f0cd3 | 513 | struct grpci1_regs __iomem *regs; |
d8650106 DH |
514 | struct grpci1_priv *priv; |
515 | int err, len; | |
516 | const int *tmp; | |
517 | u32 cfg, size, err_mask; | |
518 | struct resource *res; | |
519 | ||
520 | if (grpci1priv) { | |
521 | dev_err(&ofdev->dev, "only one GRPCI1 supported\n"); | |
522 | return -ENODEV; | |
523 | } | |
524 | ||
525 | if (ofdev->num_resources < 3) { | |
526 | dev_err(&ofdev->dev, "not enough APB/AHB resources\n"); | |
527 | return -EIO; | |
528 | } | |
529 | ||
530 | priv = devm_kzalloc(&ofdev->dev, sizeof(*priv), GFP_KERNEL); | |
531 | if (!priv) { | |
532 | dev_err(&ofdev->dev, "memory allocation failed\n"); | |
533 | return -ENOMEM; | |
534 | } | |
535 | platform_set_drvdata(ofdev, priv); | |
536 | priv->dev = &ofdev->dev; | |
537 | ||
538 | /* find device register base address */ | |
539 | res = platform_get_resource(ofdev, IORESOURCE_MEM, 0); | |
f670758f TB |
540 | regs = devm_ioremap_resource(&ofdev->dev, res); |
541 | if (IS_ERR(regs)) | |
542 | return PTR_ERR(regs); | |
d8650106 DH |
543 | |
544 | /* | |
545 | * check that we're in Host Slot and that we can act as a Host Bridge | |
546 | * and not only as target/peripheral. | |
547 | */ | |
548 | cfg = REGLOAD(regs->cfg_stat); | |
549 | if ((cfg & CFGSTAT_HOST) == 0) { | |
550 | dev_err(&ofdev->dev, "not in host system slot\n"); | |
551 | return -EIO; | |
552 | } | |
553 | ||
554 | /* check that BAR1 support 256 MByte so that we can map kernel space */ | |
555 | REGSTORE(regs->page1, 0xffffffff); | |
556 | size = ~REGLOAD(regs->page1) + 1; | |
557 | if (size < 0x10000000) { | |
558 | dev_err(&ofdev->dev, "BAR1 must be at least 256MByte\n"); | |
559 | return -EIO; | |
560 | } | |
561 | ||
562 | /* hardware must support little-endian PCI (byte-twisting) */ | |
563 | if ((REGLOAD(regs->page0) & PAGE0_BTEN) == 0) { | |
564 | dev_err(&ofdev->dev, "byte-twisting is required\n"); | |
565 | return -EIO; | |
566 | } | |
567 | ||
568 | priv->regs = regs; | |
569 | priv->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0); | |
570 | dev_info(&ofdev->dev, "host found at 0x%p, irq%d\n", regs, priv->irq); | |
571 | ||
572 | /* Find PCI Memory, I/O and Configuration Space Windows */ | |
573 | priv->pci_area = ofdev->resource[1].start; | |
574 | priv->pci_area_end = ofdev->resource[1].end+1; | |
575 | priv->pci_io = ofdev->resource[2].start; | |
576 | priv->pci_conf = ofdev->resource[2].start + 0x10000; | |
577 | priv->pci_conf_end = priv->pci_conf + 0x10000; | |
578 | priv->pci_io_va = (unsigned long)ioremap(priv->pci_io, 0x10000); | |
579 | if (!priv->pci_io_va) { | |
580 | dev_err(&ofdev->dev, "unable to map PCI I/O area\n"); | |
581 | return -EIO; | |
582 | } | |
583 | ||
584 | printk(KERN_INFO | |
585 | "GRPCI1: MEMORY SPACE [0x%08lx - 0x%08lx]\n" | |
586 | " I/O SPACE [0x%08lx - 0x%08lx]\n" | |
587 | " CONFIG SPACE [0x%08lx - 0x%08lx]\n", | |
588 | priv->pci_area, priv->pci_area_end-1, | |
589 | priv->pci_io, priv->pci_conf-1, | |
590 | priv->pci_conf, priv->pci_conf_end-1); | |
591 | ||
592 | /* | |
593 | * I/O Space resources in I/O Window mapped into Virtual Adr Space | |
594 | * We never use low 4KB because some devices seem have problems using | |
595 | * address 0. | |
596 | */ | |
597 | priv->info.io_space.name = "GRPCI1 PCI I/O Space"; | |
598 | priv->info.io_space.start = priv->pci_io_va + 0x1000; | |
599 | priv->info.io_space.end = priv->pci_io_va + 0x10000 - 1; | |
600 | priv->info.io_space.flags = IORESOURCE_IO; | |
601 | ||
602 | /* | |
603 | * grpci1 has no prefetchable memory, map everything as | |
604 | * non-prefetchable memory | |
605 | */ | |
606 | priv->info.mem_space.name = "GRPCI1 PCI MEM Space"; | |
607 | priv->info.mem_space.start = priv->pci_area; | |
608 | priv->info.mem_space.end = priv->pci_area_end - 1; | |
609 | priv->info.mem_space.flags = IORESOURCE_MEM; | |
610 | ||
611 | if (request_resource(&iomem_resource, &priv->info.mem_space) < 0) { | |
612 | dev_err(&ofdev->dev, "unable to request PCI memory area\n"); | |
613 | err = -ENOMEM; | |
614 | goto err1; | |
615 | } | |
616 | ||
617 | if (request_resource(&ioport_resource, &priv->info.io_space) < 0) { | |
618 | dev_err(&ofdev->dev, "unable to request PCI I/O area\n"); | |
619 | err = -ENOMEM; | |
620 | goto err2; | |
621 | } | |
622 | ||
623 | /* setup maximum supported PCI buses */ | |
624 | priv->info.busn.name = "GRPCI1 busn"; | |
625 | priv->info.busn.start = 0; | |
626 | priv->info.busn.end = 15; | |
627 | ||
628 | grpci1priv = priv; | |
629 | ||
630 | /* Initialize hardware */ | |
631 | grpci1_hw_init(priv); | |
632 | ||
633 | /* | |
634 | * Get PCI Interrupt to System IRQ mapping and setup IRQ handling | |
635 | * Error IRQ. All PCI and PCI-Error interrupts are shared using the | |
636 | * same system IRQ. | |
637 | */ | |
638 | leon_update_virq_handling(priv->irq, grpci1_pci_flow_irq, "pcilvl", 0); | |
639 | ||
640 | priv->irq_map[0] = grpci1_build_device_irq(1); | |
641 | priv->irq_map[1] = grpci1_build_device_irq(2); | |
642 | priv->irq_map[2] = grpci1_build_device_irq(3); | |
643 | priv->irq_map[3] = grpci1_build_device_irq(4); | |
644 | priv->irq_err = grpci1_build_device_irq(5); | |
645 | ||
646 | printk(KERN_INFO " PCI INTA..D#: IRQ%d, IRQ%d, IRQ%d, IRQ%d\n", | |
647 | priv->irq_map[0], priv->irq_map[1], priv->irq_map[2], | |
648 | priv->irq_map[3]); | |
649 | ||
650 | /* Enable IRQs on LEON IRQ controller */ | |
651 | err = devm_request_irq(&ofdev->dev, priv->irq, grpci1_jump_interrupt, 0, | |
652 | "GRPCI1_JUMP", priv); | |
653 | if (err) { | |
654 | dev_err(&ofdev->dev, "ERR IRQ request failed: %d\n", err); | |
655 | goto err3; | |
656 | } | |
657 | ||
658 | /* Setup IRQ handler for access errors */ | |
659 | err = devm_request_irq(&ofdev->dev, priv->irq_err, | |
660 | grpci1_err_interrupt, IRQF_SHARED, "GRPCI1_ERR", | |
661 | priv); | |
662 | if (err) { | |
663 | dev_err(&ofdev->dev, "ERR VIRQ request failed: %d\n", err); | |
664 | goto err3; | |
665 | } | |
666 | ||
667 | tmp = of_get_property(ofdev->dev.of_node, "all_pci_errors", &len); | |
668 | if (tmp && (len == 4)) { | |
669 | priv->pci_err_mask = ALL_PCI_ERRORS; | |
670 | err_mask = IRQ_ALL_ERRORS << IRQ_MASK_BIT; | |
671 | } else { | |
672 | priv->pci_err_mask = DEF_PCI_ERRORS; | |
673 | err_mask = IRQ_DEF_ERRORS << IRQ_MASK_BIT; | |
674 | } | |
675 | ||
676 | /* | |
677 | * Enable Error Interrupts. PCI interrupts are unmasked once request_irq | |
678 | * is called by the PCI Device drivers | |
679 | */ | |
680 | REGSTORE(regs->irq, err_mask); | |
681 | ||
682 | /* Init common layer and scan buses */ | |
683 | priv->info.ops = &grpci1_ops; | |
684 | priv->info.map_irq = grpci1_map_irq; | |
685 | leon_pci_init(ofdev, &priv->info); | |
686 | ||
687 | return 0; | |
688 | ||
689 | err3: | |
690 | release_resource(&priv->info.io_space); | |
691 | err2: | |
692 | release_resource(&priv->info.mem_space); | |
693 | err1: | |
d65f0cd3 | 694 | iounmap((void __iomem *)priv->pci_io_va); |
d8650106 DH |
695 | grpci1priv = NULL; |
696 | return err; | |
697 | } | |
698 | ||
4154bb82 | 699 | static const struct of_device_id grpci1_of_match[] __initconst = { |
d8650106 DH |
700 | { |
701 | .name = "GAISLER_PCIFBRG", | |
702 | }, | |
703 | { | |
704 | .name = "01_014", | |
705 | }, | |
706 | {}, | |
707 | }; | |
708 | ||
709 | static struct platform_driver grpci1_of_driver = { | |
710 | .driver = { | |
711 | .name = "grpci1", | |
d8650106 DH |
712 | .of_match_table = grpci1_of_match, |
713 | }, | |
714 | .probe = grpci1_of_probe, | |
715 | }; | |
716 | ||
717 | static int __init grpci1_init(void) | |
718 | { | |
719 | return platform_driver_register(&grpci1_of_driver); | |
720 | } | |
721 | ||
722 | subsys_initcall(grpci1_init); |