Commit | Line | Data |
---|---|---|
4a907dec | 1 | /* irq.c: UltraSparc IRQ handling/init/registry. |
1da177e4 | 2 | * |
227c3311 | 3 | * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
4 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) |
5 | * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz) | |
6 | */ | |
7 | ||
1da177e4 | 8 | #include <linux/sched.h> |
9843099f | 9 | #include <linux/linkage.h> |
1da177e4 LT |
10 | #include <linux/ptrace.h> |
11 | #include <linux/errno.h> | |
12 | #include <linux/kernel_stat.h> | |
13 | #include <linux/signal.h> | |
14 | #include <linux/mm.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/random.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/proc_fs.h> | |
21 | #include <linux/seq_file.h> | |
9960e9e8 | 22 | #include <linux/ftrace.h> |
e18e2a00 | 23 | #include <linux/irq.h> |
2e2dc1d7 | 24 | #include <linux/kmemleak.h> |
1da177e4 LT |
25 | |
26 | #include <asm/ptrace.h> | |
27 | #include <asm/processor.h> | |
60063497 | 28 | #include <linux/atomic.h> |
1da177e4 | 29 | #include <asm/irq.h> |
2e457ef6 | 30 | #include <asm/io.h> |
1da177e4 LT |
31 | #include <asm/iommu.h> |
32 | #include <asm/upa.h> | |
33 | #include <asm/oplib.h> | |
25c7581b | 34 | #include <asm/prom.h> |
1da177e4 LT |
35 | #include <asm/timer.h> |
36 | #include <asm/smp.h> | |
37 | #include <asm/starfire.h> | |
38 | #include <asm/uaccess.h> | |
39 | #include <asm/cache.h> | |
40 | #include <asm/cpudata.h> | |
63b61452 | 41 | #include <asm/auxio.h> |
92704a1c | 42 | #include <asm/head.h> |
4a907dec | 43 | #include <asm/hypervisor.h> |
42d5f99b | 44 | #include <asm/cacheflush.h> |
1da177e4 | 45 | |
d91aa123 | 46 | #include "entry.h" |
280ff974 | 47 | #include "cpumap.h" |
ec687886 | 48 | #include "kstack.h" |
e18e2a00 DM |
49 | |
50 | #define NUM_IVECS (IMAP_INR + 1) | |
d91aa123 | 51 | |
10397e40 | 52 | struct ino_bucket *ivector_table; |
eb2d8d60 | 53 | unsigned long ivector_table_pa; |
1da177e4 | 54 | |
42d5f99b DM |
55 | /* On several sun4u processors, it is illegal to mix bypass and |
56 | * non-bypass accesses. Therefore we access all INO buckets | |
57 | * using bypass accesses only. | |
58 | */ | |
59 | static unsigned long bucket_get_chain_pa(unsigned long bucket_pa) | |
60 | { | |
61 | unsigned long ret; | |
62 | ||
63 | __asm__ __volatile__("ldxa [%1] %2, %0" | |
64 | : "=&r" (ret) | |
65 | : "r" (bucket_pa + | |
66 | offsetof(struct ino_bucket, | |
67 | __irq_chain_pa)), | |
68 | "i" (ASI_PHYS_USE_EC)); | |
69 | ||
70 | return ret; | |
71 | } | |
72 | ||
73 | static void bucket_clear_chain_pa(unsigned long bucket_pa) | |
74 | { | |
75 | __asm__ __volatile__("stxa %%g0, [%0] %1" | |
76 | : /* no outputs */ | |
77 | : "r" (bucket_pa + | |
78 | offsetof(struct ino_bucket, | |
79 | __irq_chain_pa)), | |
80 | "i" (ASI_PHYS_USE_EC)); | |
81 | } | |
82 | ||
fe41493f | 83 | static unsigned int bucket_get_irq(unsigned long bucket_pa) |
42d5f99b DM |
84 | { |
85 | unsigned int ret; | |
86 | ||
87 | __asm__ __volatile__("lduwa [%1] %2, %0" | |
88 | : "=&r" (ret) | |
89 | : "r" (bucket_pa + | |
90 | offsetof(struct ino_bucket, | |
fe41493f | 91 | __irq)), |
42d5f99b DM |
92 | "i" (ASI_PHYS_USE_EC)); |
93 | ||
94 | return ret; | |
95 | } | |
96 | ||
fe41493f | 97 | static void bucket_set_irq(unsigned long bucket_pa, unsigned int irq) |
42d5f99b DM |
98 | { |
99 | __asm__ __volatile__("stwa %0, [%1] %2" | |
100 | : /* no outputs */ | |
fe41493f | 101 | : "r" (irq), |
42d5f99b DM |
102 | "r" (bucket_pa + |
103 | offsetof(struct ino_bucket, | |
fe41493f | 104 | __irq)), |
42d5f99b DM |
105 | "i" (ASI_PHYS_USE_EC)); |
106 | } | |
107 | ||
eb2d8d60 | 108 | #define irq_work_pa(__cpu) &(trap_block[(__cpu)].irq_worklist_pa) |
1da177e4 | 109 | |
93b3238e | 110 | static struct { |
93b3238e DM |
111 | unsigned int dev_handle; |
112 | unsigned int dev_ino; | |
256c1df3 | 113 | unsigned int in_use; |
fe41493f SR |
114 | } irq_table[NR_IRQS]; |
115 | static DEFINE_SPINLOCK(irq_alloc_lock); | |
8047e247 | 116 | |
fe41493f | 117 | unsigned char irq_alloc(unsigned int dev_handle, unsigned int dev_ino) |
8047e247 | 118 | { |
759f89e0 | 119 | unsigned long flags; |
8047e247 DM |
120 | unsigned char ent; |
121 | ||
122 | BUILD_BUG_ON(NR_IRQS >= 256); | |
123 | ||
fe41493f | 124 | spin_lock_irqsave(&irq_alloc_lock, flags); |
759f89e0 | 125 | |
35a17eb6 | 126 | for (ent = 1; ent < NR_IRQS; ent++) { |
fe41493f | 127 | if (!irq_table[ent].in_use) |
35a17eb6 DM |
128 | break; |
129 | } | |
8047e247 DM |
130 | if (ent >= NR_IRQS) { |
131 | printk(KERN_ERR "IRQ: Out of virtual IRQs.\n"); | |
759f89e0 DM |
132 | ent = 0; |
133 | } else { | |
fe41493f SR |
134 | irq_table[ent].dev_handle = dev_handle; |
135 | irq_table[ent].dev_ino = dev_ino; | |
136 | irq_table[ent].in_use = 1; | |
8047e247 DM |
137 | } |
138 | ||
fe41493f | 139 | spin_unlock_irqrestore(&irq_alloc_lock, flags); |
8047e247 DM |
140 | |
141 | return ent; | |
142 | } | |
143 | ||
5746c99d | 144 | #ifdef CONFIG_PCI_MSI |
fe41493f | 145 | void irq_free(unsigned int irq) |
8047e247 | 146 | { |
759f89e0 | 147 | unsigned long flags; |
8047e247 | 148 | |
fe41493f | 149 | if (irq >= NR_IRQS) |
35a17eb6 DM |
150 | return; |
151 | ||
fe41493f | 152 | spin_lock_irqsave(&irq_alloc_lock, flags); |
759f89e0 | 153 | |
fe41493f | 154 | irq_table[irq].in_use = 0; |
35a17eb6 | 155 | |
fe41493f | 156 | spin_unlock_irqrestore(&irq_alloc_lock, flags); |
8047e247 | 157 | } |
5746c99d | 158 | #endif |
8047e247 | 159 | |
1da177e4 | 160 | /* |
e18e2a00 | 161 | * /proc/interrupts printing: |
1da177e4 | 162 | */ |
fa680c7c | 163 | int arch_show_interrupts(struct seq_file *p, int prec) |
1da177e4 | 164 | { |
fa680c7c | 165 | int j; |
e18e2a00 | 166 | |
fa680c7c TG |
167 | seq_printf(p, "NMI: "); |
168 | for_each_online_cpu(j) | |
169 | seq_printf(p, "%10u ", cpu_data(j).__nmi_count); | |
170 | seq_printf(p, " Non-maskable interrupts\n"); | |
1da177e4 LT |
171 | return 0; |
172 | } | |
173 | ||
ebd8c56c DM |
174 | static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid) |
175 | { | |
176 | unsigned int tid; | |
177 | ||
178 | if (this_is_starfire) { | |
179 | tid = starfire_translate(imap, cpuid); | |
180 | tid <<= IMAP_TID_SHIFT; | |
181 | tid &= IMAP_TID_UPA; | |
182 | } else { | |
183 | if (tlb_type == cheetah || tlb_type == cheetah_plus) { | |
184 | unsigned long ver; | |
185 | ||
186 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
187 | if ((ver >> 32UL) == __JALAPENO_ID || | |
188 | (ver >> 32UL) == __SERRANO_ID) { | |
189 | tid = cpuid << IMAP_TID_SHIFT; | |
190 | tid &= IMAP_TID_JBUS; | |
191 | } else { | |
192 | unsigned int a = cpuid & 0x1f; | |
193 | unsigned int n = (cpuid >> 5) & 0x1f; | |
194 | ||
195 | tid = ((a << IMAP_AID_SHIFT) | | |
196 | (n << IMAP_NID_SHIFT)); | |
197 | tid &= (IMAP_AID_SAFARI | | |
a419aef8 | 198 | IMAP_NID_SAFARI); |
ebd8c56c DM |
199 | } |
200 | } else { | |
201 | tid = cpuid << IMAP_TID_SHIFT; | |
202 | tid &= IMAP_TID_UPA; | |
203 | } | |
204 | } | |
205 | ||
206 | return tid; | |
207 | } | |
208 | ||
e18e2a00 DM |
209 | struct irq_handler_data { |
210 | unsigned long iclr; | |
211 | unsigned long imap; | |
8047e247 | 212 | |
e18e2a00 | 213 | void (*pre_handler)(unsigned int, void *, void *); |
8d57d3ad DM |
214 | void *arg1; |
215 | void *arg2; | |
e18e2a00 | 216 | }; |
1da177e4 | 217 | |
e18e2a00 | 218 | #ifdef CONFIG_SMP |
fe41493f | 219 | static int irq_choose_cpu(unsigned int irq, const struct cpumask *affinity) |
088dd1f8 | 220 | { |
e65e49d0 | 221 | cpumask_t mask; |
e18e2a00 | 222 | int cpuid; |
088dd1f8 | 223 | |
1091ce62 | 224 | cpumask_copy(&mask, affinity); |
fb1fece5 | 225 | if (cpumask_equal(&mask, cpu_online_mask)) { |
fe41493f | 226 | cpuid = map_to_cpu(irq); |
e18e2a00 DM |
227 | } else { |
228 | cpumask_t tmp; | |
088dd1f8 | 229 | |
fb1fece5 KM |
230 | cpumask_and(&tmp, cpu_online_mask, &mask); |
231 | cpuid = cpumask_empty(&tmp) ? map_to_cpu(irq) : cpumask_first(&tmp); | |
1da177e4 | 232 | } |
088dd1f8 | 233 | |
e18e2a00 DM |
234 | return cpuid; |
235 | } | |
236 | #else | |
fe41493f | 237 | #define irq_choose_cpu(irq, affinity) \ |
6abce771 | 238 | real_hard_smp_processor_id() |
e18e2a00 | 239 | #endif |
1da177e4 | 240 | |
4832b992 | 241 | static void sun4u_irq_enable(struct irq_data *data) |
e3999574 | 242 | { |
4832b992 | 243 | struct irq_handler_data *handler_data = data->handler_data; |
e3999574 | 244 | |
cae78728 | 245 | if (likely(handler_data)) { |
861fe906 | 246 | unsigned long cpuid, imap, val; |
e18e2a00 | 247 | unsigned int tid; |
e3999574 | 248 | |
4832b992 | 249 | cpuid = irq_choose_cpu(data->irq, data->affinity); |
cae78728 | 250 | imap = handler_data->imap; |
e3999574 | 251 | |
e18e2a00 | 252 | tid = sun4u_compute_tid(imap, cpuid); |
e3999574 | 253 | |
861fe906 DM |
254 | val = upa_readq(imap); |
255 | val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS | | |
256 | IMAP_AID_SAFARI | IMAP_NID_SAFARI); | |
257 | val |= tid | IMAP_VALID; | |
258 | upa_writeq(val, imap); | |
cae78728 | 259 | upa_writeq(ICLR_IDLE, handler_data->iclr); |
e3999574 | 260 | } |
e3999574 DM |
261 | } |
262 | ||
4832b992 SR |
263 | static int sun4u_set_affinity(struct irq_data *data, |
264 | const struct cpumask *mask, bool force) | |
b53bcb67 | 265 | { |
4832b992 | 266 | struct irq_handler_data *handler_data = data->handler_data; |
1091ce62 | 267 | |
cae78728 | 268 | if (likely(handler_data)) { |
1091ce62 DM |
269 | unsigned long cpuid, imap, val; |
270 | unsigned int tid; | |
271 | ||
4832b992 | 272 | cpuid = irq_choose_cpu(data->irq, mask); |
cae78728 | 273 | imap = handler_data->imap; |
1091ce62 DM |
274 | |
275 | tid = sun4u_compute_tid(imap, cpuid); | |
276 | ||
277 | val = upa_readq(imap); | |
278 | val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS | | |
279 | IMAP_AID_SAFARI | IMAP_NID_SAFARI); | |
280 | val |= tid | IMAP_VALID; | |
281 | upa_writeq(val, imap); | |
cae78728 | 282 | upa_writeq(ICLR_IDLE, handler_data->iclr); |
1091ce62 | 283 | } |
d5dedd45 YL |
284 | |
285 | return 0; | |
b53bcb67 DM |
286 | } |
287 | ||
d0cac39e DM |
288 | /* Don't do anything. The desc->status check for IRQ_DISABLED in |
289 | * handler_irq() will skip the handler call and that will leave the | |
290 | * interrupt in the sent state. The next ->enable() call will hit the | |
291 | * ICLR register to reset the state machine. | |
292 | * | |
293 | * This scheme is necessary, instead of clearing the Valid bit in the | |
294 | * IMAP register, to handle the case of IMAP registers being shared by | |
295 | * multiple INOs (and thus ICLR registers). Since we use a different | |
296 | * virtual IRQ for each shared IMAP instance, the generic code thinks | |
297 | * there is only one user so it prematurely calls ->disable() on | |
298 | * free_irq(). | |
299 | * | |
300 | * We have to provide an explicit ->disable() method instead of using | |
301 | * NULL to get the default. The reason is that if the generic code | |
302 | * sees that, it also hooks up a default ->shutdown method which | |
303 | * invokes ->mask() which we do not want. See irq_chip_set_defaults(). | |
304 | */ | |
4832b992 | 305 | static void sun4u_irq_disable(struct irq_data *data) |
1da177e4 | 306 | { |
088dd1f8 DM |
307 | } |
308 | ||
4832b992 | 309 | static void sun4u_irq_eoi(struct irq_data *data) |
088dd1f8 | 310 | { |
4832b992 | 311 | struct irq_handler_data *handler_data = data->handler_data; |
088dd1f8 | 312 | |
cae78728 SR |
313 | if (likely(handler_data)) |
314 | upa_writeq(ICLR_IDLE, handler_data->iclr); | |
088dd1f8 DM |
315 | } |
316 | ||
4832b992 | 317 | static void sun4v_irq_enable(struct irq_data *data) |
088dd1f8 | 318 | { |
fe41493f | 319 | unsigned int ino = irq_table[data->irq].dev_ino; |
4832b992 | 320 | unsigned long cpuid = irq_choose_cpu(data->irq, data->affinity); |
77182300 DM |
321 | int err; |
322 | ||
323 | err = sun4v_intr_settarget(ino, cpuid); | |
324 | if (err != HV_EOK) | |
325 | printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): " | |
326 | "err(%d)\n", ino, cpuid, err); | |
327 | err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); | |
328 | if (err != HV_EOK) | |
329 | printk(KERN_ERR "sun4v_intr_setstate(%x): " | |
330 | "err(%d)\n", ino, err); | |
331 | err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED); | |
332 | if (err != HV_EOK) | |
333 | printk(KERN_ERR "sun4v_intr_setenabled(%x): err(%d)\n", | |
334 | ino, err); | |
088dd1f8 DM |
335 | } |
336 | ||
4832b992 SR |
337 | static int sun4v_set_affinity(struct irq_data *data, |
338 | const struct cpumask *mask, bool force) | |
b53bcb67 | 339 | { |
fe41493f | 340 | unsigned int ino = irq_table[data->irq].dev_ino; |
4832b992 | 341 | unsigned long cpuid = irq_choose_cpu(data->irq, mask); |
77182300 DM |
342 | int err; |
343 | ||
344 | err = sun4v_intr_settarget(ino, cpuid); | |
345 | if (err != HV_EOK) | |
346 | printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): " | |
347 | "err(%d)\n", ino, cpuid, err); | |
d5dedd45 YL |
348 | |
349 | return 0; | |
b53bcb67 DM |
350 | } |
351 | ||
4832b992 | 352 | static void sun4v_irq_disable(struct irq_data *data) |
1da177e4 | 353 | { |
fe41493f | 354 | unsigned int ino = irq_table[data->irq].dev_ino; |
77182300 | 355 | int err; |
1da177e4 | 356 | |
77182300 DM |
357 | err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED); |
358 | if (err != HV_EOK) | |
359 | printk(KERN_ERR "sun4v_intr_setenabled(%x): " | |
360 | "err(%d)\n", ino, err); | |
e18e2a00 | 361 | } |
1da177e4 | 362 | |
4832b992 | 363 | static void sun4v_irq_eoi(struct irq_data *data) |
e18e2a00 | 364 | { |
fe41493f | 365 | unsigned int ino = irq_table[data->irq].dev_ino; |
77182300 | 366 | int err; |
5a606b72 | 367 | |
77182300 DM |
368 | err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); |
369 | if (err != HV_EOK) | |
370 | printk(KERN_ERR "sun4v_intr_setstate(%x): " | |
371 | "err(%d)\n", ino, err); | |
1da177e4 LT |
372 | } |
373 | ||
4832b992 | 374 | static void sun4v_virq_enable(struct irq_data *data) |
4a907dec | 375 | { |
77182300 DM |
376 | unsigned long cpuid, dev_handle, dev_ino; |
377 | int err; | |
378 | ||
4832b992 | 379 | cpuid = irq_choose_cpu(data->irq, data->affinity); |
77182300 | 380 | |
fe41493f SR |
381 | dev_handle = irq_table[data->irq].dev_handle; |
382 | dev_ino = irq_table[data->irq].dev_ino; | |
77182300 DM |
383 | |
384 | err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid); | |
385 | if (err != HV_EOK) | |
386 | printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): " | |
387 | "err(%d)\n", | |
388 | dev_handle, dev_ino, cpuid, err); | |
389 | err = sun4v_vintr_set_state(dev_handle, dev_ino, | |
390 | HV_INTR_STATE_IDLE); | |
391 | if (err != HV_EOK) | |
392 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," | |
393 | "HV_INTR_STATE_IDLE): err(%d)\n", | |
394 | dev_handle, dev_ino, err); | |
395 | err = sun4v_vintr_set_valid(dev_handle, dev_ino, | |
396 | HV_INTR_ENABLED); | |
397 | if (err != HV_EOK) | |
398 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," | |
399 | "HV_INTR_ENABLED): err(%d)\n", | |
400 | dev_handle, dev_ino, err); | |
4a907dec DM |
401 | } |
402 | ||
4832b992 SR |
403 | static int sun4v_virt_set_affinity(struct irq_data *data, |
404 | const struct cpumask *mask, bool force) | |
b53bcb67 | 405 | { |
77182300 DM |
406 | unsigned long cpuid, dev_handle, dev_ino; |
407 | int err; | |
b53bcb67 | 408 | |
4832b992 | 409 | cpuid = irq_choose_cpu(data->irq, mask); |
b53bcb67 | 410 | |
fe41493f SR |
411 | dev_handle = irq_table[data->irq].dev_handle; |
412 | dev_ino = irq_table[data->irq].dev_ino; | |
b53bcb67 | 413 | |
77182300 DM |
414 | err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid); |
415 | if (err != HV_EOK) | |
416 | printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): " | |
417 | "err(%d)\n", | |
418 | dev_handle, dev_ino, cpuid, err); | |
d5dedd45 YL |
419 | |
420 | return 0; | |
b53bcb67 DM |
421 | } |
422 | ||
4832b992 | 423 | static void sun4v_virq_disable(struct irq_data *data) |
4a907dec | 424 | { |
77182300 DM |
425 | unsigned long dev_handle, dev_ino; |
426 | int err; | |
427 | ||
fe41493f SR |
428 | dev_handle = irq_table[data->irq].dev_handle; |
429 | dev_ino = irq_table[data->irq].dev_ino; | |
77182300 DM |
430 | |
431 | err = sun4v_vintr_set_valid(dev_handle, dev_ino, | |
432 | HV_INTR_DISABLED); | |
433 | if (err != HV_EOK) | |
434 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," | |
435 | "HV_INTR_DISABLED): err(%d)\n", | |
436 | dev_handle, dev_ino, err); | |
4a907dec DM |
437 | } |
438 | ||
4832b992 | 439 | static void sun4v_virq_eoi(struct irq_data *data) |
4a907dec | 440 | { |
77182300 DM |
441 | unsigned long dev_handle, dev_ino; |
442 | int err; | |
5a606b72 | 443 | |
fe41493f SR |
444 | dev_handle = irq_table[data->irq].dev_handle; |
445 | dev_ino = irq_table[data->irq].dev_ino; | |
4a907dec | 446 | |
77182300 DM |
447 | err = sun4v_vintr_set_state(dev_handle, dev_ino, |
448 | HV_INTR_STATE_IDLE); | |
449 | if (err != HV_EOK) | |
450 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," | |
451 | "HV_INTR_STATE_IDLE): err(%d)\n", | |
452 | dev_handle, dev_ino, err); | |
4a907dec DM |
453 | } |
454 | ||
729e7d7e | 455 | static struct irq_chip sun4u_irq = { |
4832b992 SR |
456 | .name = "sun4u", |
457 | .irq_enable = sun4u_irq_enable, | |
458 | .irq_disable = sun4u_irq_disable, | |
459 | .irq_eoi = sun4u_irq_eoi, | |
460 | .irq_set_affinity = sun4u_set_affinity, | |
fcd8d4f4 | 461 | .flags = IRQCHIP_EOI_IF_HANDLED, |
e18e2a00 | 462 | }; |
088dd1f8 | 463 | |
729e7d7e | 464 | static struct irq_chip sun4v_irq = { |
4832b992 SR |
465 | .name = "sun4v", |
466 | .irq_enable = sun4v_irq_enable, | |
467 | .irq_disable = sun4v_irq_disable, | |
468 | .irq_eoi = sun4v_irq_eoi, | |
469 | .irq_set_affinity = sun4v_set_affinity, | |
fcd8d4f4 | 470 | .flags = IRQCHIP_EOI_IF_HANDLED, |
e18e2a00 | 471 | }; |
1da177e4 | 472 | |
4a907dec | 473 | static struct irq_chip sun4v_virq = { |
4832b992 SR |
474 | .name = "vsun4v", |
475 | .irq_enable = sun4v_virq_enable, | |
476 | .irq_disable = sun4v_virq_disable, | |
477 | .irq_eoi = sun4v_virq_eoi, | |
478 | .irq_set_affinity = sun4v_virt_set_affinity, | |
fcd8d4f4 | 479 | .flags = IRQCHIP_EOI_IF_HANDLED, |
4a907dec DM |
480 | }; |
481 | ||
fcd8d4f4 | 482 | static void pre_flow_handler(struct irq_data *d) |
8d57d3ad | 483 | { |
fcd8d4f4 TG |
484 | struct irq_handler_data *handler_data = irq_data_get_irq_handler_data(d); |
485 | unsigned int ino = irq_table[d->irq].dev_ino; | |
8d57d3ad | 486 | |
cae78728 | 487 | handler_data->pre_handler(ino, handler_data->arg1, handler_data->arg2); |
8d57d3ad DM |
488 | } |
489 | ||
fe41493f | 490 | void irq_install_pre_handler(int irq, |
e18e2a00 DM |
491 | void (*func)(unsigned int, void *, void *), |
492 | void *arg1, void *arg2) | |
493 | { | |
394d441b | 494 | struct irq_handler_data *handler_data = irq_get_handler_data(irq); |
088dd1f8 | 495 | |
cae78728 SR |
496 | handler_data->pre_handler = func; |
497 | handler_data->arg1 = arg1; | |
498 | handler_data->arg2 = arg2; | |
24ac26d4 | 499 | |
fcd8d4f4 | 500 | __irq_set_preflow_handler(irq, pre_flow_handler); |
e18e2a00 | 501 | } |
1da177e4 | 502 | |
e18e2a00 DM |
503 | unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap) |
504 | { | |
505 | struct ino_bucket *bucket; | |
cae78728 | 506 | struct irq_handler_data *handler_data; |
fe41493f | 507 | unsigned int irq; |
e18e2a00 | 508 | int ino; |
1da177e4 | 509 | |
e18e2a00 | 510 | BUG_ON(tlb_type == hypervisor); |
088dd1f8 | 511 | |
861fe906 | 512 | ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup; |
e18e2a00 | 513 | bucket = &ivector_table[ino]; |
fe41493f SR |
514 | irq = bucket_get_irq(__pa(bucket)); |
515 | if (!irq) { | |
516 | irq = irq_alloc(0, ino); | |
517 | bucket_set_irq(__pa(bucket), irq); | |
394d441b TG |
518 | irq_set_chip_and_handler_name(irq, &sun4u_irq, |
519 | handle_fasteoi_irq, "IVEC"); | |
fd0504c3 | 520 | } |
1da177e4 | 521 | |
394d441b | 522 | handler_data = irq_get_handler_data(irq); |
cae78728 | 523 | if (unlikely(handler_data)) |
e18e2a00 | 524 | goto out; |
fd0504c3 | 525 | |
cae78728 SR |
526 | handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
527 | if (unlikely(!handler_data)) { | |
e18e2a00 DM |
528 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); |
529 | prom_halt(); | |
1da177e4 | 530 | } |
394d441b | 531 | irq_set_handler_data(irq, handler_data); |
1da177e4 | 532 | |
cae78728 SR |
533 | handler_data->imap = imap; |
534 | handler_data->iclr = iclr; | |
1da177e4 | 535 | |
e18e2a00 | 536 | out: |
fe41493f | 537 | return irq; |
e18e2a00 | 538 | } |
1da177e4 | 539 | |
4a907dec DM |
540 | static unsigned int sun4v_build_common(unsigned long sysino, |
541 | struct irq_chip *chip) | |
1da177e4 | 542 | { |
8047e247 | 543 | struct ino_bucket *bucket; |
cae78728 | 544 | struct irq_handler_data *handler_data; |
fe41493f | 545 | unsigned int irq; |
8047e247 | 546 | |
e18e2a00 | 547 | BUG_ON(tlb_type != hypervisor); |
1da177e4 | 548 | |
e18e2a00 | 549 | bucket = &ivector_table[sysino]; |
fe41493f SR |
550 | irq = bucket_get_irq(__pa(bucket)); |
551 | if (!irq) { | |
552 | irq = irq_alloc(0, sysino); | |
553 | bucket_set_irq(__pa(bucket), irq); | |
394d441b | 554 | irq_set_chip_and_handler_name(irq, chip, handle_fasteoi_irq, |
8d57d3ad | 555 | "IVEC"); |
1da177e4 | 556 | } |
1da177e4 | 557 | |
394d441b | 558 | handler_data = irq_get_handler_data(irq); |
cae78728 | 559 | if (unlikely(handler_data)) |
1da177e4 | 560 | goto out; |
1da177e4 | 561 | |
cae78728 SR |
562 | handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
563 | if (unlikely(!handler_data)) { | |
e18e2a00 DM |
564 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); |
565 | prom_halt(); | |
566 | } | |
394d441b | 567 | irq_set_handler_data(irq, handler_data); |
1da177e4 | 568 | |
e18e2a00 DM |
569 | /* Catch accidental accesses to these things. IMAP/ICLR handling |
570 | * is done by hypervisor calls on sun4v platforms, not by direct | |
571 | * register accesses. | |
572 | */ | |
cae78728 SR |
573 | handler_data->imap = ~0UL; |
574 | handler_data->iclr = ~0UL; | |
1da177e4 | 575 | |
e18e2a00 | 576 | out: |
fe41493f | 577 | return irq; |
e18e2a00 | 578 | } |
1da177e4 | 579 | |
4a907dec DM |
580 | unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino) |
581 | { | |
582 | unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino); | |
583 | ||
584 | return sun4v_build_common(sysino, &sun4v_irq); | |
585 | } | |
586 | ||
587 | unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino) | |
588 | { | |
cae78728 | 589 | struct irq_handler_data *handler_data; |
b80e6998 | 590 | unsigned long hv_err, cookie; |
b7c2a757 | 591 | struct ino_bucket *bucket; |
fe41493f | 592 | unsigned int irq; |
b80e6998 DM |
593 | |
594 | bucket = kzalloc(sizeof(struct ino_bucket), GFP_ATOMIC); | |
595 | if (unlikely(!bucket)) | |
596 | return 0; | |
25ad403f DM |
597 | |
598 | /* The only reference we store to the IRQ bucket is | |
599 | * by physical address which kmemleak can't see, tell | |
600 | * it that this object explicitly is not a leak and | |
601 | * should be scanned. | |
602 | */ | |
603 | kmemleak_not_leak(bucket); | |
604 | ||
42d5f99b DM |
605 | __flush_dcache_range((unsigned long) bucket, |
606 | ((unsigned long) bucket + | |
607 | sizeof(struct ino_bucket))); | |
b80e6998 | 608 | |
fe41493f SR |
609 | irq = irq_alloc(devhandle, devino); |
610 | bucket_set_irq(__pa(bucket), irq); | |
8d57d3ad | 611 | |
394d441b | 612 | irq_set_chip_and_handler_name(irq, &sun4v_virq, handle_fasteoi_irq, |
8d57d3ad | 613 | "IVEC"); |
4a907dec | 614 | |
cae78728 SR |
615 | handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
616 | if (unlikely(!handler_data)) | |
b80e6998 | 617 | return 0; |
4a907dec | 618 | |
b7c2a757 DM |
619 | /* In order to make the LDC channel startup sequence easier, |
620 | * especially wrt. locking, we do not let request_irq() enable | |
621 | * the interrupt. | |
622 | */ | |
16741ea0 | 623 | irq_set_status_flags(irq, IRQ_NOAUTOEN); |
394d441b | 624 | irq_set_handler_data(irq, handler_data); |
4a907dec | 625 | |
b80e6998 DM |
626 | /* Catch accidental accesses to these things. IMAP/ICLR handling |
627 | * is done by hypervisor calls on sun4v platforms, not by direct | |
628 | * register accesses. | |
629 | */ | |
cae78728 SR |
630 | handler_data->imap = ~0UL; |
631 | handler_data->iclr = ~0UL; | |
b80e6998 DM |
632 | |
633 | cookie = ~__pa(bucket); | |
634 | hv_err = sun4v_vintr_set_cookie(devhandle, devino, cookie); | |
4a907dec DM |
635 | if (hv_err) { |
636 | prom_printf("IRQ: Fatal, cannot set cookie for [%x:%x] " | |
637 | "err=%lu\n", devhandle, devino, hv_err); | |
638 | prom_halt(); | |
639 | } | |
640 | ||
fe41493f | 641 | return irq; |
4a907dec DM |
642 | } |
643 | ||
fe41493f | 644 | void ack_bad_irq(unsigned int irq) |
e18e2a00 | 645 | { |
fe41493f | 646 | unsigned int ino = irq_table[irq].dev_ino; |
ab66a50e | 647 | |
77182300 DM |
648 | if (!ino) |
649 | ino = 0xdeadbeef; | |
6a76267f | 650 | |
fe41493f SR |
651 | printk(KERN_CRIT "Unexpected IRQ from ino[%x] irq[%u]\n", |
652 | ino, irq); | |
1da177e4 LT |
653 | } |
654 | ||
4f70f7a9 DM |
655 | void *hardirq_stack[NR_CPUS]; |
656 | void *softirq_stack[NR_CPUS]; | |
657 | ||
d4d1ec48 | 658 | void __irq_entry handler_irq(int pil, struct pt_regs *regs) |
1da177e4 | 659 | { |
eb2d8d60 | 660 | unsigned long pstate, bucket_pa; |
6d24c8dc | 661 | struct pt_regs *old_regs; |
4f70f7a9 | 662 | void *orig_sp; |
1da177e4 | 663 | |
d4d1ec48 | 664 | clear_softint(1 << pil); |
1da177e4 | 665 | |
6d24c8dc | 666 | old_regs = set_irq_regs(regs); |
1da177e4 | 667 | irq_enter(); |
1da177e4 | 668 | |
a650d383 DM |
669 | /* Grab an atomic snapshot of the pending IVECs. */ |
670 | __asm__ __volatile__("rdpr %%pstate, %0\n\t" | |
671 | "wrpr %0, %3, %%pstate\n\t" | |
672 | "ldx [%2], %1\n\t" | |
673 | "stx %%g0, [%2]\n\t" | |
674 | "wrpr %0, 0x0, %%pstate\n\t" | |
eb2d8d60 DM |
675 | : "=&r" (pstate), "=&r" (bucket_pa) |
676 | : "r" (irq_work_pa(smp_processor_id())), | |
a650d383 DM |
677 | "i" (PSTATE_IE) |
678 | : "memory"); | |
679 | ||
4f70f7a9 DM |
680 | orig_sp = set_hardirq_stack(); |
681 | ||
eb2d8d60 DM |
682 | while (bucket_pa) { |
683 | unsigned long next_pa; | |
fe41493f | 684 | unsigned int irq; |
1da177e4 | 685 | |
42d5f99b | 686 | next_pa = bucket_get_chain_pa(bucket_pa); |
fe41493f | 687 | irq = bucket_get_irq(bucket_pa); |
42d5f99b | 688 | bucket_clear_chain_pa(bucket_pa); |
fd0504c3 | 689 | |
fcd8d4f4 | 690 | generic_handle_irq(irq); |
eb2d8d60 DM |
691 | |
692 | bucket_pa = next_pa; | |
1da177e4 | 693 | } |
e18e2a00 | 694 | |
4f70f7a9 DM |
695 | restore_hardirq_stack(orig_sp); |
696 | ||
1da177e4 | 697 | irq_exit(); |
6d24c8dc | 698 | set_irq_regs(old_regs); |
1da177e4 LT |
699 | } |
700 | ||
7d65f4a6 | 701 | void do_softirq_own_stack(void) |
4f70f7a9 | 702 | { |
7d65f4a6 | 703 | void *orig_sp, *sp = softirq_stack[smp_processor_id()]; |
4f70f7a9 | 704 | |
7d65f4a6 | 705 | sp += THREAD_SIZE - 192 - STACK_BIAS; |
4f70f7a9 | 706 | |
7d65f4a6 FW |
707 | __asm__ __volatile__("mov %%sp, %0\n\t" |
708 | "mov %1, %%sp" | |
709 | : "=&r" (orig_sp) | |
710 | : "r" (sp)); | |
711 | __do_softirq(); | |
712 | __asm__ __volatile__("mov %0, %%sp" | |
713 | : : "r" (orig_sp)); | |
4f70f7a9 DM |
714 | } |
715 | ||
e0204409 DM |
716 | #ifdef CONFIG_HOTPLUG_CPU |
717 | void fixup_irqs(void) | |
718 | { | |
719 | unsigned int irq; | |
720 | ||
721 | for (irq = 0; irq < NR_IRQS; irq++) { | |
16741ea0 TG |
722 | struct irq_desc *desc = irq_to_desc(irq); |
723 | struct irq_data *data = irq_desc_get_irq_data(desc); | |
e0204409 DM |
724 | unsigned long flags; |
725 | ||
16741ea0 TG |
726 | raw_spin_lock_irqsave(&desc->lock, flags); |
727 | if (desc->action && !irqd_is_per_cpu(data)) { | |
4832b992 SR |
728 | if (data->chip->irq_set_affinity) |
729 | data->chip->irq_set_affinity(data, | |
16741ea0 TG |
730 | data->affinity, |
731 | false); | |
e0204409 | 732 | } |
16741ea0 | 733 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
e0204409 | 734 | } |
2eb2f779 DM |
735 | |
736 | tick_ops->disable_irq(); | |
e0204409 DM |
737 | } |
738 | #endif | |
739 | ||
cdd5186f DM |
740 | struct sun5_timer { |
741 | u64 count0; | |
742 | u64 limit0; | |
743 | u64 count1; | |
744 | u64 limit1; | |
745 | }; | |
1da177e4 | 746 | |
cdd5186f | 747 | static struct sun5_timer *prom_timers; |
1da177e4 LT |
748 | static u64 prom_limit0, prom_limit1; |
749 | ||
750 | static void map_prom_timers(void) | |
751 | { | |
25c7581b | 752 | struct device_node *dp; |
6a23acf3 | 753 | const unsigned int *addr; |
1da177e4 LT |
754 | |
755 | /* PROM timer node hangs out in the top level of device siblings... */ | |
25c7581b DM |
756 | dp = of_find_node_by_path("/"); |
757 | dp = dp->child; | |
758 | while (dp) { | |
759 | if (!strcmp(dp->name, "counter-timer")) | |
760 | break; | |
761 | dp = dp->sibling; | |
762 | } | |
1da177e4 LT |
763 | |
764 | /* Assume if node is not present, PROM uses different tick mechanism | |
765 | * which we should not care about. | |
766 | */ | |
25c7581b | 767 | if (!dp) { |
1da177e4 LT |
768 | prom_timers = (struct sun5_timer *) 0; |
769 | return; | |
770 | } | |
771 | ||
772 | /* If PROM is really using this, it must be mapped by him. */ | |
25c7581b DM |
773 | addr = of_get_property(dp, "address", NULL); |
774 | if (!addr) { | |
1da177e4 LT |
775 | prom_printf("PROM does not have timer mapped, trying to continue.\n"); |
776 | prom_timers = (struct sun5_timer *) 0; | |
777 | return; | |
778 | } | |
779 | prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]); | |
780 | } | |
781 | ||
782 | static void kill_prom_timer(void) | |
783 | { | |
784 | if (!prom_timers) | |
785 | return; | |
786 | ||
787 | /* Save them away for later. */ | |
788 | prom_limit0 = prom_timers->limit0; | |
789 | prom_limit1 = prom_timers->limit1; | |
790 | ||
ee906c9e | 791 | /* Just as in sun4c PROM uses timer which ticks at IRQ 14. |
1da177e4 LT |
792 | * We turn both off here just to be paranoid. |
793 | */ | |
794 | prom_timers->limit0 = 0; | |
795 | prom_timers->limit1 = 0; | |
796 | ||
797 | /* Wheee, eat the interrupt packet too... */ | |
798 | __asm__ __volatile__( | |
799 | " mov 0x40, %%g2\n" | |
800 | " ldxa [%%g0] %0, %%g1\n" | |
801 | " ldxa [%%g2] %1, %%g1\n" | |
802 | " stxa %%g0, [%%g0] %0\n" | |
803 | " membar #Sync\n" | |
804 | : /* no outputs */ | |
805 | : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R) | |
806 | : "g1", "g2"); | |
807 | } | |
808 | ||
9843099f | 809 | void notrace init_irqwork_curcpu(void) |
1da177e4 | 810 | { |
1da177e4 LT |
811 | int cpu = hard_smp_processor_id(); |
812 | ||
eb2d8d60 | 813 | trap_block[cpu].irq_worklist_pa = 0UL; |
1da177e4 LT |
814 | } |
815 | ||
5cbc3073 DM |
816 | /* Please be very careful with register_one_mondo() and |
817 | * sun4v_register_mondo_queues(). | |
818 | * | |
819 | * On SMP this gets invoked from the CPU trampoline before | |
820 | * the cpu has fully taken over the trap table from OBP, | |
821 | * and it's kernel stack + %g6 thread register state is | |
822 | * not fully cooked yet. | |
823 | * | |
824 | * Therefore you cannot make any OBP calls, not even prom_printf, | |
825 | * from these two routines. | |
826 | */ | |
2066aadd PG |
827 | static void notrace register_one_mondo(unsigned long paddr, unsigned long type, |
828 | unsigned long qmask) | |
ac29c11d | 829 | { |
5cbc3073 | 830 | unsigned long num_entries = (qmask + 1) / 64; |
94f8762d DM |
831 | unsigned long status; |
832 | ||
833 | status = sun4v_cpu_qconf(type, paddr, num_entries); | |
834 | if (status != HV_EOK) { | |
835 | prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, " | |
836 | "err %lu\n", type, paddr, num_entries, status); | |
ac29c11d DM |
837 | prom_halt(); |
838 | } | |
839 | } | |
840 | ||
2066aadd | 841 | void notrace sun4v_register_mondo_queues(int this_cpu) |
5b0c0572 | 842 | { |
b5a37e96 DM |
843 | struct trap_per_cpu *tb = &trap_block[this_cpu]; |
844 | ||
5cbc3073 DM |
845 | register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO, |
846 | tb->cpu_mondo_qmask); | |
847 | register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO, | |
848 | tb->dev_mondo_qmask); | |
849 | register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR, | |
850 | tb->resum_qmask); | |
851 | register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR, | |
852 | tb->nonresum_qmask); | |
b5a37e96 DM |
853 | } |
854 | ||
14a2ff6e DM |
855 | /* Each queue region must be a power of 2 multiple of 64 bytes in |
856 | * size. The base real address must be aligned to the size of the | |
857 | * region. Thus, an 8KB queue must be 8KB aligned, for example. | |
858 | */ | |
859 | static void __init alloc_one_queue(unsigned long *pa_ptr, unsigned long qmask) | |
b5a37e96 | 860 | { |
5cbc3073 | 861 | unsigned long size = PAGE_ALIGN(qmask + 1); |
14a2ff6e DM |
862 | unsigned long order = get_order(size); |
863 | unsigned long p; | |
5b0c0572 | 864 | |
14a2ff6e | 865 | p = __get_free_pages(GFP_KERNEL, order); |
5cbc3073 | 866 | if (!p) { |
14a2ff6e | 867 | prom_printf("SUN4V: Error, cannot allocate queue.\n"); |
5b0c0572 DM |
868 | prom_halt(); |
869 | } | |
870 | ||
5cbc3073 | 871 | *pa_ptr = __pa(p); |
5b0c0572 DM |
872 | } |
873 | ||
b434e719 | 874 | static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb) |
1d2f1f90 DM |
875 | { |
876 | #ifdef CONFIG_SMP | |
14a2ff6e | 877 | unsigned long page; |
1d2f1f90 DM |
878 | |
879 | BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64)); | |
880 | ||
14a2ff6e | 881 | page = get_zeroed_page(GFP_KERNEL); |
1d2f1f90 DM |
882 | if (!page) { |
883 | prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n"); | |
884 | prom_halt(); | |
885 | } | |
886 | ||
887 | tb->cpu_mondo_block_pa = __pa(page); | |
888 | tb->cpu_list_pa = __pa(page + 64); | |
889 | #endif | |
890 | } | |
891 | ||
b434e719 DM |
892 | /* Allocate mondo and error queues for all possible cpus. */ |
893 | static void __init sun4v_init_mondo_queues(void) | |
ac29c11d | 894 | { |
b434e719 | 895 | int cpu; |
ac29c11d | 896 | |
b434e719 DM |
897 | for_each_possible_cpu(cpu) { |
898 | struct trap_per_cpu *tb = &trap_block[cpu]; | |
1d2f1f90 | 899 | |
14a2ff6e DM |
900 | alloc_one_queue(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask); |
901 | alloc_one_queue(&tb->dev_mondo_pa, tb->dev_mondo_qmask); | |
902 | alloc_one_queue(&tb->resum_mondo_pa, tb->resum_qmask); | |
903 | alloc_one_queue(&tb->resum_kernel_buf_pa, tb->resum_qmask); | |
904 | alloc_one_queue(&tb->nonresum_mondo_pa, tb->nonresum_qmask); | |
905 | alloc_one_queue(&tb->nonresum_kernel_buf_pa, | |
906 | tb->nonresum_qmask); | |
43f58923 DM |
907 | } |
908 | } | |
909 | ||
910 | static void __init init_send_mondo_info(void) | |
911 | { | |
912 | int cpu; | |
913 | ||
914 | for_each_possible_cpu(cpu) { | |
915 | struct trap_per_cpu *tb = &trap_block[cpu]; | |
1d2f1f90 | 916 | |
b434e719 | 917 | init_cpu_send_mondo_info(tb); |
72aff53f | 918 | } |
ac29c11d DM |
919 | } |
920 | ||
e18e2a00 DM |
921 | static struct irqaction timer_irq_action = { |
922 | .name = "timer", | |
923 | }; | |
924 | ||
1da177e4 LT |
925 | /* Only invoked on boot processor. */ |
926 | void __init init_IRQ(void) | |
927 | { | |
10397e40 DM |
928 | unsigned long size; |
929 | ||
1da177e4 LT |
930 | map_prom_timers(); |
931 | kill_prom_timer(); | |
1da177e4 | 932 | |
10397e40 | 933 | size = sizeof(struct ino_bucket) * NUM_IVECS; |
14a2ff6e | 934 | ivector_table = kzalloc(size, GFP_KERNEL); |
10397e40 DM |
935 | if (!ivector_table) { |
936 | prom_printf("Fatal error, cannot allocate ivector_table\n"); | |
937 | prom_halt(); | |
938 | } | |
42d5f99b DM |
939 | __flush_dcache_range((unsigned long) ivector_table, |
940 | ((unsigned long) ivector_table) + size); | |
10397e40 DM |
941 | |
942 | ivector_table_pa = __pa(ivector_table); | |
eb2d8d60 | 943 | |
ac29c11d | 944 | if (tlb_type == hypervisor) |
b434e719 | 945 | sun4v_init_mondo_queues(); |
ac29c11d | 946 | |
43f58923 DM |
947 | init_send_mondo_info(); |
948 | ||
949 | if (tlb_type == hypervisor) { | |
950 | /* Load up the boot cpu's entries. */ | |
951 | sun4v_register_mondo_queues(hard_smp_processor_id()); | |
952 | } | |
953 | ||
1da177e4 LT |
954 | /* We need to clear any IRQ's pending in the soft interrupt |
955 | * registers, a spurious one could be left around from the | |
956 | * PROM timer which we just disabled. | |
957 | */ | |
958 | clear_softint(get_softint()); | |
959 | ||
960 | /* Now that ivector table is initialized, it is safe | |
961 | * to receive IRQ vector traps. We will normally take | |
962 | * one or two right now, in case some device PROM used | |
963 | * to boot us wants to speak to us. We just ignore them. | |
964 | */ | |
965 | __asm__ __volatile__("rdpr %%pstate, %%g1\n\t" | |
966 | "or %%g1, %0, %%g1\n\t" | |
967 | "wrpr %%g1, 0x0, %%pstate" | |
968 | : /* No outputs */ | |
969 | : "i" (PSTATE_IE) | |
970 | : "g1"); | |
1da177e4 | 971 | |
16741ea0 | 972 | irq_to_desc(0)->action = &timer_irq_action; |
1da177e4 | 973 | } |