Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
ad7ad57c | 2 | /* iommu.c: Generic sparc64 IOMMU support. |
1da177e4 | 3 | * |
d284142c | 4 | * Copyright (C) 1999, 2007, 2008 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
5 | * Copyright (C) 1999, 2000 Jakub Jelinek (jakub@redhat.com) |
6 | */ | |
7 | ||
8 | #include <linux/kernel.h> | |
066bcaca | 9 | #include <linux/export.h> |
5a0e3ad6 | 10 | #include <linux/slab.h> |
4dbc30fb | 11 | #include <linux/delay.h> |
ad7ad57c | 12 | #include <linux/device.h> |
0a0f0d8b | 13 | #include <linux/dma-map-ops.h> |
ad7ad57c | 14 | #include <linux/errno.h> |
d284142c | 15 | #include <linux/iommu-helper.h> |
a66022c4 | 16 | #include <linux/bitmap.h> |
0d3fdb15 | 17 | #include <asm/iommu-common.h> |
ad7ad57c DM |
18 | |
19 | #ifdef CONFIG_PCI | |
c57c2ffb | 20 | #include <linux/pci.h> |
ad7ad57c | 21 | #endif |
1da177e4 | 22 | |
ad7ad57c | 23 | #include <asm/iommu.h> |
1da177e4 LT |
24 | |
25 | #include "iommu_common.h" | |
4ac7b826 | 26 | #include "kernel.h" |
1da177e4 | 27 | |
ad7ad57c | 28 | #define STC_CTXMATCH_ADDR(STC, CTX) \ |
1da177e4 | 29 | ((STC)->strbuf_ctxmatch_base + ((CTX) << 3)) |
ad7ad57c DM |
30 | #define STC_FLUSHFLAG_INIT(STC) \ |
31 | (*((STC)->strbuf_flushflag) = 0UL) | |
32 | #define STC_FLUSHFLAG_SET(STC) \ | |
33 | (*((STC)->strbuf_flushflag) != 0UL) | |
1da177e4 | 34 | |
ad7ad57c | 35 | #define iommu_read(__reg) \ |
1da177e4 LT |
36 | ({ u64 __ret; \ |
37 | __asm__ __volatile__("ldxa [%1] %2, %0" \ | |
38 | : "=r" (__ret) \ | |
39 | : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \ | |
40 | : "memory"); \ | |
41 | __ret; \ | |
42 | }) | |
ad7ad57c | 43 | #define iommu_write(__reg, __val) \ |
1da177e4 LT |
44 | __asm__ __volatile__("stxa %0, [%1] %2" \ |
45 | : /* no outputs */ \ | |
46 | : "r" (__val), "r" (__reg), \ | |
47 | "i" (ASI_PHYS_BYPASS_EC_E)) | |
48 | ||
49 | /* Must be invoked under the IOMMU lock. */ | |
bb620c3d | 50 | static void iommu_flushall(struct iommu_map_table *iommu_map_table) |
1da177e4 | 51 | { |
bb620c3d | 52 | struct iommu *iommu = container_of(iommu_map_table, struct iommu, tbl); |
861fe906 | 53 | if (iommu->iommu_flushinv) { |
ad7ad57c | 54 | iommu_write(iommu->iommu_flushinv, ~(u64)0); |
861fe906 DM |
55 | } else { |
56 | unsigned long tag; | |
57 | int entry; | |
1da177e4 | 58 | |
ad7ad57c | 59 | tag = iommu->iommu_tags; |
861fe906 | 60 | for (entry = 0; entry < 16; entry++) { |
ad7ad57c | 61 | iommu_write(tag, 0); |
861fe906 DM |
62 | tag += 8; |
63 | } | |
1da177e4 | 64 | |
861fe906 | 65 | /* Ensure completion of previous PIO writes. */ |
ad7ad57c | 66 | (void) iommu_read(iommu->write_complete_reg); |
861fe906 | 67 | } |
1da177e4 LT |
68 | } |
69 | ||
70 | #define IOPTE_CONSISTENT(CTX) \ | |
71 | (IOPTE_VALID | IOPTE_CACHE | \ | |
72 | (((CTX) << 47) & IOPTE_CONTEXT)) | |
73 | ||
74 | #define IOPTE_STREAMING(CTX) \ | |
75 | (IOPTE_CONSISTENT(CTX) | IOPTE_STBUF) | |
76 | ||
77 | /* Existing mappings are never marked invalid, instead they | |
78 | * are pointed to a dummy page. | |
79 | */ | |
80 | #define IOPTE_IS_DUMMY(iommu, iopte) \ | |
81 | ((iopte_val(*iopte) & IOPTE_PAGE) == (iommu)->dummy_page_pa) | |
82 | ||
16ce82d8 | 83 | static inline void iopte_make_dummy(struct iommu *iommu, iopte_t *iopte) |
1da177e4 LT |
84 | { |
85 | unsigned long val = iopte_val(*iopte); | |
86 | ||
87 | val &= ~IOPTE_PAGE; | |
88 | val |= iommu->dummy_page_pa; | |
89 | ||
90 | iopte_val(*iopte) = val; | |
91 | } | |
92 | ||
ad7ad57c | 93 | int iommu_table_init(struct iommu *iommu, int tsbsize, |
c1b1a5f1 DM |
94 | u32 dma_offset, u32 dma_addr_mask, |
95 | int numa_node) | |
1da177e4 | 96 | { |
c1b1a5f1 DM |
97 | unsigned long i, order, sz, num_tsb_entries; |
98 | struct page *page; | |
688cb30b DM |
99 | |
100 | num_tsb_entries = tsbsize / sizeof(iopte_t); | |
51e85136 DM |
101 | |
102 | /* Setup initial software IOMMU state. */ | |
103 | spin_lock_init(&iommu->lock); | |
104 | iommu->ctx_lowest_free = 1; | |
bb620c3d | 105 | iommu->tbl.table_map_base = dma_offset; |
51e85136 DM |
106 | iommu->dma_addr_mask = dma_addr_mask; |
107 | ||
688cb30b DM |
108 | /* Allocate and initialize the free area map. */ |
109 | sz = num_tsb_entries / 8; | |
110 | sz = (sz + 7UL) & ~7UL; | |
86322ba9 | 111 | iommu->tbl.map = kzalloc_node(sz, GFP_KERNEL, numa_node); |
bb620c3d | 112 | if (!iommu->tbl.map) |
ad7ad57c | 113 | return -ENOMEM; |
f1600e54 | 114 | |
bb620c3d SV |
115 | iommu_tbl_pool_init(&iommu->tbl, num_tsb_entries, IO_PAGE_SHIFT, |
116 | (tlb_type != hypervisor ? iommu_flushall : NULL), | |
117 | false, 1, false); | |
d284142c | 118 | |
51e85136 DM |
119 | /* Allocate and initialize the dummy page which we |
120 | * set inactive IO PTEs to point to. | |
121 | */ | |
c1b1a5f1 DM |
122 | page = alloc_pages_node(numa_node, GFP_KERNEL, 0); |
123 | if (!page) { | |
ad7ad57c DM |
124 | printk(KERN_ERR "IOMMU: Error, gfp(dummy_page) failed.\n"); |
125 | goto out_free_map; | |
51e85136 | 126 | } |
c1b1a5f1 DM |
127 | iommu->dummy_page = (unsigned long) page_address(page); |
128 | memset((void *)iommu->dummy_page, 0, PAGE_SIZE); | |
51e85136 DM |
129 | iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page); |
130 | ||
131 | /* Now allocate and setup the IOMMU page table itself. */ | |
132 | order = get_order(tsbsize); | |
c1b1a5f1 DM |
133 | page = alloc_pages_node(numa_node, GFP_KERNEL, order); |
134 | if (!page) { | |
ad7ad57c DM |
135 | printk(KERN_ERR "IOMMU: Error, gfp(tsb) failed.\n"); |
136 | goto out_free_dummy_page; | |
51e85136 | 137 | } |
c1b1a5f1 | 138 | iommu->page_table = (iopte_t *)page_address(page); |
1da177e4 | 139 | |
688cb30b | 140 | for (i = 0; i < num_tsb_entries; i++) |
1da177e4 | 141 | iopte_make_dummy(iommu, &iommu->page_table[i]); |
ad7ad57c DM |
142 | |
143 | return 0; | |
144 | ||
145 | out_free_dummy_page: | |
146 | free_page(iommu->dummy_page); | |
147 | iommu->dummy_page = 0UL; | |
148 | ||
149 | out_free_map: | |
bb620c3d SV |
150 | kfree(iommu->tbl.map); |
151 | iommu->tbl.map = NULL; | |
ad7ad57c DM |
152 | |
153 | return -ENOMEM; | |
1da177e4 LT |
154 | } |
155 | ||
bb620c3d SV |
156 | static inline iopte_t *alloc_npages(struct device *dev, |
157 | struct iommu *iommu, | |
d284142c | 158 | unsigned long npages) |
1da177e4 | 159 | { |
d284142c | 160 | unsigned long entry; |
1da177e4 | 161 | |
bb620c3d SV |
162 | entry = iommu_tbl_range_alloc(dev, &iommu->tbl, npages, NULL, |
163 | (unsigned long)(-1), 0); | |
d618382b | 164 | if (unlikely(entry == IOMMU_ERROR_CODE)) |
688cb30b | 165 | return NULL; |
1da177e4 | 166 | |
688cb30b | 167 | return iommu->page_table + entry; |
1da177e4 LT |
168 | } |
169 | ||
16ce82d8 | 170 | static int iommu_alloc_ctx(struct iommu *iommu) |
7c963ad1 DM |
171 | { |
172 | int lowest = iommu->ctx_lowest_free; | |
711c71a0 | 173 | int n = find_next_zero_bit(iommu->ctx_bitmap, IOMMU_NUM_CTXS, lowest); |
7c963ad1 | 174 | |
711c71a0 | 175 | if (unlikely(n == IOMMU_NUM_CTXS)) { |
7c963ad1 DM |
176 | n = find_next_zero_bit(iommu->ctx_bitmap, lowest, 1); |
177 | if (unlikely(n == lowest)) { | |
178 | printk(KERN_WARNING "IOMMU: Ran out of contexts.\n"); | |
179 | n = 0; | |
180 | } | |
181 | } | |
182 | if (n) | |
183 | __set_bit(n, iommu->ctx_bitmap); | |
184 | ||
185 | return n; | |
186 | } | |
187 | ||
16ce82d8 | 188 | static inline void iommu_free_ctx(struct iommu *iommu, int ctx) |
7c963ad1 DM |
189 | { |
190 | if (likely(ctx)) { | |
191 | __clear_bit(ctx, iommu->ctx_bitmap); | |
192 | if (ctx < iommu->ctx_lowest_free) | |
193 | iommu->ctx_lowest_free = ctx; | |
194 | } | |
195 | } | |
196 | ||
ad7ad57c | 197 | static void *dma_4u_alloc_coherent(struct device *dev, size_t size, |
c416258a | 198 | dma_addr_t *dma_addrp, gfp_t gfp, |
00085f1e | 199 | unsigned long attrs) |
1da177e4 | 200 | { |
bb620c3d | 201 | unsigned long order, first_page; |
16ce82d8 | 202 | struct iommu *iommu; |
c1b1a5f1 DM |
203 | struct page *page; |
204 | int npages, nid; | |
1da177e4 | 205 | iopte_t *iopte; |
1da177e4 | 206 | void *ret; |
1da177e4 LT |
207 | |
208 | size = IO_PAGE_ALIGN(size); | |
209 | order = get_order(size); | |
210 | if (order >= 10) | |
211 | return NULL; | |
212 | ||
c1b1a5f1 DM |
213 | nid = dev->archdata.numa_node; |
214 | page = alloc_pages_node(nid, gfp, order); | |
215 | if (unlikely(!page)) | |
1da177e4 | 216 | return NULL; |
c1b1a5f1 DM |
217 | |
218 | first_page = (unsigned long) page_address(page); | |
1da177e4 LT |
219 | memset((char *)first_page, 0, PAGE_SIZE << order); |
220 | ||
ad7ad57c | 221 | iommu = dev->archdata.iommu; |
1da177e4 | 222 | |
d284142c | 223 | iopte = alloc_npages(dev, iommu, size >> IO_PAGE_SHIFT); |
688cb30b DM |
224 | |
225 | if (unlikely(iopte == NULL)) { | |
1da177e4 LT |
226 | free_pages(first_page, order); |
227 | return NULL; | |
228 | } | |
229 | ||
bb620c3d | 230 | *dma_addrp = (iommu->tbl.table_map_base + |
1da177e4 LT |
231 | ((iopte - iommu->page_table) << IO_PAGE_SHIFT)); |
232 | ret = (void *) first_page; | |
233 | npages = size >> IO_PAGE_SHIFT; | |
1da177e4 LT |
234 | first_page = __pa(first_page); |
235 | while (npages--) { | |
688cb30b | 236 | iopte_val(*iopte) = (IOPTE_CONSISTENT(0UL) | |
1da177e4 LT |
237 | IOPTE_WRITE | |
238 | (first_page & IOPTE_PAGE)); | |
239 | iopte++; | |
240 | first_page += IO_PAGE_SIZE; | |
241 | } | |
242 | ||
1da177e4 LT |
243 | return ret; |
244 | } | |
245 | ||
ad7ad57c | 246 | static void dma_4u_free_coherent(struct device *dev, size_t size, |
c416258a | 247 | void *cpu, dma_addr_t dvma, |
00085f1e | 248 | unsigned long attrs) |
1da177e4 | 249 | { |
16ce82d8 | 250 | struct iommu *iommu; |
bb620c3d | 251 | unsigned long order, npages; |
1da177e4 LT |
252 | |
253 | npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT; | |
ad7ad57c | 254 | iommu = dev->archdata.iommu; |
1da177e4 | 255 | |
d618382b | 256 | iommu_tbl_range_free(&iommu->tbl, dvma, npages, IOMMU_ERROR_CODE); |
1da177e4 LT |
257 | |
258 | order = get_order(size); | |
259 | if (order < 10) | |
260 | free_pages((unsigned long)cpu, order); | |
261 | } | |
262 | ||
797a7568 FT |
263 | static dma_addr_t dma_4u_map_page(struct device *dev, struct page *page, |
264 | unsigned long offset, size_t sz, | |
bc0a14f1 | 265 | enum dma_data_direction direction, |
00085f1e | 266 | unsigned long attrs) |
1da177e4 | 267 | { |
16ce82d8 DM |
268 | struct iommu *iommu; |
269 | struct strbuf *strbuf; | |
1da177e4 LT |
270 | iopte_t *base; |
271 | unsigned long flags, npages, oaddr; | |
272 | unsigned long i, base_paddr, ctx; | |
273 | u32 bus_addr, ret; | |
274 | unsigned long iopte_protection; | |
275 | ||
ad7ad57c DM |
276 | iommu = dev->archdata.iommu; |
277 | strbuf = dev->archdata.stc; | |
1da177e4 | 278 | |
ad7ad57c | 279 | if (unlikely(direction == DMA_NONE)) |
688cb30b | 280 | goto bad_no_ctx; |
1da177e4 | 281 | |
797a7568 | 282 | oaddr = (unsigned long)(page_address(page) + offset); |
1da177e4 LT |
283 | npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK); |
284 | npages >>= IO_PAGE_SHIFT; | |
285 | ||
c12f048f | 286 | base = alloc_npages(dev, iommu, npages); |
bb620c3d | 287 | spin_lock_irqsave(&iommu->lock, flags); |
688cb30b DM |
288 | ctx = 0; |
289 | if (iommu->iommu_ctxflush) | |
290 | ctx = iommu_alloc_ctx(iommu); | |
291 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1da177e4 | 292 | |
688cb30b | 293 | if (unlikely(!base)) |
1da177e4 | 294 | goto bad; |
688cb30b | 295 | |
bb620c3d | 296 | bus_addr = (iommu->tbl.table_map_base + |
1da177e4 LT |
297 | ((base - iommu->page_table) << IO_PAGE_SHIFT)); |
298 | ret = bus_addr | (oaddr & ~IO_PAGE_MASK); | |
299 | base_paddr = __pa(oaddr & IO_PAGE_MASK); | |
1da177e4 LT |
300 | if (strbuf->strbuf_enabled) |
301 | iopte_protection = IOPTE_STREAMING(ctx); | |
302 | else | |
303 | iopte_protection = IOPTE_CONSISTENT(ctx); | |
ad7ad57c | 304 | if (direction != DMA_TO_DEVICE) |
1da177e4 LT |
305 | iopte_protection |= IOPTE_WRITE; |
306 | ||
307 | for (i = 0; i < npages; i++, base++, base_paddr += IO_PAGE_SIZE) | |
308 | iopte_val(*base) = iopte_protection | base_paddr; | |
309 | ||
1da177e4 LT |
310 | return ret; |
311 | ||
312 | bad: | |
688cb30b DM |
313 | iommu_free_ctx(iommu, ctx); |
314 | bad_no_ctx: | |
315 | if (printk_ratelimit()) | |
316 | WARN_ON(1); | |
06301c5e | 317 | return DMA_MAPPING_ERROR; |
1da177e4 LT |
318 | } |
319 | ||
ad7ad57c DM |
320 | static void strbuf_flush(struct strbuf *strbuf, struct iommu *iommu, |
321 | u32 vaddr, unsigned long ctx, unsigned long npages, | |
322 | enum dma_data_direction direction) | |
4dbc30fb DM |
323 | { |
324 | int limit; | |
325 | ||
4dbc30fb DM |
326 | if (strbuf->strbuf_ctxflush && |
327 | iommu->iommu_ctxflush) { | |
328 | unsigned long matchreg, flushreg; | |
7c963ad1 | 329 | u64 val; |
4dbc30fb DM |
330 | |
331 | flushreg = strbuf->strbuf_ctxflush; | |
ad7ad57c | 332 | matchreg = STC_CTXMATCH_ADDR(strbuf, ctx); |
4dbc30fb | 333 | |
ad7ad57c DM |
334 | iommu_write(flushreg, ctx); |
335 | val = iommu_read(matchreg); | |
88314ee7 DM |
336 | val &= 0xffff; |
337 | if (!val) | |
7c963ad1 DM |
338 | goto do_flush_sync; |
339 | ||
7c963ad1 DM |
340 | while (val) { |
341 | if (val & 0x1) | |
ad7ad57c | 342 | iommu_write(flushreg, ctx); |
7c963ad1 | 343 | val >>= 1; |
a228dfd5 | 344 | } |
ad7ad57c | 345 | val = iommu_read(matchreg); |
7c963ad1 | 346 | if (unlikely(val)) { |
ad7ad57c | 347 | printk(KERN_WARNING "strbuf_flush: ctx flush " |
90181136 | 348 | "timeout matchreg[%llx] ctx[%lx]\n", |
7c963ad1 DM |
349 | val, ctx); |
350 | goto do_page_flush; | |
351 | } | |
4dbc30fb DM |
352 | } else { |
353 | unsigned long i; | |
354 | ||
7c963ad1 | 355 | do_page_flush: |
4dbc30fb | 356 | for (i = 0; i < npages; i++, vaddr += IO_PAGE_SIZE) |
ad7ad57c | 357 | iommu_write(strbuf->strbuf_pflush, vaddr); |
4dbc30fb DM |
358 | } |
359 | ||
7c963ad1 DM |
360 | do_flush_sync: |
361 | /* If the device could not have possibly put dirty data into | |
362 | * the streaming cache, no flush-flag synchronization needs | |
363 | * to be performed. | |
364 | */ | |
ad7ad57c | 365 | if (direction == DMA_TO_DEVICE) |
7c963ad1 DM |
366 | return; |
367 | ||
ad7ad57c DM |
368 | STC_FLUSHFLAG_INIT(strbuf); |
369 | iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa); | |
370 | (void) iommu_read(iommu->write_complete_reg); | |
4dbc30fb | 371 | |
a228dfd5 | 372 | limit = 100000; |
ad7ad57c | 373 | while (!STC_FLUSHFLAG_SET(strbuf)) { |
4dbc30fb DM |
374 | limit--; |
375 | if (!limit) | |
376 | break; | |
a228dfd5 | 377 | udelay(1); |
4f07118f | 378 | rmb(); |
4dbc30fb DM |
379 | } |
380 | if (!limit) | |
ad7ad57c | 381 | printk(KERN_WARNING "strbuf_flush: flushflag timeout " |
4dbc30fb DM |
382 | "vaddr[%08x] ctx[%lx] npages[%ld]\n", |
383 | vaddr, ctx, npages); | |
384 | } | |
385 | ||
797a7568 | 386 | static void dma_4u_unmap_page(struct device *dev, dma_addr_t bus_addr, |
bc0a14f1 | 387 | size_t sz, enum dma_data_direction direction, |
00085f1e | 388 | unsigned long attrs) |
1da177e4 | 389 | { |
16ce82d8 DM |
390 | struct iommu *iommu; |
391 | struct strbuf *strbuf; | |
1da177e4 | 392 | iopte_t *base; |
688cb30b | 393 | unsigned long flags, npages, ctx, i; |
1da177e4 | 394 | |
ad7ad57c | 395 | if (unlikely(direction == DMA_NONE)) { |
688cb30b DM |
396 | if (printk_ratelimit()) |
397 | WARN_ON(1); | |
398 | return; | |
399 | } | |
1da177e4 | 400 | |
ad7ad57c DM |
401 | iommu = dev->archdata.iommu; |
402 | strbuf = dev->archdata.stc; | |
1da177e4 LT |
403 | |
404 | npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK); | |
405 | npages >>= IO_PAGE_SHIFT; | |
406 | base = iommu->page_table + | |
bb620c3d | 407 | ((bus_addr - iommu->tbl.table_map_base) >> IO_PAGE_SHIFT); |
1da177e4 LT |
408 | bus_addr &= IO_PAGE_MASK; |
409 | ||
410 | spin_lock_irqsave(&iommu->lock, flags); | |
411 | ||
412 | /* Record the context, if any. */ | |
413 | ctx = 0; | |
414 | if (iommu->iommu_ctxflush) | |
415 | ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL; | |
416 | ||
417 | /* Step 1: Kick data out of streaming buffers if necessary. */ | |
68bbc28f | 418 | if (strbuf->strbuf_enabled && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) |
ad7ad57c DM |
419 | strbuf_flush(strbuf, iommu, bus_addr, ctx, |
420 | npages, direction); | |
1da177e4 | 421 | |
688cb30b DM |
422 | /* Step 2: Clear out TSB entries. */ |
423 | for (i = 0; i < npages; i++) | |
424 | iopte_make_dummy(iommu, base + i); | |
1da177e4 | 425 | |
7c963ad1 | 426 | iommu_free_ctx(iommu, ctx); |
c12f048f | 427 | spin_unlock_irqrestore(&iommu->lock, flags); |
bb620c3d | 428 | |
d618382b | 429 | iommu_tbl_range_free(&iommu->tbl, bus_addr, npages, IOMMU_ERROR_CODE); |
1da177e4 LT |
430 | } |
431 | ||
ad7ad57c | 432 | static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist, |
bc0a14f1 | 433 | int nelems, enum dma_data_direction direction, |
00085f1e | 434 | unsigned long attrs) |
1da177e4 | 435 | { |
13fa14e1 DM |
436 | struct scatterlist *s, *outs, *segstart; |
437 | unsigned long flags, handle, prot, ctx; | |
438 | dma_addr_t dma_next = 0, dma_addr; | |
439 | unsigned int max_seg_size; | |
f0880257 | 440 | unsigned long seg_boundary_size; |
13fa14e1 | 441 | int outcount, incount, i; |
16ce82d8 | 442 | struct strbuf *strbuf; |
38192d52 | 443 | struct iommu *iommu; |
f0880257 | 444 | unsigned long base_shift; |
13fa14e1 DM |
445 | |
446 | BUG_ON(direction == DMA_NONE); | |
1da177e4 | 447 | |
ad7ad57c DM |
448 | iommu = dev->archdata.iommu; |
449 | strbuf = dev->archdata.stc; | |
13fa14e1 | 450 | if (nelems == 0 || !iommu) |
e02373fd | 451 | return -EINVAL; |
1da177e4 LT |
452 | |
453 | spin_lock_irqsave(&iommu->lock, flags); | |
454 | ||
688cb30b DM |
455 | ctx = 0; |
456 | if (iommu->iommu_ctxflush) | |
457 | ctx = iommu_alloc_ctx(iommu); | |
458 | ||
1da177e4 | 459 | if (strbuf->strbuf_enabled) |
13fa14e1 | 460 | prot = IOPTE_STREAMING(ctx); |
1da177e4 | 461 | else |
13fa14e1 | 462 | prot = IOPTE_CONSISTENT(ctx); |
ad7ad57c | 463 | if (direction != DMA_TO_DEVICE) |
13fa14e1 DM |
464 | prot |= IOPTE_WRITE; |
465 | ||
466 | outs = s = segstart = &sglist[0]; | |
467 | outcount = 1; | |
468 | incount = nelems; | |
469 | handle = 0; | |
470 | ||
471 | /* Init first segment length for backout at failure */ | |
472 | outs->dma_length = 0; | |
473 | ||
474 | max_seg_size = dma_get_max_seg_size(dev); | |
1e9d90db | 475 | seg_boundary_size = dma_get_seg_boundary_nr_pages(dev, IO_PAGE_SHIFT); |
bb620c3d | 476 | base_shift = iommu->tbl.table_map_base >> IO_PAGE_SHIFT; |
13fa14e1 | 477 | for_each_sg(sglist, s, nelems, i) { |
f0880257 | 478 | unsigned long paddr, npages, entry, out_entry = 0, slen; |
13fa14e1 DM |
479 | iopte_t *base; |
480 | ||
481 | slen = s->length; | |
482 | /* Sanity check */ | |
483 | if (slen == 0) { | |
484 | dma_next = 0; | |
485 | continue; | |
486 | } | |
487 | /* Allocate iommu entries for that segment */ | |
488 | paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s); | |
0fcff28f | 489 | npages = iommu_num_pages(paddr, slen, IO_PAGE_SIZE); |
bb620c3d SV |
490 | entry = iommu_tbl_range_alloc(dev, &iommu->tbl, npages, |
491 | &handle, (unsigned long)(-1), 0); | |
13fa14e1 DM |
492 | |
493 | /* Handle failure */ | |
d618382b | 494 | if (unlikely(entry == IOMMU_ERROR_CODE)) { |
13fa14e1 DM |
495 | if (printk_ratelimit()) |
496 | printk(KERN_INFO "iommu_alloc failed, iommu %p paddr %lx" | |
497 | " npages %lx\n", iommu, paddr, npages); | |
498 | goto iommu_map_failed; | |
499 | } | |
688cb30b | 500 | |
13fa14e1 | 501 | base = iommu->page_table + entry; |
1da177e4 | 502 | |
13fa14e1 | 503 | /* Convert entry to a dma_addr_t */ |
bb620c3d | 504 | dma_addr = iommu->tbl.table_map_base + |
13fa14e1 DM |
505 | (entry << IO_PAGE_SHIFT); |
506 | dma_addr |= (s->offset & ~IO_PAGE_MASK); | |
38192d52 | 507 | |
13fa14e1 | 508 | /* Insert into HW table */ |
38192d52 | 509 | paddr &= IO_PAGE_MASK; |
13fa14e1 DM |
510 | while (npages--) { |
511 | iopte_val(*base) = prot | paddr; | |
38192d52 DM |
512 | base++; |
513 | paddr += IO_PAGE_SIZE; | |
38192d52 | 514 | } |
13fa14e1 DM |
515 | |
516 | /* If we are in an open segment, try merging */ | |
517 | if (segstart != s) { | |
518 | /* We cannot merge if: | |
519 | * - allocated dma_addr isn't contiguous to previous allocation | |
520 | */ | |
521 | if ((dma_addr != dma_next) || | |
f0880257 FT |
522 | (outs->dma_length + s->length > max_seg_size) || |
523 | (is_span_boundary(out_entry, base_shift, | |
524 | seg_boundary_size, outs, s))) { | |
13fa14e1 DM |
525 | /* Can't merge: create a new segment */ |
526 | segstart = s; | |
527 | outcount++; | |
528 | outs = sg_next(outs); | |
529 | } else { | |
530 | outs->dma_length += s->length; | |
531 | } | |
532 | } | |
533 | ||
534 | if (segstart == s) { | |
535 | /* This is a new segment, fill entries */ | |
536 | outs->dma_address = dma_addr; | |
537 | outs->dma_length = slen; | |
f0880257 | 538 | out_entry = entry; |
13fa14e1 DM |
539 | } |
540 | ||
541 | /* Calculate next page pointer for contiguous check */ | |
542 | dma_next = dma_addr + slen; | |
38192d52 DM |
543 | } |
544 | ||
13fa14e1 DM |
545 | spin_unlock_irqrestore(&iommu->lock, flags); |
546 | ||
547 | if (outcount < incount) { | |
548 | outs = sg_next(outs); | |
13fa14e1 DM |
549 | outs->dma_length = 0; |
550 | } | |
551 | ||
552 | return outcount; | |
553 | ||
554 | iommu_map_failed: | |
555 | for_each_sg(sglist, s, nelems, i) { | |
556 | if (s->dma_length != 0) { | |
6c830fef | 557 | unsigned long vaddr, npages, entry, j; |
13fa14e1 DM |
558 | iopte_t *base; |
559 | ||
560 | vaddr = s->dma_address & IO_PAGE_MASK; | |
0fcff28f JR |
561 | npages = iommu_num_pages(s->dma_address, s->dma_length, |
562 | IO_PAGE_SIZE); | |
13fa14e1 | 563 | |
bb620c3d | 564 | entry = (vaddr - iommu->tbl.table_map_base) |
13fa14e1 DM |
565 | >> IO_PAGE_SHIFT; |
566 | base = iommu->page_table + entry; | |
567 | ||
6c830fef DM |
568 | for (j = 0; j < npages; j++) |
569 | iopte_make_dummy(iommu, base + j); | |
13fa14e1 | 570 | |
bb620c3d | 571 | iommu_tbl_range_free(&iommu->tbl, vaddr, npages, |
d618382b | 572 | IOMMU_ERROR_CODE); |
bb620c3d | 573 | |
13fa14e1 DM |
574 | s->dma_length = 0; |
575 | } | |
576 | if (s == outs) | |
577 | break; | |
578 | } | |
579 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1da177e4 | 580 | |
e02373fd | 581 | return -EINVAL; |
1da177e4 LT |
582 | } |
583 | ||
13fa14e1 DM |
584 | /* If contexts are being used, they are the same in all of the mappings |
585 | * we make for a particular SG. | |
586 | */ | |
c12f048f | 587 | static unsigned long fetch_sg_ctx(struct iommu *iommu, struct scatterlist *sg) |
13fa14e1 DM |
588 | { |
589 | unsigned long ctx = 0; | |
590 | ||
591 | if (iommu->iommu_ctxflush) { | |
592 | iopte_t *base; | |
593 | u32 bus_addr; | |
bb620c3d | 594 | struct iommu_map_table *tbl = &iommu->tbl; |
13fa14e1 DM |
595 | |
596 | bus_addr = sg->dma_address & IO_PAGE_MASK; | |
597 | base = iommu->page_table + | |
bb620c3d | 598 | ((bus_addr - tbl->table_map_base) >> IO_PAGE_SHIFT); |
13fa14e1 DM |
599 | |
600 | ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL; | |
601 | } | |
602 | return ctx; | |
603 | } | |
604 | ||
ad7ad57c | 605 | static void dma_4u_unmap_sg(struct device *dev, struct scatterlist *sglist, |
bc0a14f1 | 606 | int nelems, enum dma_data_direction direction, |
00085f1e | 607 | unsigned long attrs) |
1da177e4 | 608 | { |
13fa14e1 DM |
609 | unsigned long flags, ctx; |
610 | struct scatterlist *sg; | |
16ce82d8 | 611 | struct strbuf *strbuf; |
38192d52 | 612 | struct iommu *iommu; |
1da177e4 | 613 | |
13fa14e1 | 614 | BUG_ON(direction == DMA_NONE); |
1da177e4 | 615 | |
ad7ad57c DM |
616 | iommu = dev->archdata.iommu; |
617 | strbuf = dev->archdata.stc; | |
618 | ||
13fa14e1 | 619 | ctx = fetch_sg_ctx(iommu, sglist); |
1da177e4 | 620 | |
13fa14e1 | 621 | spin_lock_irqsave(&iommu->lock, flags); |
1da177e4 | 622 | |
13fa14e1 DM |
623 | sg = sglist; |
624 | while (nelems--) { | |
625 | dma_addr_t dma_handle = sg->dma_address; | |
626 | unsigned int len = sg->dma_length; | |
627 | unsigned long npages, entry; | |
628 | iopte_t *base; | |
629 | int i; | |
1da177e4 | 630 | |
13fa14e1 DM |
631 | if (!len) |
632 | break; | |
0fcff28f | 633 | npages = iommu_num_pages(dma_handle, len, IO_PAGE_SIZE); |
1da177e4 | 634 | |
bb620c3d | 635 | entry = ((dma_handle - iommu->tbl.table_map_base) |
13fa14e1 DM |
636 | >> IO_PAGE_SHIFT); |
637 | base = iommu->page_table + entry; | |
1da177e4 | 638 | |
13fa14e1 | 639 | dma_handle &= IO_PAGE_MASK; |
68bbc28f | 640 | if (strbuf->strbuf_enabled && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) |
13fa14e1 DM |
641 | strbuf_flush(strbuf, iommu, dma_handle, ctx, |
642 | npages, direction); | |
1da177e4 | 643 | |
13fa14e1 DM |
644 | for (i = 0; i < npages; i++) |
645 | iopte_make_dummy(iommu, base + i); | |
1da177e4 | 646 | |
bb620c3d | 647 | iommu_tbl_range_free(&iommu->tbl, dma_handle, npages, |
d618382b | 648 | IOMMU_ERROR_CODE); |
13fa14e1 DM |
649 | sg = sg_next(sg); |
650 | } | |
1da177e4 | 651 | |
7c963ad1 DM |
652 | iommu_free_ctx(iommu, ctx); |
653 | ||
1da177e4 LT |
654 | spin_unlock_irqrestore(&iommu->lock, flags); |
655 | } | |
656 | ||
ad7ad57c DM |
657 | static void dma_4u_sync_single_for_cpu(struct device *dev, |
658 | dma_addr_t bus_addr, size_t sz, | |
659 | enum dma_data_direction direction) | |
1da177e4 | 660 | { |
16ce82d8 DM |
661 | struct iommu *iommu; |
662 | struct strbuf *strbuf; | |
1da177e4 LT |
663 | unsigned long flags, ctx, npages; |
664 | ||
ad7ad57c DM |
665 | iommu = dev->archdata.iommu; |
666 | strbuf = dev->archdata.stc; | |
1da177e4 LT |
667 | |
668 | if (!strbuf->strbuf_enabled) | |
669 | return; | |
670 | ||
671 | spin_lock_irqsave(&iommu->lock, flags); | |
672 | ||
673 | npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK); | |
674 | npages >>= IO_PAGE_SHIFT; | |
675 | bus_addr &= IO_PAGE_MASK; | |
676 | ||
677 | /* Step 1: Record the context, if any. */ | |
678 | ctx = 0; | |
679 | if (iommu->iommu_ctxflush && | |
680 | strbuf->strbuf_ctxflush) { | |
681 | iopte_t *iopte; | |
bb620c3d | 682 | struct iommu_map_table *tbl = &iommu->tbl; |
1da177e4 LT |
683 | |
684 | iopte = iommu->page_table + | |
bb620c3d | 685 | ((bus_addr - tbl->table_map_base)>>IO_PAGE_SHIFT); |
1da177e4 LT |
686 | ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL; |
687 | } | |
688 | ||
689 | /* Step 2: Kick data out of streaming buffers. */ | |
ad7ad57c | 690 | strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction); |
1da177e4 LT |
691 | |
692 | spin_unlock_irqrestore(&iommu->lock, flags); | |
693 | } | |
694 | ||
ad7ad57c DM |
695 | static void dma_4u_sync_sg_for_cpu(struct device *dev, |
696 | struct scatterlist *sglist, int nelems, | |
697 | enum dma_data_direction direction) | |
1da177e4 | 698 | { |
16ce82d8 DM |
699 | struct iommu *iommu; |
700 | struct strbuf *strbuf; | |
4dbc30fb | 701 | unsigned long flags, ctx, npages, i; |
2c941a20 | 702 | struct scatterlist *sg, *sgprv; |
4dbc30fb | 703 | u32 bus_addr; |
1da177e4 | 704 | |
ad7ad57c DM |
705 | iommu = dev->archdata.iommu; |
706 | strbuf = dev->archdata.stc; | |
1da177e4 LT |
707 | |
708 | if (!strbuf->strbuf_enabled) | |
709 | return; | |
710 | ||
711 | spin_lock_irqsave(&iommu->lock, flags); | |
712 | ||
713 | /* Step 1: Record the context, if any. */ | |
714 | ctx = 0; | |
715 | if (iommu->iommu_ctxflush && | |
716 | strbuf->strbuf_ctxflush) { | |
717 | iopte_t *iopte; | |
bb620c3d | 718 | struct iommu_map_table *tbl = &iommu->tbl; |
1da177e4 | 719 | |
bb620c3d SV |
720 | iopte = iommu->page_table + ((sglist[0].dma_address - |
721 | tbl->table_map_base) >> IO_PAGE_SHIFT); | |
1da177e4 LT |
722 | ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL; |
723 | } | |
724 | ||
725 | /* Step 2: Kick data out of streaming buffers. */ | |
4dbc30fb | 726 | bus_addr = sglist[0].dma_address & IO_PAGE_MASK; |
2c941a20 JA |
727 | sgprv = NULL; |
728 | for_each_sg(sglist, sg, nelems, i) { | |
729 | if (sg->dma_length == 0) | |
4dbc30fb | 730 | break; |
2c941a20 JA |
731 | sgprv = sg; |
732 | } | |
733 | ||
734 | npages = (IO_PAGE_ALIGN(sgprv->dma_address + sgprv->dma_length) | |
4dbc30fb | 735 | - bus_addr) >> IO_PAGE_SHIFT; |
ad7ad57c | 736 | strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction); |
1da177e4 LT |
737 | |
738 | spin_unlock_irqrestore(&iommu->lock, flags); | |
739 | } | |
740 | ||
b02c2b0b CH |
741 | static int dma_4u_supported(struct device *dev, u64 device_mask) |
742 | { | |
743 | struct iommu *iommu = dev->archdata.iommu; | |
744 | ||
c54fc984 CH |
745 | if (ali_sound_dma_hack(dev, device_mask)) |
746 | return 1; | |
747 | ||
254ecb16 | 748 | if (device_mask < iommu->dma_addr_mask) |
b02c2b0b | 749 | return 0; |
254ecb16 | 750 | return 1; |
b02c2b0b CH |
751 | } |
752 | ||
5299709d | 753 | static const struct dma_map_ops sun4u_dma_ops = { |
c416258a AP |
754 | .alloc = dma_4u_alloc_coherent, |
755 | .free = dma_4u_free_coherent, | |
797a7568 FT |
756 | .map_page = dma_4u_map_page, |
757 | .unmap_page = dma_4u_unmap_page, | |
ad7ad57c DM |
758 | .map_sg = dma_4u_map_sg, |
759 | .unmap_sg = dma_4u_unmap_sg, | |
760 | .sync_single_for_cpu = dma_4u_sync_single_for_cpu, | |
761 | .sync_sg_for_cpu = dma_4u_sync_sg_for_cpu, | |
b02c2b0b | 762 | .dma_supported = dma_4u_supported, |
8f6a93a1 DM |
763 | }; |
764 | ||
5299709d | 765 | const struct dma_map_ops *dma_ops = &sun4u_dma_ops; |
ad7ad57c | 766 | EXPORT_SYMBOL(dma_ops); |