Commit | Line | Data |
---|---|---|
1966287d | 1 | /* head.S: Initial boot code for the Sparc64 port of Linux. |
1da177e4 | 2 | * |
1966287d | 3 | * Copyright (C) 1996, 1997, 2007 David S. Miller (davem@davemloft.net) |
1da177e4 | 4 | * Copyright (C) 1996 David Sitsky (David.Sitsky@anu.edu.au) |
1966287d | 5 | * Copyright (C) 1997, 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) |
1da177e4 LT |
6 | * Copyright (C) 1997 Miguel de Icaza (miguel@nuclecu.unam.mx) |
7 | */ | |
8 | ||
1da177e4 LT |
9 | #include <linux/version.h> |
10 | #include <linux/errno.h> | |
951bc82c | 11 | #include <linux/threads.h> |
1966287d | 12 | #include <linux/init.h> |
687124dd | 13 | #include <linux/linkage.h> |
1da177e4 LT |
14 | #include <asm/thread_info.h> |
15 | #include <asm/asi.h> | |
16 | #include <asm/pstate.h> | |
17 | #include <asm/ptrace.h> | |
18 | #include <asm/spitfire.h> | |
19 | #include <asm/page.h> | |
20 | #include <asm/pgtable.h> | |
21 | #include <asm/errno.h> | |
22 | #include <asm/signal.h> | |
23 | #include <asm/processor.h> | |
24 | #include <asm/lsu.h> | |
25 | #include <asm/dcr.h> | |
26 | #include <asm/dcu.h> | |
27 | #include <asm/head.h> | |
28 | #include <asm/ttable.h> | |
29 | #include <asm/mmu.h> | |
56fb4df6 | 30 | #include <asm/cpudata.h> |
6eda3a75 DM |
31 | #include <asm/pil.h> |
32 | #include <asm/estate.h> | |
33 | #include <asm/sfafsr.h> | |
34 | #include <asm/unistd.h> | |
1da177e4 LT |
35 | |
36 | /* This section from from _start to sparc64_boot_end should fit into | |
c9c10830 | 37 | * 0x0000000000404000 to 0x0000000000408000. |
1da177e4 | 38 | */ |
1da177e4 LT |
39 | .text |
40 | .globl start, _start, stext, _stext | |
41 | _start: | |
42 | start: | |
43 | _stext: | |
44 | stext: | |
1da177e4 LT |
45 | ! 0x0000000000404000 |
46 | b sparc64_boot | |
47 | flushw /* Flush register file. */ | |
48 | ||
49 | /* This stuff has to be in sync with SILO and other potential boot loaders | |
50 | * Fields should be kept upward compatible and whenever any change is made, | |
51 | * HdrS version should be incremented. | |
52 | */ | |
53 | .global root_flags, ram_flags, root_dev | |
54 | .global sparc_ramdisk_image, sparc_ramdisk_size | |
55 | .global sparc_ramdisk_image64 | |
56 | ||
57 | .ascii "HdrS" | |
58 | .word LINUX_VERSION_CODE | |
59 | ||
60 | /* History: | |
61 | * | |
62 | * 0x0300 : Supports being located at other than 0x4000 | |
63 | * 0x0202 : Supports kernel params string | |
64 | * 0x0201 : Supports reboot_command | |
65 | */ | |
66 | .half 0x0301 /* HdrS version */ | |
67 | ||
68 | root_flags: | |
69 | .half 1 | |
70 | root_dev: | |
71 | .half 0 | |
72 | ram_flags: | |
73 | .half 0 | |
74 | sparc_ramdisk_image: | |
75 | .word 0 | |
76 | sparc_ramdisk_size: | |
77 | .word 0 | |
78 | .xword reboot_command | |
79 | .xword bootstr_info | |
80 | sparc_ramdisk_image64: | |
81 | .xword 0 | |
82 | .word _end | |
83 | ||
bff06d55 DM |
84 | /* PROM cif handler code address is in %o4. */ |
85 | sparc64_boot: | |
15f14834 | 86 | mov %o4, %l7 |
bff06d55 | 87 | |
25985edc | 88 | /* We need to remap the kernel. Use position independent |
bff06d55 | 89 | * code to remap us to KERNBASE. |
1da177e4 | 90 | * |
bff06d55 DM |
91 | * SILO can invoke us with 32-bit address masking enabled, |
92 | * so make sure that's clear. | |
1da177e4 | 93 | */ |
bff06d55 DM |
94 | rdpr %pstate, %g1 |
95 | andn %g1, PSTATE_AM, %g1 | |
96 | wrpr %g1, 0x0, %pstate | |
97 | ba,a,pt %xcc, 1f | |
98 | ||
d82ace7d DM |
99 | .globl prom_finddev_name, prom_chosen_path, prom_root_node |
100 | .globl prom_getprop_name, prom_mmu_name, prom_peer_name | |
101 | .globl prom_callmethod_name, prom_translate_name, prom_root_compatible | |
bff06d55 DM |
102 | .globl prom_map_name, prom_unmap_name, prom_mmu_ihandle_cache |
103 | .globl prom_boot_mapped_pc, prom_boot_mapping_mode | |
104 | .globl prom_boot_mapping_phys_high, prom_boot_mapping_phys_low | |
6c70b6fc | 105 | .globl prom_compatible_name, prom_cpu_path, prom_cpu_compatible |
301feb65 | 106 | .globl is_sun4v, sun4v_chip_type, prom_set_trap_table_name |
d82ace7d DM |
107 | prom_peer_name: |
108 | .asciz "peer" | |
109 | prom_compatible_name: | |
110 | .asciz "compatible" | |
bff06d55 DM |
111 | prom_finddev_name: |
112 | .asciz "finddevice" | |
113 | prom_chosen_path: | |
114 | .asciz "/chosen" | |
6c70b6fc DM |
115 | prom_cpu_path: |
116 | .asciz "/cpu" | |
bff06d55 DM |
117 | prom_getprop_name: |
118 | .asciz "getprop" | |
119 | prom_mmu_name: | |
120 | .asciz "mmu" | |
121 | prom_callmethod_name: | |
122 | .asciz "call-method" | |
123 | prom_translate_name: | |
124 | .asciz "translate" | |
125 | prom_map_name: | |
126 | .asciz "map" | |
127 | prom_unmap_name: | |
128 | .asciz "unmap" | |
301feb65 DM |
129 | prom_set_trap_table_name: |
130 | .asciz "SUNW,set-trap-table" | |
d82ace7d | 131 | prom_sun4v_name: |
6cebb520 | 132 | .asciz "sun4v" |
6c70b6fc DM |
133 | prom_niagara_prefix: |
134 | .asciz "SUNW,UltraSPARC-T" | |
4ba991d3 | 135 | prom_sparc_prefix: |
08cefa9f | 136 | .asciz "SPARC-" |
76950e6e AP |
137 | prom_sparc64x_prefix: |
138 | .asciz "SPARC64-X" | |
bff06d55 | 139 | .align 4 |
d82ace7d DM |
140 | prom_root_compatible: |
141 | .skip 64 | |
6c70b6fc DM |
142 | prom_cpu_compatible: |
143 | .skip 64 | |
d82ace7d DM |
144 | prom_root_node: |
145 | .word 0 | |
bff06d55 DM |
146 | prom_mmu_ihandle_cache: |
147 | .word 0 | |
148 | prom_boot_mapped_pc: | |
149 | .word 0 | |
150 | prom_boot_mapping_mode: | |
151 | .word 0 | |
152 | .align 8 | |
153 | prom_boot_mapping_phys_high: | |
154 | .xword 0 | |
155 | prom_boot_mapping_phys_low: | |
156 | .xword 0 | |
d82ace7d DM |
157 | is_sun4v: |
158 | .word 0 | |
6c70b6fc DM |
159 | sun4v_chip_type: |
160 | .word SUN4V_CHIP_INVALID | |
bff06d55 DM |
161 | 1: |
162 | rd %pc, %l0 | |
d82ace7d DM |
163 | |
164 | mov (1b - prom_peer_name), %l1 | |
165 | sub %l0, %l1, %l1 | |
166 | mov 0, %l2 | |
167 | ||
168 | /* prom_root_node = prom_peer(0) */ | |
169 | stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "peer" | |
170 | mov 1, %l3 | |
171 | stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1 | |
172 | stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1 | |
173 | stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, 0 | |
174 | stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1 | |
175 | call %l7 | |
176 | add %sp, (2047 + 128), %o0 ! argument array | |
177 | ||
178 | ldx [%sp + 2047 + 128 + 0x20], %l4 ! prom root node | |
179 | mov (1b - prom_root_node), %l1 | |
180 | sub %l0, %l1, %l1 | |
181 | stw %l4, [%l1] | |
182 | ||
183 | mov (1b - prom_getprop_name), %l1 | |
184 | mov (1b - prom_compatible_name), %l2 | |
185 | mov (1b - prom_root_compatible), %l5 | |
186 | sub %l0, %l1, %l1 | |
187 | sub %l0, %l2, %l2 | |
188 | sub %l0, %l5, %l5 | |
189 | ||
190 | /* prom_getproperty(prom_root_node, "compatible", | |
191 | * &prom_root_compatible, 64) | |
192 | */ | |
193 | stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop" | |
194 | mov 4, %l3 | |
195 | stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4 | |
196 | mov 1, %l3 | |
197 | stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1 | |
198 | stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, prom_root_node | |
199 | stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "compatible" | |
200 | stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_root_compatible | |
201 | mov 64, %l3 | |
202 | stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size | |
203 | stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1 | |
204 | call %l7 | |
205 | add %sp, (2047 + 128), %o0 ! argument array | |
206 | ||
bff06d55 DM |
207 | mov (1b - prom_finddev_name), %l1 |
208 | mov (1b - prom_chosen_path), %l2 | |
209 | mov (1b - prom_boot_mapped_pc), %l3 | |
210 | sub %l0, %l1, %l1 | |
211 | sub %l0, %l2, %l2 | |
212 | sub %l0, %l3, %l3 | |
213 | stw %l0, [%l3] | |
214 | sub %sp, (192 + 128), %sp | |
215 | ||
216 | /* chosen_node = prom_finddevice("/chosen") */ | |
217 | stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice" | |
218 | mov 1, %l3 | |
219 | stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1 | |
220 | stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1 | |
221 | stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/chosen" | |
222 | stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1 | |
223 | call %l7 | |
224 | add %sp, (2047 + 128), %o0 ! argument array | |
225 | ||
226 | ldx [%sp + 2047 + 128 + 0x20], %l4 ! chosen device node | |
227 | ||
228 | mov (1b - prom_getprop_name), %l1 | |
229 | mov (1b - prom_mmu_name), %l2 | |
230 | mov (1b - prom_mmu_ihandle_cache), %l5 | |
231 | sub %l0, %l1, %l1 | |
232 | sub %l0, %l2, %l2 | |
233 | sub %l0, %l5, %l5 | |
234 | ||
235 | /* prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu") */ | |
236 | stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop" | |
237 | mov 4, %l3 | |
238 | stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4 | |
239 | mov 1, %l3 | |
240 | stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1 | |
241 | stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, chosen_node | |
242 | stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "mmu" | |
243 | stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_mmu_ihandle_cache | |
244 | mov 4, %l3 | |
245 | stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, sizeof(arg3) | |
246 | stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1 | |
247 | call %l7 | |
248 | add %sp, (2047 + 128), %o0 ! argument array | |
249 | ||
250 | mov (1b - prom_callmethod_name), %l1 | |
251 | mov (1b - prom_translate_name), %l2 | |
252 | sub %l0, %l1, %l1 | |
253 | sub %l0, %l2, %l2 | |
254 | lduw [%l5], %l5 ! prom_mmu_ihandle_cache | |
255 | ||
256 | stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "call-method" | |
257 | mov 3, %l3 | |
258 | stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 3 | |
259 | mov 5, %l3 | |
260 | stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 5 | |
261 | stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1: "translate" | |
262 | stx %l5, [%sp + 2047 + 128 + 0x20] ! arg2: prom_mmu_ihandle_cache | |
b1b510aa DM |
263 | /* PAGE align */ |
264 | srlx %l0, 13, %l3 | |
265 | sllx %l3, 13, %l3 | |
bff06d55 DM |
266 | stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: vaddr, our PC |
267 | stx %g0, [%sp + 2047 + 128 + 0x30] ! res1 | |
268 | stx %g0, [%sp + 2047 + 128 + 0x38] ! res2 | |
269 | stx %g0, [%sp + 2047 + 128 + 0x40] ! res3 | |
270 | stx %g0, [%sp + 2047 + 128 + 0x48] ! res4 | |
271 | stx %g0, [%sp + 2047 + 128 + 0x50] ! res5 | |
272 | call %l7 | |
273 | add %sp, (2047 + 128), %o0 ! argument array | |
274 | ||
275 | ldx [%sp + 2047 + 128 + 0x40], %l1 ! translation mode | |
276 | mov (1b - prom_boot_mapping_mode), %l4 | |
277 | sub %l0, %l4, %l4 | |
278 | stw %l1, [%l4] | |
279 | mov (1b - prom_boot_mapping_phys_high), %l4 | |
280 | sub %l0, %l4, %l4 | |
281 | ldx [%sp + 2047 + 128 + 0x48], %l2 ! physaddr high | |
282 | stx %l2, [%l4 + 0x0] | |
283 | ldx [%sp + 2047 + 128 + 0x50], %l3 ! physaddr low | |
b1b510aa | 284 | /* 4MB align */ |
0eef331a DM |
285 | srlx %l3, ILOG2_4MB, %l3 |
286 | sllx %l3, ILOG2_4MB, %l3 | |
bff06d55 DM |
287 | stx %l3, [%l4 + 0x8] |
288 | ||
289 | /* Leave service as-is, "call-method" */ | |
290 | mov 7, %l3 | |
291 | stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 7 | |
292 | mov 1, %l3 | |
a8201c61 | 293 | stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1 |
bff06d55 DM |
294 | mov (1b - prom_map_name), %l3 |
295 | sub %l0, %l3, %l3 | |
296 | stx %l3, [%sp + 2047 + 128 + 0x18] ! arg1: "map" | |
297 | /* Leave arg2 as-is, prom_mmu_ihandle_cache */ | |
298 | mov -1, %l3 | |
299 | stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: mode (-1 default) | |
64658743 DM |
300 | /* 4MB align the kernel image size. */ |
301 | set (_end - KERNBASE), %l3 | |
302 | set ((4 * 1024 * 1024) - 1), %l4 | |
303 | add %l3, %l4, %l3 | |
304 | andn %l3, %l4, %l3 | |
305 | stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4: roundup(ksize, 4MB) | |
bff06d55 DM |
306 | sethi %hi(KERNBASE), %l3 |
307 | stx %l3, [%sp + 2047 + 128 + 0x38] ! arg5: vaddr (KERNBASE) | |
308 | stx %g0, [%sp + 2047 + 128 + 0x40] ! arg6: empty | |
309 | mov (1b - prom_boot_mapping_phys_low), %l3 | |
310 | sub %l0, %l3, %l3 | |
311 | ldx [%l3], %l3 | |
312 | stx %l3, [%sp + 2047 + 128 + 0x48] ! arg7: phys addr | |
313 | call %l7 | |
314 | add %sp, (2047 + 128), %o0 ! argument array | |
315 | ||
316 | add %sp, (192 + 128), %sp | |
317 | ||
d82ace7d DM |
318 | sethi %hi(prom_root_compatible), %g1 |
319 | or %g1, %lo(prom_root_compatible), %g1 | |
320 | sethi %hi(prom_sun4v_name), %g7 | |
321 | or %g7, %lo(prom_sun4v_name), %g7 | |
6cebb520 | 322 | mov 5, %g3 |
6c70b6fc | 323 | 90: ldub [%g7], %g2 |
d82ace7d DM |
324 | ldub [%g1], %g4 |
325 | cmp %g2, %g4 | |
6c70b6fc | 326 | bne,pn %icc, 80f |
d82ace7d DM |
327 | add %g7, 1, %g7 |
328 | subcc %g3, 1, %g3 | |
6c70b6fc | 329 | bne,pt %xcc, 90b |
d82ace7d DM |
330 | add %g1, 1, %g1 |
331 | ||
332 | sethi %hi(is_sun4v), %g1 | |
333 | or %g1, %lo(is_sun4v), %g1 | |
334 | mov 1, %g7 | |
335 | stw %g7, [%g1] | |
336 | ||
6c70b6fc DM |
337 | /* cpu_node = prom_finddevice("/cpu") */ |
338 | mov (1b - prom_finddev_name), %l1 | |
339 | mov (1b - prom_cpu_path), %l2 | |
340 | sub %l0, %l1, %l1 | |
341 | sub %l0, %l2, %l2 | |
342 | sub %sp, (192 + 128), %sp | |
343 | ||
344 | stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice" | |
345 | mov 1, %l3 | |
346 | stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1 | |
347 | stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1 | |
348 | stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/cpu" | |
349 | stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1 | |
350 | call %l7 | |
351 | add %sp, (2047 + 128), %o0 ! argument array | |
352 | ||
353 | ldx [%sp + 2047 + 128 + 0x20], %l4 ! cpu device node | |
354 | ||
355 | mov (1b - prom_getprop_name), %l1 | |
356 | mov (1b - prom_compatible_name), %l2 | |
357 | mov (1b - prom_cpu_compatible), %l5 | |
358 | sub %l0, %l1, %l1 | |
359 | sub %l0, %l2, %l2 | |
360 | sub %l0, %l5, %l5 | |
361 | ||
362 | /* prom_getproperty(cpu_node, "compatible", | |
363 | * &prom_cpu_compatible, 64) | |
364 | */ | |
365 | stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop" | |
366 | mov 4, %l3 | |
367 | stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4 | |
368 | mov 1, %l3 | |
369 | stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1 | |
370 | stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, cpu_node | |
371 | stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "compatible" | |
372 | stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_cpu_compatible | |
373 | mov 64, %l3 | |
374 | stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size | |
375 | stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1 | |
376 | call %l7 | |
377 | add %sp, (2047 + 128), %o0 ! argument array | |
378 | ||
379 | add %sp, (192 + 128), %sp | |
380 | ||
381 | sethi %hi(prom_cpu_compatible), %g1 | |
382 | or %g1, %lo(prom_cpu_compatible), %g1 | |
383 | sethi %hi(prom_niagara_prefix), %g7 | |
384 | or %g7, %lo(prom_niagara_prefix), %g7 | |
385 | mov 17, %g3 | |
4ba991d3 DM |
386 | 90: ldub [%g7], %g2 |
387 | ldub [%g1], %g4 | |
388 | cmp %g2, %g4 | |
389 | bne,pn %icc, 89f | |
390 | add %g7, 1, %g7 | |
391 | subcc %g3, 1, %g3 | |
392 | bne,pt %xcc, 90b | |
393 | add %g1, 1, %g1 | |
394 | ba,pt %xcc, 91f | |
395 | nop | |
396 | ||
397 | 89: sethi %hi(prom_cpu_compatible), %g1 | |
398 | or %g1, %lo(prom_cpu_compatible), %g1 | |
399 | sethi %hi(prom_sparc_prefix), %g7 | |
400 | or %g7, %lo(prom_sparc_prefix), %g7 | |
08cefa9f | 401 | mov 6, %g3 |
6c70b6fc DM |
402 | 90: ldub [%g7], %g2 |
403 | ldub [%g1], %g4 | |
404 | cmp %g2, %g4 | |
405 | bne,pn %icc, 4f | |
406 | add %g7, 1, %g7 | |
407 | subcc %g3, 1, %g3 | |
408 | bne,pt %xcc, 90b | |
409 | add %g1, 1, %g1 | |
410 | ||
411 | sethi %hi(prom_cpu_compatible), %g1 | |
4ba991d3 | 412 | or %g1, %lo(prom_cpu_compatible), %g1 |
08cefa9f DM |
413 | ldub [%g1 + 6], %g2 |
414 | cmp %g2, 'T' | |
415 | be,pt %xcc, 70f | |
416 | cmp %g2, 'M' | |
c5b8b5be KA |
417 | be,pt %xcc, 70f |
418 | cmp %g2, 'S' | |
76950e6e | 419 | bne,pn %xcc, 49f |
08cefa9f DM |
420 | nop |
421 | ||
422 | 70: ldub [%g1 + 7], %g2 | |
4ba991d3 DM |
423 | cmp %g2, '3' |
424 | be,pt %xcc, 5f | |
425 | mov SUN4V_CHIP_NIAGARA3, %g4 | |
08cefa9f DM |
426 | cmp %g2, '4' |
427 | be,pt %xcc, 5f | |
428 | mov SUN4V_CHIP_NIAGARA4, %g4 | |
429 | cmp %g2, '5' | |
430 | be,pt %xcc, 5f | |
431 | mov SUN4V_CHIP_NIAGARA5, %g4 | |
cadbb580 AP |
432 | cmp %g2, '6' |
433 | be,pt %xcc, 5f | |
434 | mov SUN4V_CHIP_SPARC_M6, %g4 | |
435 | cmp %g2, '7' | |
436 | be,pt %xcc, 5f | |
437 | mov SUN4V_CHIP_SPARC_M7, %g4 | |
c5b8b5be KA |
438 | cmp %g2, 'N' |
439 | be,pt %xcc, 5f | |
440 | mov SUN4V_CHIP_SPARC_SN, %g4 | |
76950e6e | 441 | ba,pt %xcc, 49f |
4ba991d3 DM |
442 | nop |
443 | ||
444 | 91: sethi %hi(prom_cpu_compatible), %g1 | |
6c70b6fc DM |
445 | or %g1, %lo(prom_cpu_compatible), %g1 |
446 | ldub [%g1 + 17], %g2 | |
447 | cmp %g2, '1' | |
448 | be,pt %xcc, 5f | |
449 | mov SUN4V_CHIP_NIAGARA1, %g4 | |
450 | cmp %g2, '2' | |
451 | be,pt %xcc, 5f | |
452 | mov SUN4V_CHIP_NIAGARA2, %g4 | |
4ba991d3 | 453 | |
6c70b6fc | 454 | 4: |
76950e6e AP |
455 | /* Athena */ |
456 | sethi %hi(prom_cpu_compatible), %g1 | |
457 | or %g1, %lo(prom_cpu_compatible), %g1 | |
458 | sethi %hi(prom_sparc64x_prefix), %g7 | |
459 | or %g7, %lo(prom_sparc64x_prefix), %g7 | |
460 | mov 9, %g3 | |
461 | 41: ldub [%g7], %g2 | |
462 | ldub [%g1], %g4 | |
463 | cmp %g2, %g4 | |
464 | bne,pn %icc, 49f | |
465 | add %g7, 1, %g7 | |
466 | subcc %g3, 1, %g3 | |
467 | bne,pt %xcc, 41b | |
468 | add %g1, 1, %g1 | |
76950e6e | 469 | ba,pt %xcc, 5f |
49fa5230 | 470 | mov SUN4V_CHIP_SPARC64X, %g4 |
76950e6e AP |
471 | |
472 | 49: | |
6c70b6fc DM |
473 | mov SUN4V_CHIP_UNKNOWN, %g4 |
474 | 5: sethi %hi(sun4v_chip_type), %g2 | |
475 | or %g2, %lo(sun4v_chip_type), %g2 | |
476 | stw %g4, [%g2] | |
477 | ||
478 | 80: | |
d82ace7d | 479 | BRANCH_IF_SUN4V(g1, jump_to_sun4u_init) |
1da177e4 LT |
480 | BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot) |
481 | BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot) | |
482 | ba,pt %xcc, spitfire_boot | |
483 | nop | |
484 | ||
485 | cheetah_plus_boot: | |
486 | /* Preserve OBP chosen DCU and DCR register settings. */ | |
487 | ba,pt %xcc, cheetah_generic_boot | |
488 | nop | |
489 | ||
490 | cheetah_boot: | |
491 | mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1 | |
492 | wr %g1, %asr18 | |
493 | ||
494 | sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7 | |
495 | or %g7, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7 | |
496 | sllx %g7, 32, %g7 | |
497 | or %g7, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g7 | |
498 | stxa %g7, [%g0] ASI_DCU_CONTROL_REG | |
499 | membar #Sync | |
500 | ||
501 | cheetah_generic_boot: | |
502 | mov TSB_EXTENSION_P, %g3 | |
503 | stxa %g0, [%g3] ASI_DMMU | |
504 | stxa %g0, [%g3] ASI_IMMU | |
505 | membar #Sync | |
506 | ||
507 | mov TSB_EXTENSION_S, %g3 | |
508 | stxa %g0, [%g3] ASI_DMMU | |
509 | membar #Sync | |
510 | ||
511 | mov TSB_EXTENSION_N, %g3 | |
512 | stxa %g0, [%g3] ASI_DMMU | |
513 | stxa %g0, [%g3] ASI_IMMU | |
514 | membar #Sync | |
515 | ||
bff06d55 | 516 | ba,a,pt %xcc, jump_to_sun4u_init |
1da177e4 LT |
517 | |
518 | spitfire_boot: | |
519 | /* Typically PROM has already enabled both MMU's and both on-chip | |
520 | * caches, but we do it here anyway just to be paranoid. | |
521 | */ | |
522 | mov (LSU_CONTROL_IC|LSU_CONTROL_DC|LSU_CONTROL_IM|LSU_CONTROL_DM), %g1 | |
523 | stxa %g1, [%g0] ASI_LSU_CONTROL | |
524 | membar #Sync | |
525 | ||
bff06d55 | 526 | jump_to_sun4u_init: |
1da177e4 LT |
527 | /* |
528 | * Make sure we are in privileged mode, have address masking, | |
529 | * using the ordinary globals and have enabled floating | |
530 | * point. | |
531 | * | |
532 | * Again, typically PROM has left %pil at 13 or similar, and | |
533 | * (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE) in %pstate. | |
534 | */ | |
535 | wrpr %g0, (PSTATE_PRIV|PSTATE_PEF|PSTATE_IE), %pstate | |
536 | wr %g0, 0, %fprs | |
537 | ||
1da177e4 LT |
538 | set sun4u_init, %g2 |
539 | jmpl %g2 + %g0, %g0 | |
540 | nop | |
541 | ||
a0871e8c | 542 | __REF |
1da177e4 | 543 | sun4u_init: |
6cebb520 DM |
544 | BRANCH_IF_SUN4V(g1, sun4v_init) |
545 | ||
1da177e4 | 546 | /* Set ctx 0 */ |
8b11bd12 | 547 | mov PRIMARY_CONTEXT, %g7 |
6cebb520 | 548 | stxa %g0, [%g7] ASI_DMMU |
8b11bd12 DM |
549 | membar #Sync |
550 | ||
551 | mov SECONDARY_CONTEXT, %g7 | |
6cebb520 DM |
552 | stxa %g0, [%g7] ASI_DMMU |
553 | membar #Sync | |
554 | ||
49fa5230 | 555 | ba,a,pt %xcc, sun4u_continue |
8b11bd12 | 556 | |
6cebb520 DM |
557 | sun4v_init: |
558 | /* Set ctx 0 */ | |
559 | mov PRIMARY_CONTEXT, %g7 | |
8b11bd12 | 560 | stxa %g0, [%g7] ASI_MMU |
6cebb520 | 561 | membar #Sync |
1da177e4 | 562 | |
6cebb520 DM |
563 | mov SECONDARY_CONTEXT, %g7 |
564 | stxa %g0, [%g7] ASI_MMU | |
565 | membar #Sync | |
49fa5230 | 566 | ba,a,pt %xcc, niagara_tlb_fixup |
1da177e4 | 567 | |
6cebb520 | 568 | sun4u_continue: |
d82ace7d | 569 | BRANCH_IF_ANY_CHEETAH(g1, g7, cheetah_tlb_fixup) |
1da177e4 | 570 | |
49fa5230 | 571 | ba,a,pt %xcc, spitfire_tlb_fixup |
1da177e4 | 572 | |
8591e302 DM |
573 | niagara_tlb_fixup: |
574 | mov 3, %g2 /* Set TLB type to hypervisor. */ | |
575 | sethi %hi(tlb_type), %g1 | |
576 | stw %g2, [%g1 + %lo(tlb_type)] | |
577 | ||
578 | /* Patch copy/clear ops. */ | |
6c70b6fc DM |
579 | sethi %hi(sun4v_chip_type), %g1 |
580 | lduw [%g1 + %lo(sun4v_chip_type)], %g1 | |
581 | cmp %g1, SUN4V_CHIP_NIAGARA1 | |
582 | be,pt %xcc, niagara_patch | |
583 | cmp %g1, SUN4V_CHIP_NIAGARA2 | |
cf5adce1 | 584 | be,pt %xcc, niagara2_patch |
6c70b6fc | 585 | nop |
4ba991d3 | 586 | cmp %g1, SUN4V_CHIP_NIAGARA3 |
08cefa9f DM |
587 | be,pt %xcc, niagara2_patch |
588 | nop | |
589 | cmp %g1, SUN4V_CHIP_NIAGARA4 | |
ae2c6ca6 | 590 | be,pt %xcc, niagara4_patch |
08cefa9f DM |
591 | nop |
592 | cmp %g1, SUN4V_CHIP_NIAGARA5 | |
cadbb580 AP |
593 | be,pt %xcc, niagara4_patch |
594 | nop | |
595 | cmp %g1, SUN4V_CHIP_SPARC_M6 | |
596 | be,pt %xcc, niagara4_patch | |
597 | nop | |
598 | cmp %g1, SUN4V_CHIP_SPARC_M7 | |
c5b8b5be KA |
599 | be,pt %xcc, niagara4_patch |
600 | nop | |
601 | cmp %g1, SUN4V_CHIP_SPARC_SN | |
ae2c6ca6 | 602 | be,pt %xcc, niagara4_patch |
4ba991d3 | 603 | nop |
6c70b6fc DM |
604 | |
605 | call generic_patch_copyops | |
606 | nop | |
607 | call generic_patch_bzero | |
608 | nop | |
609 | call generic_patch_pageops | |
610 | nop | |
611 | ||
612 | ba,a,pt %xcc, 80f | |
ae2c6ca6 DM |
613 | niagara4_patch: |
614 | call niagara4_patch_copyops | |
615 | nop | |
9f825962 | 616 | call niagara4_patch_bzero |
ae2c6ca6 DM |
617 | nop |
618 | call niagara4_patch_pageops | |
619 | nop | |
620 | ||
621 | ba,a,pt %xcc, 80f | |
622 | ||
cf5adce1 DM |
623 | niagara2_patch: |
624 | call niagara2_patch_copyops | |
625 | nop | |
626 | call niagara_patch_bzero | |
627 | nop | |
e95ade08 | 628 | call niagara_patch_pageops |
cf5adce1 DM |
629 | nop |
630 | ||
631 | ba,a,pt %xcc, 80f | |
6c70b6fc DM |
632 | |
633 | niagara_patch: | |
8591e302 DM |
634 | call niagara_patch_copyops |
635 | nop | |
8ca2557c DM |
636 | call niagara_patch_bzero |
637 | nop | |
8591e302 DM |
638 | call niagara_patch_pageops |
639 | nop | |
640 | ||
6c70b6fc | 641 | 80: |
8591e302 DM |
642 | /* Patch TLB/cache ops. */ |
643 | call hypervisor_patch_cachetlbops | |
644 | nop | |
645 | ||
49fa5230 | 646 | ba,a,pt %xcc, tlb_fixup_done |
d82ace7d | 647 | |
1da177e4 | 648 | cheetah_tlb_fixup: |
1da177e4 LT |
649 | mov 2, %g2 /* Set TLB type to cheetah+. */ |
650 | BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f) | |
651 | ||
652 | mov 1, %g2 /* Set TLB type to cheetah. */ | |
653 | ||
654 | 1: sethi %hi(tlb_type), %g1 | |
655 | stw %g2, [%g1 + %lo(tlb_type)] | |
656 | ||
0835ae0f | 657 | /* Patch copy/page operations to cheetah optimized versions. */ |
1da177e4 LT |
658 | call cheetah_patch_copyops |
659 | nop | |
dbd2fdf5 DM |
660 | call cheetah_patch_copy_page |
661 | nop | |
1da177e4 LT |
662 | call cheetah_patch_cachetlbops |
663 | nop | |
664 | ||
49fa5230 | 665 | ba,a,pt %xcc, tlb_fixup_done |
1da177e4 LT |
666 | |
667 | spitfire_tlb_fixup: | |
1da177e4 LT |
668 | /* Set TLB type to spitfire. */ |
669 | mov 0, %g2 | |
670 | sethi %hi(tlb_type), %g1 | |
671 | stw %g2, [%g1 + %lo(tlb_type)] | |
672 | ||
673 | tlb_fixup_done: | |
674 | sethi %hi(init_thread_union), %g6 | |
675 | or %g6, %lo(init_thread_union), %g6 | |
676 | ldx [%g6 + TI_TASK], %g4 | |
1da177e4 | 677 | |
1da177e4 LT |
678 | wr %g0, ASI_P, %asi |
679 | mov 1, %g1 | |
680 | sllx %g1, THREAD_SHIFT, %g1 | |
681 | sub %g1, (STACKFRAME_SZ + STACK_BIAS), %g1 | |
682 | add %g6, %g1, %sp | |
1da177e4 LT |
683 | |
684 | /* Set per-cpu pointer initially to zero, this makes | |
685 | * the boot-cpu use the in-kernel-image per-cpu areas | |
686 | * before setup_per_cpu_area() is invoked. | |
687 | */ | |
688 | clr %g5 | |
689 | ||
690 | wrpr %g0, 0, %wstate | |
691 | wrpr %g0, 0x0, %tl | |
692 | ||
693 | /* Clear the bss */ | |
694 | sethi %hi(__bss_start), %o0 | |
695 | or %o0, %lo(__bss_start), %o0 | |
696 | sethi %hi(_end), %o1 | |
697 | or %o1, %lo(_end), %o1 | |
698 | call __bzero | |
699 | sub %o1, %o0, %o1 | |
700 | ||
1da177e4 LT |
701 | call prom_init |
702 | mov %l7, %o0 ! OpenPROM cif handler | |
703 | ||
ef3e035c DM |
704 | /* To create a one-register-window buffer between the kernel's |
705 | * initial stack and the last stack frame we use from the firmware, | |
706 | * do the rest of the boot from a C helper function. | |
951bc82c | 707 | */ |
ef3e035c | 708 | call start_early_boot |
1da177e4 LT |
709 | nop |
710 | /* Not reached... */ | |
711 | ||
1966287d DM |
712 | .previous |
713 | ||
5d8e1b18 DM |
714 | /* This is meant to allow the sharing of this code between |
715 | * boot processor invocation (via setup_tba() below) and | |
716 | * secondary processor startup (via trampoline.S). The | |
717 | * former does use this code, the latter does not yet due | |
718 | * to some complexities. That should be fixed up at some | |
719 | * point. | |
c9c10830 DM |
720 | * |
721 | * There used to be enormous complexity wrt. transferring | |
877d0310 | 722 | * over from the firmware's trap table to the Linux kernel's. |
c9c10830 DM |
723 | * For example, there was a chicken & egg problem wrt. building |
724 | * the OBP page tables, yet needing to be on the Linux kernel | |
725 | * trap table (to translate PAGE_OFFSET addresses) in order to | |
726 | * do that. | |
727 | * | |
728 | * We now handle OBP tlb misses differently, via linear lookups | |
729 | * into the prom_trans[] array. So that specific problem no | |
730 | * longer exists. Yet, unfortunately there are still some issues | |
731 | * preventing trampoline.S from using this code... ho hum. | |
5d8e1b18 DM |
732 | */ |
733 | .globl setup_trap_table | |
734 | setup_trap_table: | |
735 | save %sp, -192, %sp | |
736 | ||
c9c10830 | 737 | /* Force interrupts to be disabled. */ |
d8573e20 DM |
738 | rdpr %pstate, %l0 |
739 | andn %l0, PSTATE_IE, %o1 | |
5d8e1b18 | 740 | wrpr %o1, 0x0, %pstate |
d8573e20 | 741 | rdpr %pil, %l1 |
b4f4372f | 742 | wrpr %g0, PIL_NORMAL_MAX, %pil |
1da177e4 | 743 | |
c9c10830 | 744 | /* Make the firmware call to jump over to the Linux trap table. */ |
12eaa328 DM |
745 | sethi %hi(is_sun4v), %o0 |
746 | lduw [%o0 + %lo(is_sun4v)], %o0 | |
747 | brz,pt %o0, 1f | |
748 | nop | |
749 | ||
750 | TRAP_LOAD_TRAP_BLOCK(%g2, %g3) | |
751 | add %g2, TRAP_PER_CPU_FAULT_INFO, %g2 | |
752 | stxa %g2, [%g0] ASI_SCRATCHPAD | |
753 | ||
754 | /* Compute physical address: | |
755 | * | |
756 | * paddr = kern_base + (mmfsa_vaddr - KERNBASE) | |
757 | */ | |
758 | sethi %hi(KERNBASE), %g3 | |
759 | sub %g2, %g3, %g2 | |
760 | sethi %hi(kern_base), %g3 | |
761 | ldx [%g3 + %lo(kern_base)], %g3 | |
762 | add %g2, %g3, %o1 | |
301feb65 | 763 | sethi %hi(sparc64_ttable_tl0), %o0 |
12eaa328 | 764 | |
301feb65 DM |
765 | set prom_set_trap_table_name, %g2 |
766 | stx %g2, [%sp + 2047 + 128 + 0x00] | |
767 | mov 2, %g2 | |
768 | stx %g2, [%sp + 2047 + 128 + 0x08] | |
769 | mov 0, %g2 | |
770 | stx %g2, [%sp + 2047 + 128 + 0x10] | |
771 | stx %o0, [%sp + 2047 + 128 + 0x18] | |
772 | stx %o1, [%sp + 2047 + 128 + 0x20] | |
773 | sethi %hi(p1275buf), %g2 | |
774 | or %g2, %lo(p1275buf), %g2 | |
775 | ldx [%g2 + 0x08], %o1 | |
776 | call %o1 | |
777 | add %sp, (2047 + 128), %o0 | |
12eaa328 | 778 | |
49fa5230 | 779 | ba,a,pt %xcc, 2f |
12eaa328 | 780 | |
301feb65 DM |
781 | 1: sethi %hi(sparc64_ttable_tl0), %o0 |
782 | set prom_set_trap_table_name, %g2 | |
783 | stx %g2, [%sp + 2047 + 128 + 0x00] | |
784 | mov 1, %g2 | |
785 | stx %g2, [%sp + 2047 + 128 + 0x08] | |
786 | mov 0, %g2 | |
787 | stx %g2, [%sp + 2047 + 128 + 0x10] | |
788 | stx %o0, [%sp + 2047 + 128 + 0x18] | |
789 | sethi %hi(p1275buf), %g2 | |
790 | or %g2, %lo(p1275buf), %g2 | |
791 | ldx [%g2 + 0x08], %o1 | |
792 | call %o1 | |
793 | add %sp, (2047 + 128), %o0 | |
5d8e1b18 DM |
794 | |
795 | /* Start using proper page size encodings in ctx register. */ | |
12eaa328 | 796 | 2: sethi %hi(sparc64_kern_pri_context), %g3 |
5d8e1b18 | 797 | ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2 |
8b11bd12 DM |
798 | |
799 | mov PRIMARY_CONTEXT, %g1 | |
800 | ||
801 | 661: stxa %g2, [%g1] ASI_DMMU | |
802 | .section .sun4v_1insn_patch, "ax" | |
803 | .word 661b | |
804 | stxa %g2, [%g1] ASI_MMU | |
805 | .previous | |
806 | ||
5d8e1b18 DM |
807 | membar #Sync |
808 | ||
53140b71 DM |
809 | BRANCH_IF_SUN4V(o2, 1f) |
810 | ||
1da177e4 LT |
811 | /* Kill PROM timer */ |
812 | sethi %hi(0x80000000), %o2 | |
813 | sllx %o2, 32, %o2 | |
814 | wr %o2, 0, %tick_cmpr | |
815 | ||
d82ace7d | 816 | BRANCH_IF_ANY_CHEETAH(o2, o3, 1f) |
1da177e4 | 817 | |
49fa5230 | 818 | ba,a,pt %xcc, 2f |
1da177e4 LT |
819 | |
820 | /* Disable STICK_INT interrupts. */ | |
821 | 1: | |
822 | sethi %hi(0x80000000), %o2 | |
823 | sllx %o2, 32, %o2 | |
824 | wr %o2, %asr25 | |
825 | ||
1da177e4 LT |
826 | 2: |
827 | wrpr %g0, %g0, %wstate | |
1da177e4 LT |
828 | |
829 | call init_irqwork_curcpu | |
830 | nop | |
831 | ||
d8573e20 DM |
832 | /* Now we can restore interrupt state. */ |
833 | wrpr %l0, 0, %pstate | |
834 | wrpr %l1, 0x0, %pil | |
5d8e1b18 DM |
835 | |
836 | ret | |
837 | restore | |
838 | ||
839 | .globl setup_tba | |
a8b900d8 | 840 | setup_tba: |
5d8e1b18 DM |
841 | save %sp, -192, %sp |
842 | ||
843 | /* The boot processor is the only cpu which invokes this | |
844 | * routine, the other cpus set things up via trampoline.S. | |
845 | * So save the OBP trap table address here. | |
846 | */ | |
847 | rdpr %tba, %g7 | |
848 | sethi %hi(prom_tba), %o1 | |
849 | or %o1, %lo(prom_tba), %o1 | |
850 | stx %g7, [%o1] | |
851 | ||
852 | call setup_trap_table | |
853 | nop | |
1da177e4 LT |
854 | |
855 | ret | |
856 | restore | |
c9c10830 DM |
857 | sparc64_boot_end: |
858 | ||
a88b5ba8 SR |
859 | #include "etrap_64.S" |
860 | #include "rtrap_64.S" | |
c9c10830 | 861 | #include "winfixup.S" |
6eda3a75 DM |
862 | #include "fpu_traps.S" |
863 | #include "ivec.S" | |
864 | #include "getsetcc.S" | |
865 | #include "utrap.S" | |
866 | #include "spiterrs.S" | |
867 | #include "cherrs.S" | |
868 | #include "misctrap.S" | |
869 | #include "syscalls.S" | |
870 | #include "helpers.S" | |
871 | #include "hvcalls.S" | |
5b0c0572 DM |
872 | #include "sun4v_tlb_miss.S" |
873 | #include "sun4v_ivec.S" | |
2d9e2763 DM |
874 | #include "ktlb.S" |
875 | #include "tsb.S" | |
1da177e4 LT |
876 | |
877 | /* | |
c9c10830 | 878 | * The following skip makes sure the trap table in ttable.S is aligned |
1da177e4 | 879 | * on a 32K boundary as required by the v9 specs for TBA register. |
2f7ee7c6 DM |
880 | * |
881 | * We align to a 32K boundary, then we have the 32K kernel TSB, | |
2d9e2763 | 882 | * the 64K kernel 4MB TSB, and then the 32K aligned trap table. |
1da177e4 | 883 | */ |
c9c10830 DM |
884 | 1: |
885 | .skip 0x4000 + _start - 1b | |
1da177e4 | 886 | |
2d9e2763 DM |
887 | ! 0x0000000000408000 |
888 | ||
2f7ee7c6 DM |
889 | .globl swapper_tsb |
890 | swapper_tsb: | |
891 | .skip (32 * 1024) | |
1da177e4 | 892 | |
2d9e2763 DM |
893 | .globl swapper_4m_tsb |
894 | swapper_4m_tsb: | |
895 | .skip (64 * 1024) | |
896 | ||
897 | ! 0x0000000000420000 | |
1da177e4 | 898 | |
2d9e2763 DM |
899 | /* Some care needs to be exercised if you try to move the |
900 | * location of the trap table relative to other things. For | |
901 | * one thing there are br* instructions in some of the | |
902 | * trap table entires which branch back to code in ktlb.S | |
903 | * Those instructions can only handle a signed 16-bit | |
904 | * displacement. | |
905 | * | |
906 | * There is a binutils bug (bugzilla #4558) which causes | |
907 | * the relocation overflow checks for such instructions to | |
908 | * not be done correctly. So bintuils will not notice the | |
909 | * error and will instead write junk into the relocation and | |
910 | * you'll have an unbootable kernel. | |
911 | */ | |
b979542d | 912 | #include "ttable_64.S" |
1da177e4 | 913 | |
2d9e2763 DM |
914 | ! 0x0000000000428000 |
915 | ||
a88b5ba8 | 916 | #include "systbls_64.S" |
074d82cf | 917 | |
1da177e4 LT |
918 | .data |
919 | .align 8 | |
920 | .globl prom_tba, tlb_type | |
921 | prom_tba: .xword 0 | |
922 | tlb_type: .word 0 /* Must NOT end up in BSS */ | |
923 | .section ".fixup",#alloc,#execinstr | |
5fd29752 | 924 | |
40bdac7d DM |
925 | .globl __ret_efault, __retl_efault, __ret_one, __retl_one |
926 | ENTRY(__ret_efault) | |
1da177e4 LT |
927 | ret |
928 | restore %g0, -EFAULT, %o0 | |
40bdac7d DM |
929 | ENDPROC(__ret_efault) |
930 | ||
931 | ENTRY(__retl_efault) | |
5fd29752 DM |
932 | retl |
933 | mov -EFAULT, %o0 | |
40bdac7d DM |
934 | ENDPROC(__retl_efault) |
935 | ||
936 | ENTRY(__retl_one) | |
937 | retl | |
938 | mov 1, %o0 | |
939 | ENDPROC(__retl_one) | |
940 | ||
a7c5724b RG |
941 | ENTRY(__retl_one_fp) |
942 | VISExitHalf | |
943 | retl | |
944 | mov 1, %o0 | |
945 | ENDPROC(__retl_one_fp) | |
946 | ||
40bdac7d DM |
947 | ENTRY(__ret_one_asi) |
948 | wr %g0, ASI_AIUS, %asi | |
949 | ret | |
950 | restore %g0, 1, %o0 | |
951 | ENDPROC(__ret_one_asi) | |
952 | ||
953 | ENTRY(__retl_one_asi) | |
954 | wr %g0, ASI_AIUS, %asi | |
955 | retl | |
956 | mov 1, %o0 | |
957 | ENDPROC(__retl_one_asi) | |
958 | ||
a7c5724b RG |
959 | ENTRY(__retl_one_asi_fp) |
960 | wr %g0, ASI_AIUS, %asi | |
961 | VISExitHalf | |
962 | retl | |
963 | mov 1, %o0 | |
964 | ENDPROC(__retl_one_asi_fp) | |
965 | ||
40bdac7d DM |
966 | ENTRY(__retl_o1) |
967 | retl | |
968 | mov %o1, %o0 | |
969 | ENDPROC(__retl_o1) |