[linux-2.6-block.git] / arch / sparc / include / asm / trap_block.h

#ifndef _SPARC_TRAP_BLOCK_H
#define _SPARC_TRAP_BLOCK_H

#include <asm/hypervisor.h>
#include <asm/asi.h>

#ifndef __ASSEMBLY__

/* Trap handling code needs to get at a few critical values upon
 * trap entry and to process TSB misses.  These cannot be in the
 * per_cpu() area as we really need to lock them into the TLB and
 * thus make them part of the main kernel image.  As a result we
 * try to make this as small as possible.
 *
 * This is padded out and aligned to 64-bytes to avoid false sharing
 * on SMP.
 */

/* If you modify the size of this structure, please update
 * TRAP_BLOCK_SZ_SHIFT below.
 */
struct thread_info;
struct trap_per_cpu {
/* D-cache line 1: Basic thread information, cpu and device mondo queues */
	struct thread_info	*thread;
	unsigned long		pgd_paddr;
	unsigned long		cpu_mondo_pa;
	unsigned long		dev_mondo_pa;

/* D-cache line 2: Error Mondo Queue and kernel buffer pointers */
	unsigned long		resum_mondo_pa;
	unsigned long		resum_kernel_buf_pa;
	unsigned long		nonresum_mondo_pa;
	unsigned long		nonresum_kernel_buf_pa;

/* Dcache lines 3, 4, 5, and 6: Hypervisor Fault Status */
	struct hv_fault_status	fault_info;

/* Dcache line 7: Physical addresses of CPU send mondo block and CPU list.  */
	unsigned long		cpu_mondo_block_pa;
	unsigned long		cpu_list_pa;
	unsigned long		tsb_huge;
	unsigned long		tsb_huge_temp;

/* Dcache line 8: IRQ work list, and keep trap_block a power-of-2 in size.  */
	unsigned long		irq_worklist_pa;
	unsigned int		cpu_mondo_qmask;
	unsigned int		dev_mondo_qmask;
	unsigned int		resum_qmask;
	unsigned int		nonresum_qmask;
	unsigned long		__per_cpu_base;
} __attribute__((aligned(64)));
extern struct trap_per_cpu trap_block[NR_CPUS];
void init_cur_cpu_trap(struct thread_info *);
void setup_tba(void);
extern int ncpus_probed;

unsigned long real_hard_smp_processor_id(void);

struct cpuid_patch_entry {
	unsigned int	addr;
	unsigned int	cheetah_safari[4];
	unsigned int	cheetah_jbus[4];
	unsigned int	starfire[4];
	unsigned int	sun4v[4];
};
extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end;

struct sun4v_1insn_patch_entry {
	unsigned int	addr;
	unsigned int	insn;
};
extern struct sun4v_1insn_patch_entry __sun4v_1insn_patch,
	__sun4v_1insn_patch_end;

struct sun4v_2insn_patch_entry {
	unsigned int	addr;
	unsigned int	insns[2];
};
extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
	__sun4v_2insn_patch_end;
extern struct sun4v_2insn_patch_entry __sun_m7_2insn_patch,
	__sun_m7_2insn_patch_end;


#endif /* !(__ASSEMBLY__) */

#define TRAP_PER_CPU_THREAD		0x00
#define TRAP_PER_CPU_PGD_PADDR		0x08
#define TRAP_PER_CPU_CPU_MONDO_PA	0x10
#define TRAP_PER_CPU_DEV_MONDO_PA	0x18
#define TRAP_PER_CPU_RESUM_MONDO_PA	0x20
#define TRAP_PER_CPU_RESUM_KBUF_PA	0x28
#define TRAP_PER_CPU_NONRESUM_MONDO_PA	0x30
#define TRAP_PER_CPU_NONRESUM_KBUF_PA	0x38
#define TRAP_PER_CPU_FAULT_INFO		0x40
#define TRAP_PER_CPU_CPU_MONDO_BLOCK_PA	0xc0
#define TRAP_PER_CPU_CPU_LIST_PA	0xc8
#define TRAP_PER_CPU_TSB_HUGE		0xd0
#define TRAP_PER_CPU_TSB_HUGE_TEMP	0xd8
#define TRAP_PER_CPU_IRQ_WORKLIST_PA	0xe0
#define TRAP_PER_CPU_CPU_MONDO_QMASK	0xe8
#define TRAP_PER_CPU_DEV_MONDO_QMASK	0xec
#define TRAP_PER_CPU_RESUM_QMASK	0xf0
#define TRAP_PER_CPU_NONRESUM_QMASK	0xf4
#define TRAP_PER_CPU_PER_CPU_BASE	0xf8

#define TRAP_BLOCK_SZ_SHIFT		8

#include <asm/scratchpad.h>

#define __GET_CPUID(REG)				\
	/* Spitfire implementation (default). */	\
661:	ldxa		[%g0] ASI_UPA_CONFIG, REG;	\
	srlx		REG, 17, REG;			\
	 and		REG, 0x1f, REG;			\
	nop;						\
	.section	.cpuid_patch, "ax";		\
	/* Instruction location. */			\
	.word		661b;				\
	/* Cheetah Safari implementation. */		\
	ldxa		[%g0] ASI_SAFARI_CONFIG, REG;	\
	srlx		REG, 17, REG;			\
	and		REG, 0x3ff, REG;		\
	nop;						\
	/* Cheetah JBUS implementation. */		\
	ldxa		[%g0] ASI_JBUS_CONFIG, REG;	\
	srlx		REG, 17, REG;			\
	and		REG, 0x1f, REG;			\
	nop;						\
	/* Starfire implementation. */			\
	sethi		%hi(0x1fff40000d0 >> 9), REG;	\
	sllx		REG, 9, REG;			\
	or		REG, 0xd0, REG;			\
	lduwa		[REG] ASI_PHYS_BYPASS_EC_E, REG;\
	/* sun4v implementation. */			\
	mov		SCRATCHPAD_CPUID, REG;		\
	ldxa		[REG] ASI_SCRATCHPAD, REG;	\
	nop;						\
	nop;						\
	.previous;

#ifdef CONFIG_SMP

#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
	__GET_CPUID(TMP)			\
	sethi	%hi(trap_block), DEST;		\
	sllx	TMP, TRAP_BLOCK_SZ_SHIFT, TMP;	\
	or	DEST, %lo(trap_block), DEST;	\
	add	DEST, TMP, DEST;		\

/* Clobbers TMP, current address space PGD phys address into DEST.  */
#define TRAP_LOAD_PGD_PHYS(DEST, TMP)		\
	TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
	ldx	[DEST + TRAP_PER_CPU_PGD_PADDR], DEST;

/* Clobbers TMP, loads local processor's IRQ work area into DEST.  */
#define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP)	\
	TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
	add	DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST;

/* Clobbers TMP, loads DEST with current thread info pointer.  */
#define TRAP_LOAD_THREAD_REG(DEST, TMP)		\
	TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
	ldx	[DEST + TRAP_PER_CPU_THREAD], DEST;

/* Given the current thread info pointer in THR, load the per-cpu
 * area base of the current processor into DEST.  REG1, REG2, and REG3 are
 * clobbered.
 *
 * You absolutely cannot use DEST as a temporary in this code.  The
 * reason is that traps can happen during execution, and return from
 * trap will load the fully resolved DEST per-cpu base.  This can corrupt
 * the calculations done by the macro mid-stream.
 */
#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)	\
	lduh	[THR + TI_CPU], REG1;			\
	sethi	%hi(trap_block), REG2;			\
	sllx	REG1, TRAP_BLOCK_SZ_SHIFT, REG1;	\
	or	REG2, %lo(trap_block), REG2;		\
	add	REG2, REG1, REG2;			\
	ldx	[REG2 + TRAP_PER_CPU_PER_CPU_BASE], DEST;

#else

#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
	sethi	%hi(trap_block), DEST;		\
	or	DEST, %lo(trap_block), DEST;	\

/* Uniprocessor versions, we know the cpuid is zero.  */
#define TRAP_LOAD_PGD_PHYS(DEST, TMP)		\
	TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
	ldx	[DEST + TRAP_PER_CPU_PGD_PADDR], DEST;

/* Clobbers TMP, loads local processor's IRQ work area into DEST.  */
#define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP)	\
	TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
	add	DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST;

#define TRAP_LOAD_THREAD_REG(DEST, TMP)		\
	TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
	ldx	[DEST + TRAP_PER_CPU_THREAD], DEST;

/* No per-cpu areas on uniprocessor, so no need to load DEST.  */
#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)

#endif /* !(CONFIG_SMP) */

#endif /* _SPARC_TRAP_BLOCK_H */
Commit	Line	Data
19f0fa3f DM	1	#ifndef _SPARC_TRAP_BLOCK_H
	2	#define _SPARC_TRAP_BLOCK_H
	3
	4	#include <asm/hypervisor.h>
	5	#include <asm/asi.h>
	6
	7	#ifndef __ASSEMBLY__
	8
	9	/* Trap handling code needs to get at a few critical values upon
	10	* trap entry and to process TSB misses. These cannot be in the
	11	* per_cpu() area as we really need to lock them into the TLB and
	12	* thus make them part of the main kernel image. As a result we
	13	* try to make this as small as possible.
	14	*
	15	* This is padded out and aligned to 64-bytes to avoid false sharing
	16	* on SMP.
	17	*/
	18
	19	/* If you modify the size of this structure, please update
	20	* TRAP_BLOCK_SZ_SHIFT below.
	21	*/
	22	struct thread_info;
	23	struct trap_per_cpu {
	24	/* D-cache line 1: Basic thread information, cpu and device mondo queues */
	25	struct thread_info *thread;
	26	unsigned long pgd_paddr;
	27	unsigned long cpu_mondo_pa;
	28	unsigned long dev_mondo_pa;
	29
	30	/* D-cache line 2: Error Mondo Queue and kernel buffer pointers */
	31	unsigned long resum_mondo_pa;
	32	unsigned long resum_kernel_buf_pa;
	33	unsigned long nonresum_mondo_pa;
	34	unsigned long nonresum_kernel_buf_pa;
	35
	36	/* Dcache lines 3, 4, 5, and 6: Hypervisor Fault Status */
	37	struct hv_fault_status fault_info;
	38
	39	/* Dcache line 7: Physical addresses of CPU send mondo block and CPU list. */
	40	unsigned long cpu_mondo_block_pa;
	41	unsigned long cpu_list_pa;
	42	unsigned long tsb_huge;
	43	unsigned long tsb_huge_temp;
	44
	45	/* Dcache line 8: IRQ work list, and keep trap_block a power-of-2 in size. */
	46	unsigned long irq_worklist_pa;
	47	unsigned int cpu_mondo_qmask;
	48	unsigned int dev_mondo_qmask;
	49	unsigned int resum_qmask;
	50	unsigned int nonresum_qmask;
5a5488d3	51	unsigned long __per_cpu_base;
19f0fa3f DM	52	} __attribute__((aligned(64)));
19f0fa3f DM	53	extern struct trap_per_cpu trap_block[NR_CPUS];
f05a6865 SR	54	void init_cur_cpu_trap(struct thread_info *);
f05a6865 SR	55	void setup_tba(void);
19f0fa3f DM	56	extern int ncpus_probed;
19f0fa3f DM	57
f05a6865	58	unsigned long real_hard_smp_processor_id(void);
19f0fa3f DM	59
	60	struct cpuid_patch_entry {
	61	unsigned int addr;
	62	unsigned int cheetah_safari[4];
	63	unsigned int cheetah_jbus[4];
	64	unsigned int starfire[4];
	65	unsigned int sun4v[4];
	66	};
	67	extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end;
	68
	69	struct sun4v_1insn_patch_entry {
	70	unsigned int addr;
	71	unsigned int insn;
	72	};
	73	extern struct sun4v_1insn_patch_entry __sun4v_1insn_patch,
	74	__sun4v_1insn_patch_end;
	75
	76	struct sun4v_2insn_patch_entry {
	77	unsigned int addr;
	78	unsigned int insns[2];
	79	};
	80	extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
	81	__sun4v_2insn_patch_end;
494e5b6f KA	82	extern struct sun4v_2insn_patch_entry __sun_m7_2insn_patch,
494e5b6f KA	83	__sun_m7_2insn_patch_end;
19f0fa3f DM	84
	85
	86	#endif /* !(__ASSEMBLY__) */
	87
	88	#define TRAP_PER_CPU_THREAD 0x00
	89	#define TRAP_PER_CPU_PGD_PADDR 0x08
	90	#define TRAP_PER_CPU_CPU_MONDO_PA 0x10
	91	#define TRAP_PER_CPU_DEV_MONDO_PA 0x18
	92	#define TRAP_PER_CPU_RESUM_MONDO_PA 0x20
	93	#define TRAP_PER_CPU_RESUM_KBUF_PA 0x28
	94	#define TRAP_PER_CPU_NONRESUM_MONDO_PA 0x30
	95	#define TRAP_PER_CPU_NONRESUM_KBUF_PA 0x38
	96	#define TRAP_PER_CPU_FAULT_INFO 0x40
	97	#define TRAP_PER_CPU_CPU_MONDO_BLOCK_PA 0xc0
	98	#define TRAP_PER_CPU_CPU_LIST_PA 0xc8
	99	#define TRAP_PER_CPU_TSB_HUGE 0xd0
	100	#define TRAP_PER_CPU_TSB_HUGE_TEMP 0xd8
	101	#define TRAP_PER_CPU_IRQ_WORKLIST_PA 0xe0
	102	#define TRAP_PER_CPU_CPU_MONDO_QMASK 0xe8
	103	#define TRAP_PER_CPU_DEV_MONDO_QMASK 0xec
	104	#define TRAP_PER_CPU_RESUM_QMASK 0xf0
	105	#define TRAP_PER_CPU_NONRESUM_QMASK 0xf4
5a5488d3	106	#define TRAP_PER_CPU_PER_CPU_BASE 0xf8
19f0fa3f DM	107
	108	#define TRAP_BLOCK_SZ_SHIFT 8
	109
	110	#include <asm/scratchpad.h>
	111
	112	#define __GET_CPUID(REG) \
	113	/* Spitfire implementation (default). */ \
	114	661: ldxa [%g0] ASI_UPA_CONFIG, REG; \
	115	srlx REG, 17, REG; \
	116	and REG, 0x1f, REG; \
	117	nop; \
	118	.section .cpuid_patch, "ax"; \
	119	/* Instruction location. */ \
	120	.word 661b; \
	121	/* Cheetah Safari implementation. */ \
	122	ldxa [%g0] ASI_SAFARI_CONFIG, REG; \
	123	srlx REG, 17, REG; \
	124	and REG, 0x3ff, REG; \
	125	nop; \
	126	/* Cheetah JBUS implementation. */ \
	127	ldxa [%g0] ASI_JBUS_CONFIG, REG; \
	128	srlx REG, 17, REG; \
	129	and REG, 0x1f, REG; \
	130	nop; \
	131	/* Starfire implementation. */ \
	132	sethi %hi(0x1fff40000d0 >> 9), REG; \
	133	sllx REG, 9, REG; \
	134	or REG, 0xd0, REG; \
	135	lduwa [REG] ASI_PHYS_BYPASS_EC_E, REG;\
	136	/* sun4v implementation. */ \
	137	mov SCRATCHPAD_CPUID, REG; \
	138	ldxa [REG] ASI_SCRATCHPAD, REG; \
	139	nop; \
	140	nop; \
	141	.previous;
	142
	143	#ifdef CONFIG_SMP
	144
	145	#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
	146	__GET_CPUID(TMP) \
	147	sethi %hi(trap_block), DEST; \
	148	sllx TMP, TRAP_BLOCK_SZ_SHIFT, TMP; \
	149	or DEST, %lo(trap_block), DEST; \
	150	add DEST, TMP, DEST; \
	151
	152	/* Clobbers TMP, current address space PGD phys address into DEST. */
	153	#define TRAP_LOAD_PGD_PHYS(DEST, TMP) \
	154	TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
	155	ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
	156
	157	/* Clobbers TMP, loads local processor's IRQ work area into DEST. */
	158	#define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP) \
	159	TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
	160	add DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST;
	161
	162	/* Clobbers TMP, loads DEST with current thread info pointer. */
	163	#define TRAP_LOAD_THREAD_REG(DEST, TMP) \
	164	TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
	165	ldx [DEST + TRAP_PER_CPU_THREAD], DEST;
	166
	167	/* Given the current thread info pointer in THR, load the per-cpu
	168	* area base of the current processor into DEST. REG1, REG2, and REG3 are
	169	* clobbered.
	170	*
171	* You absolutely cannot use DEST as a temporary in this code. The
172	* reason is that traps can happen during execution, and return from
173	* trap will load the fully resolved DEST per-cpu base. This can corrupt
174	* the calculations done by the macro mid-stream.
175	*/
176	#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) \
177	lduh [THR + TI_CPU], REG1; \
5a5488d3 DM	178	sethi %hi(trap_block), REG2; \
	179	sllx REG1, TRAP_BLOCK_SZ_SHIFT, REG1; \
	180	or REG2, %lo(trap_block), REG2; \
	181	add REG2, REG1, REG2; \
	182	ldx [REG2 + TRAP_PER_CPU_PER_CPU_BASE], DEST;
19f0fa3f DM	183
	184	#else
	185
	186	#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
	187	sethi %hi(trap_block), DEST; \
	188	or DEST, %lo(trap_block), DEST; \
	189
	190	/* Uniprocessor versions, we know the cpuid is zero. */
	191	#define TRAP_LOAD_PGD_PHYS(DEST, TMP) \
	192	TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
	193	ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
	194
	195	/* Clobbers TMP, loads local processor's IRQ work area into DEST. */
	196	#define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP) \
	197	TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
	198	add DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST;
	199
	200	#define TRAP_LOAD_THREAD_REG(DEST, TMP) \
	201	TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
	202	ldx [DEST + TRAP_PER_CPU_THREAD], DEST;
	203
	204	/* No per-cpu areas on uniprocessor, so no need to load DEST. */
	205	#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)
	206
	207	#endif /* !(CONFIG_SMP) */
	208
	209	#endif /* _SPARC_TRAP_BLOCK_H */