Commit | Line | Data |
---|---|---|
b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
19f0fa3f DM |
2 | #ifndef _SPARC_TRAP_BLOCK_H |
3 | #define _SPARC_TRAP_BLOCK_H | |
4 | ||
5 | #include <asm/hypervisor.h> | |
6 | #include <asm/asi.h> | |
7 | ||
8 | #ifndef __ASSEMBLY__ | |
9 | ||
10 | /* Trap handling code needs to get at a few critical values upon | |
11 | * trap entry and to process TSB misses. These cannot be in the | |
12 | * per_cpu() area as we really need to lock them into the TLB and | |
13 | * thus make them part of the main kernel image. As a result we | |
14 | * try to make this as small as possible. | |
15 | * | |
16 | * This is padded out and aligned to 64-bytes to avoid false sharing | |
17 | * on SMP. | |
18 | */ | |
19 | ||
20 | /* If you modify the size of this structure, please update | |
21 | * TRAP_BLOCK_SZ_SHIFT below. | |
22 | */ | |
23 | struct thread_info; | |
24 | struct trap_per_cpu { | |
25 | /* D-cache line 1: Basic thread information, cpu and device mondo queues */ | |
26 | struct thread_info *thread; | |
27 | unsigned long pgd_paddr; | |
28 | unsigned long cpu_mondo_pa; | |
29 | unsigned long dev_mondo_pa; | |
30 | ||
31 | /* D-cache line 2: Error Mondo Queue and kernel buffer pointers */ | |
32 | unsigned long resum_mondo_pa; | |
33 | unsigned long resum_kernel_buf_pa; | |
34 | unsigned long nonresum_mondo_pa; | |
35 | unsigned long nonresum_kernel_buf_pa; | |
36 | ||
37 | /* Dcache lines 3, 4, 5, and 6: Hypervisor Fault Status */ | |
38 | struct hv_fault_status fault_info; | |
39 | ||
40 | /* Dcache line 7: Physical addresses of CPU send mondo block and CPU list. */ | |
41 | unsigned long cpu_mondo_block_pa; | |
42 | unsigned long cpu_list_pa; | |
43 | unsigned long tsb_huge; | |
44 | unsigned long tsb_huge_temp; | |
45 | ||
46 | /* Dcache line 8: IRQ work list, and keep trap_block a power-of-2 in size. */ | |
47 | unsigned long irq_worklist_pa; | |
48 | unsigned int cpu_mondo_qmask; | |
49 | unsigned int dev_mondo_qmask; | |
50 | unsigned int resum_qmask; | |
51 | unsigned int nonresum_qmask; | |
5a5488d3 | 52 | unsigned long __per_cpu_base; |
19f0fa3f DM |
53 | } __attribute__((aligned(64))); |
54 | extern struct trap_per_cpu trap_block[NR_CPUS]; | |
f05a6865 SR |
55 | void init_cur_cpu_trap(struct thread_info *); |
56 | void setup_tba(void); | |
19f0fa3f | 57 | extern int ncpus_probed; |
9d53caec | 58 | extern u64 cpu_mondo_counter[NR_CPUS]; |
19f0fa3f | 59 | |
f05a6865 | 60 | unsigned long real_hard_smp_processor_id(void); |
19f0fa3f DM |
61 | |
62 | struct cpuid_patch_entry { | |
63 | unsigned int addr; | |
64 | unsigned int cheetah_safari[4]; | |
65 | unsigned int cheetah_jbus[4]; | |
66 | unsigned int starfire[4]; | |
67 | unsigned int sun4v[4]; | |
68 | }; | |
69 | extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end; | |
70 | ||
71 | struct sun4v_1insn_patch_entry { | |
72 | unsigned int addr; | |
73 | unsigned int insn; | |
74 | }; | |
75 | extern struct sun4v_1insn_patch_entry __sun4v_1insn_patch, | |
76 | __sun4v_1insn_patch_end; | |
a7159a87 AY |
77 | extern struct sun4v_1insn_patch_entry __fast_win_ctrl_1insn_patch, |
78 | __fast_win_ctrl_1insn_patch_end; | |
19f0fa3f DM |
79 | |
80 | struct sun4v_2insn_patch_entry { | |
81 | unsigned int addr; | |
82 | unsigned int insns[2]; | |
83 | }; | |
84 | extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch, | |
85 | __sun4v_2insn_patch_end; | |
494e5b6f KA |
86 | extern struct sun4v_2insn_patch_entry __sun_m7_2insn_patch, |
87 | __sun_m7_2insn_patch_end; | |
19f0fa3f DM |
88 | |
89 | ||
90 | #endif /* !(__ASSEMBLY__) */ | |
91 | ||
92 | #define TRAP_PER_CPU_THREAD 0x00 | |
93 | #define TRAP_PER_CPU_PGD_PADDR 0x08 | |
94 | #define TRAP_PER_CPU_CPU_MONDO_PA 0x10 | |
95 | #define TRAP_PER_CPU_DEV_MONDO_PA 0x18 | |
96 | #define TRAP_PER_CPU_RESUM_MONDO_PA 0x20 | |
97 | #define TRAP_PER_CPU_RESUM_KBUF_PA 0x28 | |
98 | #define TRAP_PER_CPU_NONRESUM_MONDO_PA 0x30 | |
99 | #define TRAP_PER_CPU_NONRESUM_KBUF_PA 0x38 | |
100 | #define TRAP_PER_CPU_FAULT_INFO 0x40 | |
101 | #define TRAP_PER_CPU_CPU_MONDO_BLOCK_PA 0xc0 | |
102 | #define TRAP_PER_CPU_CPU_LIST_PA 0xc8 | |
103 | #define TRAP_PER_CPU_TSB_HUGE 0xd0 | |
104 | #define TRAP_PER_CPU_TSB_HUGE_TEMP 0xd8 | |
105 | #define TRAP_PER_CPU_IRQ_WORKLIST_PA 0xe0 | |
106 | #define TRAP_PER_CPU_CPU_MONDO_QMASK 0xe8 | |
107 | #define TRAP_PER_CPU_DEV_MONDO_QMASK 0xec | |
108 | #define TRAP_PER_CPU_RESUM_QMASK 0xf0 | |
109 | #define TRAP_PER_CPU_NONRESUM_QMASK 0xf4 | |
5a5488d3 | 110 | #define TRAP_PER_CPU_PER_CPU_BASE 0xf8 |
19f0fa3f DM |
111 | |
112 | #define TRAP_BLOCK_SZ_SHIFT 8 | |
113 | ||
114 | #include <asm/scratchpad.h> | |
115 | ||
116 | #define __GET_CPUID(REG) \ | |
117 | /* Spitfire implementation (default). */ \ | |
118 | 661: ldxa [%g0] ASI_UPA_CONFIG, REG; \ | |
119 | srlx REG, 17, REG; \ | |
120 | and REG, 0x1f, REG; \ | |
121 | nop; \ | |
122 | .section .cpuid_patch, "ax"; \ | |
123 | /* Instruction location. */ \ | |
124 | .word 661b; \ | |
125 | /* Cheetah Safari implementation. */ \ | |
126 | ldxa [%g0] ASI_SAFARI_CONFIG, REG; \ | |
127 | srlx REG, 17, REG; \ | |
128 | and REG, 0x3ff, REG; \ | |
129 | nop; \ | |
130 | /* Cheetah JBUS implementation. */ \ | |
131 | ldxa [%g0] ASI_JBUS_CONFIG, REG; \ | |
132 | srlx REG, 17, REG; \ | |
133 | and REG, 0x1f, REG; \ | |
134 | nop; \ | |
135 | /* Starfire implementation. */ \ | |
136 | sethi %hi(0x1fff40000d0 >> 9), REG; \ | |
137 | sllx REG, 9, REG; \ | |
138 | or REG, 0xd0, REG; \ | |
139 | lduwa [REG] ASI_PHYS_BYPASS_EC_E, REG;\ | |
140 | /* sun4v implementation. */ \ | |
141 | mov SCRATCHPAD_CPUID, REG; \ | |
142 | ldxa [REG] ASI_SCRATCHPAD, REG; \ | |
143 | nop; \ | |
144 | nop; \ | |
145 | .previous; | |
146 | ||
147 | #ifdef CONFIG_SMP | |
148 | ||
149 | #define TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ | |
150 | __GET_CPUID(TMP) \ | |
151 | sethi %hi(trap_block), DEST; \ | |
152 | sllx TMP, TRAP_BLOCK_SZ_SHIFT, TMP; \ | |
153 | or DEST, %lo(trap_block), DEST; \ | |
154 | add DEST, TMP, DEST; \ | |
155 | ||
156 | /* Clobbers TMP, current address space PGD phys address into DEST. */ | |
157 | #define TRAP_LOAD_PGD_PHYS(DEST, TMP) \ | |
158 | TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ | |
159 | ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST; | |
160 | ||
161 | /* Clobbers TMP, loads local processor's IRQ work area into DEST. */ | |
162 | #define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP) \ | |
163 | TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ | |
164 | add DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST; | |
165 | ||
166 | /* Clobbers TMP, loads DEST with current thread info pointer. */ | |
167 | #define TRAP_LOAD_THREAD_REG(DEST, TMP) \ | |
168 | TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ | |
169 | ldx [DEST + TRAP_PER_CPU_THREAD], DEST; | |
170 | ||
171 | /* Given the current thread info pointer in THR, load the per-cpu | |
172 | * area base of the current processor into DEST. REG1, REG2, and REG3 are | |
173 | * clobbered. | |
174 | * | |
175 | * You absolutely cannot use DEST as a temporary in this code. The | |
176 | * reason is that traps can happen during execution, and return from | |
177 | * trap will load the fully resolved DEST per-cpu base. This can corrupt | |
178 | * the calculations done by the macro mid-stream. | |
179 | */ | |
180 | #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) \ | |
181 | lduh [THR + TI_CPU], REG1; \ | |
5a5488d3 DM |
182 | sethi %hi(trap_block), REG2; \ |
183 | sllx REG1, TRAP_BLOCK_SZ_SHIFT, REG1; \ | |
184 | or REG2, %lo(trap_block), REG2; \ | |
185 | add REG2, REG1, REG2; \ | |
186 | ldx [REG2 + TRAP_PER_CPU_PER_CPU_BASE], DEST; | |
19f0fa3f DM |
187 | |
188 | #else | |
189 | ||
190 | #define TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ | |
191 | sethi %hi(trap_block), DEST; \ | |
192 | or DEST, %lo(trap_block), DEST; \ | |
193 | ||
194 | /* Uniprocessor versions, we know the cpuid is zero. */ | |
195 | #define TRAP_LOAD_PGD_PHYS(DEST, TMP) \ | |
196 | TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ | |
197 | ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST; | |
198 | ||
199 | /* Clobbers TMP, loads local processor's IRQ work area into DEST. */ | |
200 | #define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP) \ | |
201 | TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ | |
202 | add DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST; | |
203 | ||
204 | #define TRAP_LOAD_THREAD_REG(DEST, TMP) \ | |
205 | TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \ | |
206 | ldx [DEST + TRAP_PER_CPU_THREAD], DEST; | |
207 | ||
208 | /* No per-cpu areas on uniprocessor, so no need to load DEST. */ | |
209 | #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) | |
210 | ||
211 | #endif /* !(CONFIG_SMP) */ | |
212 | ||
213 | #endif /* _SPARC_TRAP_BLOCK_H */ |