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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
f5e706ad SR |
2 | #ifndef _ASM_SPARC64_TOPOLOGY_H |
3 | #define _ASM_SPARC64_TOPOLOGY_H | |
4 | ||
5 | #ifdef CONFIG_NUMA | |
6 | ||
7 | #include <asm/mmzone.h> | |
8 | ||
9 | static inline int cpu_to_node(int cpu) | |
10 | { | |
11 | return numa_cpu_lookup_table[cpu]; | |
12 | } | |
13 | ||
14 | #define parent_node(node) (node) | |
15 | ||
e5981fd6 AB |
16 | #define cpumask_of_node(node) ((node) == -1 ? \ |
17 | cpu_all_mask : \ | |
18 | &numa_cpumask_lookup_table[node]) | |
f5e706ad | 19 | |
f5e706ad SR |
20 | struct pci_bus; |
21 | #ifdef CONFIG_PCI | |
f05a6865 | 22 | int pcibus_to_node(struct pci_bus *pbus); |
f5e706ad SR |
23 | #else |
24 | static inline int pcibus_to_node(struct pci_bus *pbus) | |
25 | { | |
26 | return -1; | |
27 | } | |
28 | #endif | |
29 | ||
9d079337 DM |
30 | #define cpumask_of_pcibus(bus) \ |
31 | (pcibus_to_node(bus) == -1 ? \ | |
e9b37512 | 32 | cpu_all_mask : \ |
9d079337 | 33 | cpumask_of_node(pcibus_to_node(bus))) |
f5e706ad | 34 | |
52708d69 NG |
35 | int __node_distance(int, int); |
36 | #define node_distance(a, b) __node_distance(a, b) | |
37 | ||
f5e706ad SR |
38 | #else /* CONFIG_NUMA */ |
39 | ||
40 | #include <asm-generic/topology.h> | |
41 | ||
42 | #endif /* !(CONFIG_NUMA) */ | |
43 | ||
44 | #ifdef CONFIG_SMP | |
fc5e8c28 BH |
45 | |
46 | #include <asm/cpudata.h> | |
47 | ||
f5e706ad SR |
48 | #define topology_physical_package_id(cpu) (cpu_data(cpu).proc_id) |
49 | #define topology_core_id(cpu) (cpu_data(cpu).core_id) | |
acc455cf | 50 | #define topology_core_cpumask(cpu) (&cpu_core_sib_map[cpu]) |
d624716b | 51 | #define topology_core_cache_cpumask(cpu) (&cpu_core_sib_cache_map[cpu]) |
06931e62 | 52 | #define topology_sibling_cpumask(cpu) (&per_cpu(cpu_sibling_map, cpu)) |
f5e706ad SR |
53 | #endif /* CONFIG_SMP */ |
54 | ||
3905c54f | 55 | extern cpumask_t cpu_core_map[NR_CPUS]; |
acc455cf | 56 | extern cpumask_t cpu_core_sib_map[NR_CPUS]; |
d624716b AP |
57 | extern cpumask_t cpu_core_sib_cache_map[NR_CPUS]; |
58 | ||
59 | /** | |
60 | * Return cores that shares the last level cache. | |
61 | */ | |
3905c54f SR |
62 | static inline const struct cpumask *cpu_coregroup_mask(int cpu) |
63 | { | |
d624716b | 64 | return &cpu_core_sib_cache_map[cpu]; |
3905c54f | 65 | } |
f5e706ad SR |
66 | |
67 | #endif /* _ASM_SPARC64_TOPOLOGY_H */ |