projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
License cleanup: add SPDX GPL-2.0 license identifier to files with no license
[linux-block.git] / arch / sparc / include / asm / pgtable_64.h
CommitLineData
b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
f5e706ad
SR		 2/*
3 * pgtable.h: SpitFire page table operations.
4 *
5 * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu)
6 * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
7 */
8
9#ifndef _SPARC64_PGTABLE_H
10#define _SPARC64_PGTABLE_H
11
12/* This file contains the functions and defines necessary to modify and use
13 * the SpitFire page tables.
14 */
15
9849a569 16#include <asm-generic/5level-fixup.h>
f5e706ad
SR		 17#include <linux/compiler.h>
18#include <linux/const.h>
19#include <asm/types.h>
20#include <asm/spitfire.h>
21#include <asm/asi.h>
f5e706ad
SR		 22#include <asm/page.h>
23#include <asm/processor.h>
24
25/* The kernel image occupies 0x4000000 to 0x6000000 (4MB --> 96MB).
26 * The page copy blockops can use 0x6000000 to 0x8000000.
b18eb2d7
DM		 27 * The 8K TSB is mapped in the 0x8000000 to 0x8400000 range.
28 * The 4M TSB is mapped in the 0x8400000 to 0x8800000 range.
f5e706ad
SR		 29 * The PROM resides in an area spanning 0xf0000000 to 0x100000000.
30 * The vmalloc area spans 0x100000000 to 0x200000000.
31 * Since modules need to be in the lowest 32-bits of the address space,
32 * we place them right before the OBP area from 0x10000000 to 0xf0000000.
33 * There is a single static kernel PMD which maps from 0x0 to address
34 * 0x400000000.
35 */
36#define TLBTEMP_BASE _AC(0x0000000006000000,UL)
b18eb2d7
DM		 37#define TSBMAP_8K_BASE _AC(0x0000000008000000,UL)
38#define TSBMAP_4M_BASE _AC(0x0000000008400000,UL)
f5e706ad
SR		 39#define MODULES_VADDR _AC(0x0000000010000000,UL)
40#define MODULES_LEN _AC(0x00000000e0000000,UL)
41#define MODULES_END _AC(0x00000000f0000000,UL)
42#define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL)
43#define HI_OBP_ADDRESS _AC(0x0000000100000000,UL)
44#define VMALLOC_START _AC(0x0000000100000000,UL)
bb4e6e85 45#define VMEMMAP_BASE VMALLOC_END
f5e706ad 46
f5e706ad
SR		 47/* PMD_SHIFT determines the size of the area a second-level page
48 * table can map
49 */
37b3a8ff 50#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3))
f5e706ad
SR		 51#define PMD_SIZE (_AC(1,UL) << PMD_SHIFT)
52#define PMD_MASK (~(PMD_SIZE-1))
2b77933c 53#define PMD_BITS (PAGE_SHIFT - 3)
f5e706ad 54
ac55c768
DM		 55/* PUD_SHIFT determines the size of the area a third-level page
56 * table can map
57 */
58#define PUD_SHIFT (PMD_SHIFT + PMD_BITS)
59#define PUD_SIZE (_AC(1,UL) << PUD_SHIFT)
60#define PUD_MASK (~(PUD_SIZE-1))
61#define PUD_BITS (PAGE_SHIFT - 3)
62
63/* PGDIR_SHIFT determines what a fourth-level page table entry can map */
64#define PGDIR_SHIFT (PUD_SHIFT + PUD_BITS)
f5e706ad
SR		 65#define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT)
66#define PGDIR_MASK (~(PGDIR_SIZE-1))
2b77933c 67#define PGDIR_BITS (PAGE_SHIFT - 3)
f5e706ad 68
7c0fa0f2
DM		 69#if (MAX_PHYS_ADDRESS_BITS > PGDIR_SHIFT + PGDIR_BITS)
70#error MAX_PHYS_ADDRESS_BITS exceeds what kernel page tables can support
71#endif
72
ac55c768 73#if (PGDIR_SHIFT + PGDIR_BITS) != 53
56a70b8c
DM		 74#error Page table parameters do not cover virtual address space properly.
75#endif
76
9e695d2e
DM		 77#if (PMD_SHIFT != HPAGE_SHIFT)
78#error PMD_SHIFT must equal HPAGE_SHIFT for transparent huge pages.
79#endif
80
f5e706ad
SR		 81#ifndef __ASSEMBLY__
82
bb4e6e85
DM		 83extern unsigned long VMALLOC_END;
84
85#define vmemmap ((struct page *)VMEMMAP_BASE)
86
f5e706ad
SR		 87#include <linux/sched.h>
88
0dd5b7b0 89bool kern_addr_valid(unsigned long addr);
26cf4325 90
f5e706ad 91/* Entries per page directory level. */
37b3a8ff 92#define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3))
f5e706ad 93#define PTRS_PER_PMD (1UL << PMD_BITS)
ac55c768 94#define PTRS_PER_PUD (1UL << PUD_BITS)
f5e706ad
SR		 95#define PTRS_PER_PGD (1UL << PGDIR_BITS)
96
97/* Kernel has a separate 44bit address space. */
d016bf7e 98#define FIRST_USER_ADDRESS 0UL
f5e706ad 99
fe866433
DM		 100#define pmd_ERROR(e) \
101 pr_err("%s:%d: bad pmd %p(%016lx) seen at (%pS)\n", \
102 __FILE__, __LINE__, &(e), pmd_val(e), __builtin_return_address(0))
ac55c768
DM		 103#define pud_ERROR(e) \
104 pr_err("%s:%d: bad pud %p(%016lx) seen at (%pS)\n", \
105 __FILE__, __LINE__, &(e), pud_val(e), __builtin_return_address(0))
fe866433
DM		 106#define pgd_ERROR(e) \
107 pr_err("%s:%d: bad pgd %p(%016lx) seen at (%pS)\n", \
108 __FILE__, __LINE__, &(e), pgd_val(e), __builtin_return_address(0))
f5e706ad
SR		 109
110#endif /* !(__ASSEMBLY__) */
111
112/* PTE bits which are the same in SUN4U and SUN4V format. */
113#define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */
114#define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/
683d2fa6 115#define _PAGE_SPECIAL _AC(0x0200000000000000,UL) /* Special page */
a7b9403f 116#define _PAGE_PMD_HUGE _AC(0x0100000000000000,UL) /* Huge page */
0dd5b7b0 117#define _PAGE_PUD_HUGE _PAGE_PMD_HUGE
683d2fa6
DM		 118
119/* Advertise support for _PAGE_SPECIAL */
120#define __HAVE_ARCH_PTE_SPECIAL
f5e706ad
SR		 121
122/* SUN4U pte bits... */
123#define _PAGE_SZ4MB_4U _AC(0x6000000000000000,UL) /* 4MB Page */
124#define _PAGE_SZ512K_4U _AC(0x4000000000000000,UL) /* 512K Page */
125#define _PAGE_SZ64K_4U _AC(0x2000000000000000,UL) /* 64K Page */
126#define _PAGE_SZ8K_4U _AC(0x0000000000000000,UL) /* 8K Page */
127#define _PAGE_NFO_4U _AC(0x1000000000000000,UL) /* No Fault Only */
128#define _PAGE_IE_4U _AC(0x0800000000000000,UL) /* Invert Endianness */
129#define _PAGE_SOFT2_4U _AC(0x07FC000000000000,UL) /* Software bits, set 2 */
683d2fa6 130#define _PAGE_SPECIAL_4U _AC(0x0200000000000000,UL) /* Special page */
a7b9403f 131#define _PAGE_PMD_HUGE_4U _AC(0x0100000000000000,UL) /* Huge page */
f5e706ad
SR		 132#define _PAGE_RES1_4U _AC(0x0002000000000000,UL) /* Reserved */
133#define _PAGE_SZ32MB_4U _AC(0x0001000000000000,UL) /* (Panther) 32MB page */
134#define _PAGE_SZ256MB_4U _AC(0x2001000000000000,UL) /* (Panther) 256MB page */
135#define _PAGE_SZALL_4U _AC(0x6001000000000000,UL) /* All pgsz bits */
136#define _PAGE_SN_4U _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */
137#define _PAGE_RES2_4U _AC(0x0000780000000000,UL) /* Reserved */
138#define _PAGE_PADDR_4U _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13] */
139#define _PAGE_SOFT_4U _AC(0x0000000000001F80,UL) /* Software bits: */
140#define _PAGE_EXEC_4U _AC(0x0000000000001000,UL) /* Executable SW bit */
141#define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty) */
f5e706ad
SR		 142#define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd) */
143#define _PAGE_READ_4U _AC(0x0000000000000200,UL) /* Readable SW Bit */
144#define _PAGE_WRITE_4U _AC(0x0000000000000100,UL) /* Writable SW Bit */
145#define _PAGE_PRESENT_4U _AC(0x0000000000000080,UL) /* Present */
146#define _PAGE_L_4U _AC(0x0000000000000040,UL) /* Locked TTE */
147#define _PAGE_CP_4U _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */
148#define _PAGE_CV_4U _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */
149#define _PAGE_E_4U _AC(0x0000000000000008,UL) /* side-Effect */
150#define _PAGE_P_4U _AC(0x0000000000000004,UL) /* Privileged Page */
151#define _PAGE_W_4U _AC(0x0000000000000002,UL) /* Writable */
152
153/* SUN4V pte bits... */
154#define _PAGE_NFO_4V _AC(0x4000000000000000,UL) /* No Fault Only */
155#define _PAGE_SOFT2_4V _AC(0x3F00000000000000,UL) /* Software bits, set 2 */
156#define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty) */
157#define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd) */
158#define _PAGE_READ_4V _AC(0x0800000000000000,UL) /* Readable SW Bit */
159#define _PAGE_WRITE_4V _AC(0x0400000000000000,UL) /* Writable SW Bit */
683d2fa6 160#define _PAGE_SPECIAL_4V _AC(0x0200000000000000,UL) /* Special page */
a7b9403f 161#define _PAGE_PMD_HUGE_4V _AC(0x0100000000000000,UL) /* Huge page */
f5e706ad
SR		 162#define _PAGE_PADDR_4V _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13] */
163#define _PAGE_IE_4V _AC(0x0000000000001000,UL) /* Invert Endianness */
164#define _PAGE_E_4V _AC(0x0000000000000800,UL) /* side-Effect */
165#define _PAGE_CP_4V _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */
166#define _PAGE_CV_4V _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */
167#define _PAGE_P_4V _AC(0x0000000000000100,UL) /* Privileged Page */
168#define _PAGE_EXEC_4V _AC(0x0000000000000080,UL) /* Executable Page */
169#define _PAGE_W_4V _AC(0x0000000000000040,UL) /* Writable */
170#define _PAGE_SOFT_4V _AC(0x0000000000000030,UL) /* Software bits */
f5e706ad
SR		 171#define _PAGE_PRESENT_4V _AC(0x0000000000000010,UL) /* Present */
172#define _PAGE_RESV_4V _AC(0x0000000000000008,UL) /* Reserved */
173#define _PAGE_SZ16GB_4V _AC(0x0000000000000007,UL) /* 16GB Page */
174#define _PAGE_SZ2GB_4V _AC(0x0000000000000006,UL) /* 2GB Page */
175#define _PAGE_SZ256MB_4V _AC(0x0000000000000005,UL) /* 256MB Page */
176#define _PAGE_SZ32MB_4V _AC(0x0000000000000004,UL) /* 32MB Page */
177#define _PAGE_SZ4MB_4V _AC(0x0000000000000003,UL) /* 4MB Page */
178#define _PAGE_SZ512K_4V _AC(0x0000000000000002,UL) /* 512K Page */
179#define _PAGE_SZ64K_4V _AC(0x0000000000000001,UL) /* 64K Page */
180#define _PAGE_SZ8K_4V _AC(0x0000000000000000,UL) /* 8K Page */
181#define _PAGE_SZALL_4V _AC(0x0000000000000007,UL) /* All pgsz bits */
182
f5e706ad
SR		 183#define _PAGE_SZBITS_4U _PAGE_SZ8K_4U
184#define _PAGE_SZBITS_4V _PAGE_SZ8K_4V
15b9350a 185
37b3a8ff
DM		 186#if REAL_HPAGE_SHIFT != 22
187#error REAL_HPAGE_SHIFT and _PAGE_SZHUGE_foo must match up
188#endif
189
f5e706ad
SR		 190#define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U
191#define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V
f5e706ad
SR		 192
193/* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */
194#define __P000 __pgprot(0)
195#define __P001 __pgprot(0)
196#define __P010 __pgprot(0)
197#define __P011 __pgprot(0)
198#define __P100 __pgprot(0)
199#define __P101 __pgprot(0)
200#define __P110 __pgprot(0)
201#define __P111 __pgprot(0)
202
203#define __S000 __pgprot(0)
204#define __S001 __pgprot(0)
205#define __S010 __pgprot(0)
206#define __S011 __pgprot(0)
207#define __S100 __pgprot(0)
208#define __S101 __pgprot(0)
209#define __S110 __pgprot(0)
210#define __S111 __pgprot(0)
211
212#ifndef __ASSEMBLY__
213
f05a6865 214pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long);
f5e706ad 215
f05a6865 216unsigned long pte_sz_bits(unsigned long size);
f5e706ad
SR		 217
218extern pgprot_t PAGE_KERNEL;
219extern pgprot_t PAGE_KERNEL_LOCKED;
220extern pgprot_t PAGE_COPY;
221extern pgprot_t PAGE_SHARED;
222
08f80073 223/* XXX This ugliness is for the atyfb driver's sparc mmap() support. XXX */
f5e706ad
SR		 224extern unsigned long _PAGE_IE;
225extern unsigned long _PAGE_E;
226extern unsigned long _PAGE_CACHE;
227
228extern unsigned long pg_iobits;
229extern unsigned long _PAGE_ALL_SZ_BITS;
f5e706ad
SR		 230
231extern struct page *mem_map_zero;
232#define ZERO_PAGE(vaddr) (mem_map_zero)
233
234/* PFNs are real physical page numbers. However, mem_map only begins to record
235 * per-page information starting at pfn_base. This is to handle systems where
236 * the first physical page in the machine is at some huge physical address,
237 * such as 4GB. This is common on a partitioned E10000, for example.
238 */
239static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
240{
241 unsigned long paddr = pfn << PAGE_SHIFT;
15b9350a
DM		 242
243 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL);
244 return __pte(paddr | pgprot_val(prot));
f5e706ad
SR		 245}
246#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
247
9e695d2e 248#ifdef CONFIG_TRANSPARENT_HUGEPAGE
a7b9403f 249static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot)
9e695d2e 250{
a7b9403f
DM		 251 pte_t pte = pfn_pte(page_nr, pgprot);
252
253 return __pmd(pte_val(pte));
9e695d2e 254}
a7b9403f 255#define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot))
9e695d2e
DM		 256#endif
257
f5e706ad
SR		 258/* This one can be done with two shifts. */
259static inline unsigned long pte_pfn(pte_t pte)
260{
261 unsigned long ret;
262
263 __asm__ __volatile__(
264 "\n661: sllx %1, %2, %0\n"
265 " srlx %0, %3, %0\n"
266 " .section .sun4v_2insn_patch, \"ax\"\n"
267 " .word 661b\n"
268 " sllx %1, %4, %0\n"
269 " srlx %0, %5, %0\n"
270 " .previous\n"
271 : "=r" (ret)
272 : "r" (pte_val(pte)),
273 "i" (21), "i" (21 + PAGE_SHIFT),
274 "i" (8), "i" (8 + PAGE_SHIFT));
275
276 return ret;
277}
278#define pte_page(x) pfn_to_page(pte_pfn(x))
279
280static inline pte_t pte_modify(pte_t pte, pgprot_t prot)
281{
282 unsigned long mask, tmp;
283
eaf85da8
DM		 284 /* SUN4U: 0x630107ffffffec38 (negated == 0x9cfef800000013c7)
285 * SUN4V: 0x33ffffffffffee07 (negated == 0xcc000000000011f8)
f5e706ad
SR		 286 *
287 * Even if we use negation tricks the result is still a 6
288 * instruction sequence, so don't try to play fancy and just
289 * do the most straightforward implementation.
290 *
291 * Note: We encode this into 3 sun4v 2-insn patch sequences.
292 */
293
15b9350a 294 BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL);
f5e706ad
SR		 295 __asm__ __volatile__(
296 "\n661: sethi %%uhi(%2), %1\n"
297 " sethi %%hi(%2), %0\n"
298 "\n662: or %1, %%ulo(%2), %1\n"
299 " or %0, %%lo(%2), %0\n"
300 "\n663: sllx %1, 32, %1\n"
301 " or %0, %1, %0\n"
302 " .section .sun4v_2insn_patch, \"ax\"\n"
303 " .word 661b\n"
304 " sethi %%uhi(%3), %1\n"
305 " sethi %%hi(%3), %0\n"
306 " .word 662b\n"
307 " or %1, %%ulo(%3), %1\n"
308 " or %0, %%lo(%3), %0\n"
309 " .word 663b\n"
310 " sllx %1, 32, %1\n"
311 " or %0, %1, %0\n"
312 " .previous\n"
494e5b6f
KA		 313 " .section .sun_m7_2insn_patch, \"ax\"\n"
314 " .word 661b\n"
315 " sethi %%uhi(%4), %1\n"
316 " sethi %%hi(%4), %0\n"
317 " .word 662b\n"
318 " or %1, %%ulo(%4), %1\n"
319 " or %0, %%lo(%4), %0\n"
320 " .word 663b\n"
321 " sllx %1, 32, %1\n"
322 " or %0, %1, %0\n"
323 " .previous\n"
f5e706ad
SR		 324 : "=r" (mask), "=r" (tmp)
325 : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U |
eaf85da8 326 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U |
a7b9403f 327 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4U),
f5e706ad 328 "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V |
eaf85da8 329 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V |
494e5b6f
KA		 330 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4V),
331 "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V |
332 _PAGE_CP_4V | _PAGE_E_4V |
a7b9403f 333 _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4V));
f5e706ad
SR		 334
335 return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask));
336}
337
a7b9403f
DM		 338#ifdef CONFIG_TRANSPARENT_HUGEPAGE
339static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
340{
341 pte_t pte = __pte(pmd_val(pmd));
342
343 pte = pte_modify(pte, newprot);
344
345 return __pmd(pte_val(pte));
346}
347#endif
348
f5e706ad
SR		 349static inline pgprot_t pgprot_noncached(pgprot_t prot)
350{
351 unsigned long val = pgprot_val(prot);
352
353 __asm__ __volatile__(
354 "\n661: andn %0, %2, %0\n"
355 " or %0, %3, %0\n"
356 " .section .sun4v_2insn_patch, \"ax\"\n"
357 " .word 661b\n"
358 " andn %0, %4, %0\n"
359 " or %0, %5, %0\n"
360 " .previous\n"
494e5b6f
KA		 361 " .section .sun_m7_2insn_patch, \"ax\"\n"
362 " .word 661b\n"
363 " andn %0, %6, %0\n"
364 " or %0, %5, %0\n"
365 " .previous\n"
f5e706ad
SR		 366 : "=r" (val)
367 : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U),
494e5b6f
KA		 368 "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V),
369 "i" (_PAGE_CP_4V));
f5e706ad
SR		 370
371 return __pgprot(val);
372}
373/* Various pieces of code check for platform support by ifdef testing
374 * on "pgprot_noncached". That's broken and should be fixed, but for
375 * now...
376 */
377#define pgprot_noncached pgprot_noncached
378
a7b9403f 379#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
c7d9f77d
NG		 380extern pte_t arch_make_huge_pte(pte_t entry, struct vm_area_struct *vma,
381 struct page *page, int writable);
382#define arch_make_huge_pte arch_make_huge_pte
383static inline unsigned long __pte_default_huge_mask(void)
f5e706ad
SR		 384{
385 unsigned long mask;
386
387 __asm__ __volatile__(
388 "\n661: sethi %%uhi(%1), %0\n"
389 " sllx %0, 32, %0\n"
390 " .section .sun4v_2insn_patch, \"ax\"\n"
391 " .word 661b\n"
392 " mov %2, %0\n"
393 " nop\n"
394 " .previous\n"
395 : "=r" (mask)
396 : "i" (_PAGE_SZHUGE_4U), "i" (_PAGE_SZHUGE_4V));
397
24e49ee3
NG		 398 return mask;
399}
400
401static inline pte_t pte_mkhuge(pte_t pte)
402{
c7d9f77d 403 return __pte(pte_val(pte) | __pte_default_huge_mask());
24e49ee3
NG		 404}
405
c7d9f77d 406static inline bool is_default_hugetlb_pte(pte_t pte)
24e49ee3 407{
c7d9f77d
NG		 408 unsigned long mask = __pte_default_huge_mask();
409
410 return (pte_val(pte) & mask) == mask;
f5e706ad 411}
24e49ee3 412
7bc3777c
NG		 413static inline bool is_hugetlb_pmd(pmd_t pmd)
414{
415 return !!(pmd_val(pmd) & _PAGE_PMD_HUGE);
416}
417
df7b2155
NG		 418static inline bool is_hugetlb_pud(pud_t pud)
419{
420 return !!(pud_val(pud) & _PAGE_PUD_HUGE);
421}
422
a7b9403f
DM		 423#ifdef CONFIG_TRANSPARENT_HUGEPAGE
424static inline pmd_t pmd_mkhuge(pmd_t pmd)
425{
426 pte_t pte = __pte(pmd_val(pmd));
427
428 pte = pte_mkhuge(pte);
429 pte_val(pte) |= _PAGE_PMD_HUGE;
430
431 return __pmd(pte_val(pte));
432}
433#endif
24e49ee3
NG		 434#else
435static inline bool is_hugetlb_pte(pte_t pte)
436{
437 return false;
438}
f5e706ad
SR		 439#endif
440
441static inline pte_t pte_mkdirty(pte_t pte)
442{
443 unsigned long val = pte_val(pte), tmp;
444
445 __asm__ __volatile__(
446 "\n661: or %0, %3, %0\n"
447 " nop\n"
448 "\n662: nop\n"
449 " nop\n"
450 " .section .sun4v_2insn_patch, \"ax\"\n"
451 " .word 661b\n"
452 " sethi %%uhi(%4), %1\n"
453 " sllx %1, 32, %1\n"
454 " .word 662b\n"
455 " or %1, %%lo(%4), %1\n"
456 " or %0, %1, %0\n"
457 " .previous\n"
458 : "=r" (val), "=r" (tmp)
459 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
460 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
461
462 return __pte(val);
463}
464
465static inline pte_t pte_mkclean(pte_t pte)
466{
467 unsigned long val = pte_val(pte), tmp;
468
469 __asm__ __volatile__(
470 "\n661: andn %0, %3, %0\n"
471 " nop\n"
472 "\n662: nop\n"
473 " nop\n"
474 " .section .sun4v_2insn_patch, \"ax\"\n"
475 " .word 661b\n"
476 " sethi %%uhi(%4), %1\n"
477 " sllx %1, 32, %1\n"
478 " .word 662b\n"
479 " or %1, %%lo(%4), %1\n"
480 " andn %0, %1, %0\n"
481 " .previous\n"
482 : "=r" (val), "=r" (tmp)
483 : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U),
484 "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V));
485
486 return __pte(val);
487}
488
489static inline pte_t pte_mkwrite(pte_t pte)
490{
491 unsigned long val = pte_val(pte), mask;
492
493 __asm__ __volatile__(
494 "\n661: mov %1, %0\n"
495 " nop\n"
496 " .section .sun4v_2insn_patch, \"ax\"\n"
497 " .word 661b\n"
498 " sethi %%uhi(%2), %0\n"
499 " sllx %0, 32, %0\n"
500 " .previous\n"
501 : "=r" (mask)
502 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
503
504 return __pte(val | mask);
505}
506
507static inline pte_t pte_wrprotect(pte_t pte)
508{
509 unsigned long val = pte_val(pte), tmp;
510
511 __asm__ __volatile__(
512 "\n661: andn %0, %3, %0\n"
513 " nop\n"
514 "\n662: nop\n"
515 " nop\n"
516 " .section .sun4v_2insn_patch, \"ax\"\n"
517 " .word 661b\n"
518 " sethi %%uhi(%4), %1\n"
519 " sllx %1, 32, %1\n"
520 " .word 662b\n"
521 " or %1, %%lo(%4), %1\n"
522 " andn %0, %1, %0\n"
523 " .previous\n"
524 : "=r" (val), "=r" (tmp)
525 : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U),
526 "i" (_PAGE_WRITE_4V | _PAGE_W_4V));
527
528 return __pte(val);
529}
530
531static inline pte_t pte_mkold(pte_t pte)
532{
533 unsigned long mask;
534
535 __asm__ __volatile__(
536 "\n661: mov %1, %0\n"
537 " nop\n"
538 " .section .sun4v_2insn_patch, \"ax\"\n"
539 " .word 661b\n"
540 " sethi %%uhi(%2), %0\n"
541 " sllx %0, 32, %0\n"
542 " .previous\n"
543 : "=r" (mask)
544 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
545
546 mask |= _PAGE_R;
547
548 return __pte(pte_val(pte) & ~mask);
549}
550
551static inline pte_t pte_mkyoung(pte_t pte)
552{
553 unsigned long mask;
554
555 __asm__ __volatile__(
556 "\n661: mov %1, %0\n"
557 " nop\n"
558 " .section .sun4v_2insn_patch, \"ax\"\n"
559 " .word 661b\n"
560 " sethi %%uhi(%2), %0\n"
561 " sllx %0, 32, %0\n"
562 " .previous\n"
563 : "=r" (mask)
564 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
565
566 mask |= _PAGE_R;
567
568 return __pte(pte_val(pte) | mask);
569}
570
571static inline pte_t pte_mkspecial(pte_t pte)
572{
683d2fa6 573 pte_val(pte) |= _PAGE_SPECIAL;
f5e706ad
SR		 574 return pte;
575}
576
577static inline unsigned long pte_young(pte_t pte)
578{
579 unsigned long mask;
580
581 __asm__ __volatile__(
582 "\n661: mov %1, %0\n"
583 " nop\n"
584 " .section .sun4v_2insn_patch, \"ax\"\n"
585 " .word 661b\n"
586 " sethi %%uhi(%2), %0\n"
587 " sllx %0, 32, %0\n"
588 " .previous\n"
589 : "=r" (mask)
590 : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V));
591
592 return (pte_val(pte) & mask);
593}
594
595static inline unsigned long pte_dirty(pte_t pte)
596{
597 unsigned long mask;
598
599 __asm__ __volatile__(
600 "\n661: mov %1, %0\n"
601 " nop\n"
602 " .section .sun4v_2insn_patch, \"ax\"\n"
603 " .word 661b\n"
604 " sethi %%uhi(%2), %0\n"
605 " sllx %0, 32, %0\n"
606 " .previous\n"
607 : "=r" (mask)
608 : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V));
609
610 return (pte_val(pte) & mask);
611}
612
613static inline unsigned long pte_write(pte_t pte)
614{
615 unsigned long mask;
616
617 __asm__ __volatile__(
618 "\n661: mov %1, %0\n"
619 " nop\n"
620 " .section .sun4v_2insn_patch, \"ax\"\n"
621 " .word 661b\n"
622 " sethi %%uhi(%2), %0\n"
623 " sllx %0, 32, %0\n"
624 " .previous\n"
625 : "=r" (mask)
626 : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V));
627
628 return (pte_val(pte) & mask);
629}
630
631static inline unsigned long pte_exec(pte_t pte)
632{
633 unsigned long mask;
634
635 __asm__ __volatile__(
636 "\n661: sethi %%hi(%1), %0\n"
637 " .section .sun4v_1insn_patch, \"ax\"\n"
638 " .word 661b\n"
639 " mov %2, %0\n"
640 " .previous\n"
641 : "=r" (mask)
642 : "i" (_PAGE_EXEC_4U), "i" (_PAGE_EXEC_4V));
643
644 return (pte_val(pte) & mask);
645}
646
f5e706ad
SR		 647static inline unsigned long pte_present(pte_t pte)
648{
649 unsigned long val = pte_val(pte);
650
651 __asm__ __volatile__(
652 "\n661: and %0, %2, %0\n"
653 " .section .sun4v_1insn_patch, \"ax\"\n"
654 " .word 661b\n"
655 " and %0, %3, %0\n"
656 " .previous\n"
657 : "=r" (val)
658 : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V));
659
660 return val;
661}
662
4a9d1946 663#define pte_accessible pte_accessible
20841405 664static inline unsigned long pte_accessible(struct mm_struct *mm, pte_t a)
4a9d1946
DM		 665{
666 return pte_val(a) & _PAGE_VALID;
667}
668
683d2fa6 669static inline unsigned long pte_special(pte_t pte)
f5e706ad 670{
683d2fa6 671 return pte_val(pte) & _PAGE_SPECIAL;
f5e706ad
SR		 672}
673
a7b9403f 674static inline unsigned long pmd_large(pmd_t pmd)
89a77915 675{
a7b9403f
DM		 676 pte_t pte = __pte(pmd_val(pmd));
677
04df419d 678 return pte_val(pte) & _PAGE_PMD_HUGE;
89a77915
DM		 679}
680
0dd5b7b0 681static inline unsigned long pmd_pfn(pmd_t pmd)
9e695d2e 682{
a7b9403f
DM		 683 pte_t pte = __pte(pmd_val(pmd));
684
0dd5b7b0 685 return pte_pfn(pte);
9e695d2e
DM		 686}
687
9ae34dbd
TH		 688#define __HAVE_ARCH_PMD_WRITE
689static inline unsigned long pmd_write(pmd_t pmd)
c164e038
KS		 690{
691 pte_t pte = __pte(pmd_val(pmd));
692
9ae34dbd 693 return pte_write(pte);
c164e038
KS		 694}
695
44382b01
NG		 696#define pud_write(pud) pte_write(__pte(pud_val(pud)))
697
9ae34dbd
TH		 698#ifdef CONFIG_TRANSPARENT_HUGEPAGE
699static inline unsigned long pmd_dirty(pmd_t pmd)
9e695d2e 700{
a7b9403f
DM		 701 pte_t pte = __pte(pmd_val(pmd));
702
9ae34dbd 703 return pte_dirty(pte);
9e695d2e
DM		 704}
705
9ae34dbd 706static inline unsigned long pmd_young(pmd_t pmd)
9e695d2e 707{
a7b9403f 708 pte_t pte = __pte(pmd_val(pmd));
9e695d2e 709
9ae34dbd 710 return pte_young(pte);
9e695d2e
DM		 711}
712
a7b9403f 713static inline unsigned long pmd_trans_huge(pmd_t pmd)
9e695d2e 714{
a7b9403f
DM		 715 pte_t pte = __pte(pmd_val(pmd));
716
717 return pte_val(pte) & _PAGE_PMD_HUGE;
9e695d2e
DM		 718}
719
9e695d2e
DM		 720static inline pmd_t pmd_mkold(pmd_t pmd)
721{
a7b9403f
DM		 722 pte_t pte = __pte(pmd_val(pmd));
723
724 pte = pte_mkold(pte);
725
726 return __pmd(pte_val(pte));
9e695d2e
DM		 727}
728
729static inline pmd_t pmd_wrprotect(pmd_t pmd)
730{
a7b9403f
DM		 731 pte_t pte = __pte(pmd_val(pmd));
732
733 pte = pte_wrprotect(pte);
734
735 return __pmd(pte_val(pte));
9e695d2e
DM		 736}
737
738static inline pmd_t pmd_mkdirty(pmd_t pmd)
739{
a7b9403f
DM		 740 pte_t pte = __pte(pmd_val(pmd));
741
742 pte = pte_mkdirty(pte);
743
744 return __pmd(pte_val(pte));
9e695d2e
DM		 745}
746
79cedb8f
MK		 747static inline pmd_t pmd_mkclean(pmd_t pmd)
748{
749 pte_t pte = __pte(pmd_val(pmd));
750
751 pte = pte_mkclean(pte);
752
753 return __pmd(pte_val(pte));
754}
755
9e695d2e
DM		 756static inline pmd_t pmd_mkyoung(pmd_t pmd)
757{
a7b9403f
DM		 758 pte_t pte = __pte(pmd_val(pmd));
759
760 pte = pte_mkyoung(pte);
761
762 return __pmd(pte_val(pte));
9e695d2e
DM		 763}
764
765static inline pmd_t pmd_mkwrite(pmd_t pmd)
766{
a7b9403f
DM		 767 pte_t pte = __pte(pmd_val(pmd));
768
769 pte = pte_mkwrite(pte);
770
a7b9403f 771 return __pmd(pte_val(pte));
9e695d2e
DM		 772}
773
a7b9403f
DM		 774static inline pgprot_t pmd_pgprot(pmd_t entry)
775{
776 unsigned long val = pmd_val(entry);
777
778 return __pgprot(val);
779}
9e695d2e
DM		 780#endif
781
782static inline int pmd_present(pmd_t pmd)
783{
2b77933c 784 return pmd_val(pmd) != 0UL;
9e695d2e
DM		 785}
786
787#define pmd_none(pmd) (!pmd_val(pmd))
788
26cf4325
DM		 789/* pmd_bad() is only called on non-trans-huge PMDs. Our encoding is
790 * very simple, it's just the physical address. PTE tables are of
791 * size PAGE_SIZE so make sure the sub-PAGE_SIZE bits are clear and
792 * the top bits outside of the range of any physical address size we
793 * support are clear as well. We also validate the physical itself.
794 */
0dd5b7b0 795#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
26cf4325
DM		 796
797#define pud_none(pud) (!pud_val(pud))
798
0dd5b7b0 799#define pud_bad(pud) (pud_val(pud) & ~PAGE_MASK)
26cf4325 800
ac55c768
DM		 801#define pgd_none(pgd) (!pgd_val(pgd))
802
0dd5b7b0 803#define pgd_bad(pgd) (pgd_val(pgd) & ~PAGE_MASK)
ac55c768 804
9e695d2e 805#ifdef CONFIG_TRANSPARENT_HUGEPAGE
f05a6865
SR		 806void set_pmd_at(struct mm_struct *mm, unsigned long addr,
807 pmd_t *pmdp, pmd_t pmd);
9e695d2e
DM		 808#else
809static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
810 pmd_t *pmdp, pmd_t pmd)
811{
812 *pmdp = pmd;
813}
814#endif
815
816static inline void pmd_set(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep)
817{
a7b9403f 818 unsigned long val = __pa((unsigned long) (ptep));
9e695d2e
DM		 819
820 pmd_val(*pmdp) = val;
821}
822
f5e706ad 823#define pud_set(pudp, pmdp) \
a7b9403f 824 (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp))))
9e695d2e
DM		 825static inline unsigned long __pmd_page(pmd_t pmd)
826{
a7b9403f
DM		 827 pte_t pte = __pte(pmd_val(pmd));
828 unsigned long pfn;
829
830 pfn = pte_pfn(pte);
831
832 return ((unsigned long) __va(pfn << PAGE_SHIFT));
9e695d2e 833}
44382b01
NG		 834
835static inline unsigned long pud_page_vaddr(pud_t pud)
836{
837 pte_t pte = __pte(pud_val(pud));
838 unsigned long pfn;
839
840 pfn = pte_pfn(pte);
841
842 return ((unsigned long) __va(pfn << PAGE_SHIFT));
843}
844
f5e706ad 845#define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd))
f5e706ad 846#define pud_page(pud) virt_to_page((void *)pud_page_vaddr(pud))
2b77933c 847#define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL)
f5e706ad 848#define pud_present(pud) (pud_val(pud) != 0U)
2b77933c 849#define pud_clear(pudp) (pud_val(*(pudp)) = 0UL)
ac55c768
DM		 850#define pgd_page_vaddr(pgd) \
851 ((unsigned long) __va(pgd_val(pgd)))
852#define pgd_present(pgd) (pgd_val(pgd) != 0U)
acff7fdb 853#define pgd_clear(pgdp) (pgd_val(*(pgdp)) = 0UL)
f5e706ad 854
0dd5b7b0
DM		 855static inline unsigned long pud_large(pud_t pud)
856{
857 pte_t pte = __pte(pud_val(pud));
858
859 return pte_val(pte) & _PAGE_PMD_HUGE;
860}
861
862static inline unsigned long pud_pfn(pud_t pud)
863{
864 pte_t pte = __pte(pud_val(pud));
865
866 return pte_pfn(pte);
867}
868
f5e706ad
SR		 869/* Same in both SUN4V and SUN4U. */
870#define pte_none(pte) (!pte_val(pte))
871
ac55c768
DM		 872#define pgd_set(pgdp, pudp) \
873 (pgd_val(*(pgdp)) = (__pa((unsigned long) (pudp))))
874
f5e706ad
SR		 875/* to find an entry in a page-table-directory. */
876#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
877#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
878
879/* to find an entry in a kernel page-table-directory */
880#define pgd_offset_k(address) pgd_offset(&init_mm, address)
881
ac55c768
DM		 882/* Find an entry in the third-level page table.. */
883#define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))
884#define pud_offset(pgdp, address) \
885 ((pud_t *) pgd_page_vaddr(*(pgdp)) + pud_index(address))
886
f5e706ad
SR		 887/* Find an entry in the second-level page table.. */
888#define pmd_offset(pudp, address) \
889 ((pmd_t *) pud_page_vaddr(*(pudp)) + \
890 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)))
891
892/* Find an entry in the third-level page table.. */
893#define pte_index(dir, address) \
894 ((pte_t *) __pmd_page(*(dir)) + \
895 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
896#define pte_offset_kernel pte_index
897#define pte_offset_map pte_index
f5e706ad 898#define pte_unmap(pte) do { } while (0)
f5e706ad 899
589ee628
IM		 900/* We cannot include <linux/mm_types.h> at this point yet: */
901extern struct mm_struct init_mm;
902
f5e706ad 903/* Actual page table PTE updates. */
f05a6865 904void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr,
c7d9f77d
NG		 905 pte_t *ptep, pte_t orig, int fullmm,
906 unsigned int hugepage_shift);
f5e706ad 907
24e49ee3 908static void maybe_tlb_batch_add(struct mm_struct *mm, unsigned long vaddr,
c7d9f77d
NG		 909 pte_t *ptep, pte_t orig, int fullmm,
910 unsigned int hugepage_shift)
24e49ee3
NG		 911{
912 /* It is more efficient to let flush_tlb_kernel_range()
913 * handle init_mm tlb flushes.
914 *
915 * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U
916 * and SUN4V pte layout, so this inline test is fine.
917 */
918 if (likely(mm != &init_mm) && pte_accessible(mm, orig))
c7d9f77d 919 tlb_batch_add(mm, vaddr, ptep, orig, fullmm, hugepage_shift);
24e49ee3
NG		 920}
921
8809aa2d
AK		 922#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
923static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
924 unsigned long addr,
925 pmd_t *pmdp)
9e695d2e
DM		 926{
927 pmd_t pmd = *pmdp;
2b77933c 928 set_pmd_at(mm, addr, pmdp, __pmd(0UL));
9e695d2e
DM		 929 return pmd;
930}
931
90f08e39
PZ		 932static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
933 pte_t *ptep, pte_t pte, int fullmm)
f5e706ad
SR		 934{
935 pte_t orig = *ptep;
936
937 *ptep = pte;
c7d9f77d 938 maybe_tlb_batch_add(mm, addr, ptep, orig, fullmm, PAGE_SHIFT);
f5e706ad
SR		 939}
940
90f08e39
PZ		 941#define set_pte_at(mm,addr,ptep,pte) \
942 __set_pte_at((mm), (addr), (ptep), (pte), 0)
943
f5e706ad
SR		 944#define pte_clear(mm,addr,ptep) \
945 set_pte_at((mm), (addr), (ptep), __pte(0UL))
946
90f08e39
PZ		 947#define __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL
948#define pte_clear_not_present_full(mm,addr,ptep,fullmm) \
949 __set_pte_at((mm), (addr), (ptep), __pte(0UL), (fullmm))
950
f5e706ad
SR		 951#ifdef DCACHE_ALIASING_POSSIBLE
952#define __HAVE_ARCH_MOVE_PTE
953#define move_pte(pte, prot, old_addr, new_addr) \
954({ \
955 pte_t newpte = (pte); \
956 if (tlb_type != hypervisor && pte_present(pte)) { \
957 unsigned long this_pfn = pte_pfn(pte); \
958 \
959 if (pfn_valid(this_pfn) && \
960 (((old_addr) ^ (new_addr)) & (1 << 13))) \
961 flush_dcache_page_all(current->mm, \
962 pfn_to_page(this_pfn)); \
963 } \
964 newpte; \
965})
966#endif
967
2b77933c 968extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
f5e706ad 969
f05a6865
SR		 970void paging_init(void);
971unsigned long find_ecache_flush_span(unsigned long size);
f5e706ad 972
cb1b8209 973struct seq_file;
f05a6865 974void mmu_info(struct seq_file *);
cb1b8209 975
f5e706ad 976struct vm_area_struct;
f05a6865 977void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
9e695d2e 978#ifdef CONFIG_TRANSPARENT_HUGEPAGE
f05a6865
SR		 979void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
980 pmd_t *pmd);
9e695d2e 981
51e5ef1b
DM		 982#define __HAVE_ARCH_PMDP_INVALIDATE
983extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
984 pmd_t *pmdp);
985
9e695d2e 986#define __HAVE_ARCH_PGTABLE_DEPOSIT
f05a6865
SR		 987void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
988 pgtable_t pgtable);
9e695d2e
DM		 989
990#define __HAVE_ARCH_PGTABLE_WITHDRAW
f05a6865 991pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
9e695d2e 992#endif
f5e706ad
SR		 993
994/* Encode and de-code a swap entry */
995#define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL)
996#define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL))
997#define __swp_entry(type, offset) \
998 ( (swp_entry_t) \
999 { \
1000 (((long)(type) << PAGE_SHIFT) | \
1001 ((long)(offset) << (PAGE_SHIFT + 8UL))) \
1002 } )
1003#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
1004#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
1005
f05a6865 1006int page_in_phys_avail(unsigned long paddr);
f5e706ad 1007
f5e706ad
SR		 1008/*
1009 * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
1010 * its high 4 bits. These macros/functions put it there or get it from there.
1011 */
1012#define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4)))
1013#define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4))
1014#define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL)
1015
f05a6865
SR		 1016int remap_pfn_range(struct vm_area_struct *, unsigned long, unsigned long,
1017 unsigned long, pgprot_t);
3e37fd31
DM		 1018
1019static inline int io_remap_pfn_range(struct vm_area_struct *vma,
1020 unsigned long from, unsigned long pfn,
1021 unsigned long size, pgprot_t prot)
1022{
1023 unsigned long offset = GET_PFN(pfn) << PAGE_SHIFT;
1024 int space = GET_IOSPACE(pfn);
1025 unsigned long phys_base;
1026
1027 phys_base = offset | (((unsigned long) space) << 32UL);
1028
1029 return remap_pfn_range(vma, from, phys_base >> PAGE_SHIFT, size, prot);
1030}
40d158e6 1031#define io_remap_pfn_range io_remap_pfn_range
3e37fd31 1032
f36391d2 1033#include <asm/tlbflush.h>
f5e706ad
SR		 1034#include <asm-generic/pgtable.h>
1035
1036/* We provide our own get_unmapped_area to cope with VA holes and
1037 * SHM area cache aliasing for userland.
1038 */
1039#define HAVE_ARCH_UNMAPPED_AREA
1040#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
1041
1042/* We provide a special get_unmapped_area for framebuffer mmaps to try and use
1043 * the largest alignment possible such that larget PTEs can be used.
1044 */
f05a6865
SR		 1045unsigned long get_fb_unmapped_area(struct file *filp, unsigned long,
1046 unsigned long, unsigned long,
1047 unsigned long);
f5e706ad
SR		 1048#define HAVE_ARCH_FB_UNMAPPED_AREA
1049
f05a6865
SR		 1050void pgtable_cache_init(void);
1051void sun4v_register_fault_status(void);
1052void sun4v_ktsb_register(void);
1053void __init cheetah_ecache_flush_init(void);
1054void sun4v_patch_tlb_handlers(void);
f5e706ad
SR		 1055
1056extern unsigned long cmdline_memory_size;
1057
f05a6865 1058asmlinkage void do_sparc64_fault(struct pt_regs *regs);
b539c467 1059
f5e706ad
SR		 1060#endif /* !(__ASSEMBLY__) */
1061
1062#endif /* !(_SPARC64_PGTABLE_H) */
Linux 6.x block layer and io_uring tree(s)