Commit | Line | Data |
---|---|---|
f5e706ad SR |
1 | /* |
2 | * pgtable.h: SpitFire page table operations. | |
3 | * | |
4 | * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu) | |
5 | * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) | |
6 | */ | |
7 | ||
8 | #ifndef _SPARC64_PGTABLE_H | |
9 | #define _SPARC64_PGTABLE_H | |
10 | ||
11 | /* This file contains the functions and defines necessary to modify and use | |
12 | * the SpitFire page tables. | |
13 | */ | |
14 | ||
f5e706ad SR |
15 | #include <linux/compiler.h> |
16 | #include <linux/const.h> | |
17 | #include <asm/types.h> | |
18 | #include <asm/spitfire.h> | |
19 | #include <asm/asi.h> | |
f5e706ad SR |
20 | #include <asm/page.h> |
21 | #include <asm/processor.h> | |
22 | ||
23 | /* The kernel image occupies 0x4000000 to 0x6000000 (4MB --> 96MB). | |
24 | * The page copy blockops can use 0x6000000 to 0x8000000. | |
b18eb2d7 DM |
25 | * The 8K TSB is mapped in the 0x8000000 to 0x8400000 range. |
26 | * The 4M TSB is mapped in the 0x8400000 to 0x8800000 range. | |
f5e706ad SR |
27 | * The PROM resides in an area spanning 0xf0000000 to 0x100000000. |
28 | * The vmalloc area spans 0x100000000 to 0x200000000. | |
29 | * Since modules need to be in the lowest 32-bits of the address space, | |
30 | * we place them right before the OBP area from 0x10000000 to 0xf0000000. | |
31 | * There is a single static kernel PMD which maps from 0x0 to address | |
32 | * 0x400000000. | |
33 | */ | |
34 | #define TLBTEMP_BASE _AC(0x0000000006000000,UL) | |
b18eb2d7 DM |
35 | #define TSBMAP_8K_BASE _AC(0x0000000008000000,UL) |
36 | #define TSBMAP_4M_BASE _AC(0x0000000008400000,UL) | |
f5e706ad SR |
37 | #define MODULES_VADDR _AC(0x0000000010000000,UL) |
38 | #define MODULES_LEN _AC(0x00000000e0000000,UL) | |
39 | #define MODULES_END _AC(0x00000000f0000000,UL) | |
40 | #define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL) | |
41 | #define HI_OBP_ADDRESS _AC(0x0000000100000000,UL) | |
42 | #define VMALLOC_START _AC(0x0000000100000000,UL) | |
bb4e6e85 | 43 | #define VMEMMAP_BASE VMALLOC_END |
f5e706ad | 44 | |
f5e706ad SR |
45 | /* PMD_SHIFT determines the size of the area a second-level page |
46 | * table can map | |
47 | */ | |
37b3a8ff | 48 | #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3)) |
f5e706ad SR |
49 | #define PMD_SIZE (_AC(1,UL) << PMD_SHIFT) |
50 | #define PMD_MASK (~(PMD_SIZE-1)) | |
2b77933c | 51 | #define PMD_BITS (PAGE_SHIFT - 3) |
f5e706ad | 52 | |
ac55c768 DM |
53 | /* PUD_SHIFT determines the size of the area a third-level page |
54 | * table can map | |
55 | */ | |
56 | #define PUD_SHIFT (PMD_SHIFT + PMD_BITS) | |
57 | #define PUD_SIZE (_AC(1,UL) << PUD_SHIFT) | |
58 | #define PUD_MASK (~(PUD_SIZE-1)) | |
59 | #define PUD_BITS (PAGE_SHIFT - 3) | |
60 | ||
61 | /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ | |
62 | #define PGDIR_SHIFT (PUD_SHIFT + PUD_BITS) | |
f5e706ad SR |
63 | #define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT) |
64 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
2b77933c | 65 | #define PGDIR_BITS (PAGE_SHIFT - 3) |
f5e706ad | 66 | |
7c0fa0f2 DM |
67 | #if (MAX_PHYS_ADDRESS_BITS > PGDIR_SHIFT + PGDIR_BITS) |
68 | #error MAX_PHYS_ADDRESS_BITS exceeds what kernel page tables can support | |
69 | #endif | |
70 | ||
ac55c768 | 71 | #if (PGDIR_SHIFT + PGDIR_BITS) != 53 |
56a70b8c DM |
72 | #error Page table parameters do not cover virtual address space properly. |
73 | #endif | |
74 | ||
9e695d2e DM |
75 | #if (PMD_SHIFT != HPAGE_SHIFT) |
76 | #error PMD_SHIFT must equal HPAGE_SHIFT for transparent huge pages. | |
77 | #endif | |
78 | ||
f5e706ad SR |
79 | #ifndef __ASSEMBLY__ |
80 | ||
bb4e6e85 DM |
81 | extern unsigned long VMALLOC_END; |
82 | ||
83 | #define vmemmap ((struct page *)VMEMMAP_BASE) | |
84 | ||
f5e706ad SR |
85 | #include <linux/sched.h> |
86 | ||
0dd5b7b0 | 87 | bool kern_addr_valid(unsigned long addr); |
26cf4325 | 88 | |
f5e706ad | 89 | /* Entries per page directory level. */ |
37b3a8ff | 90 | #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3)) |
f5e706ad | 91 | #define PTRS_PER_PMD (1UL << PMD_BITS) |
ac55c768 | 92 | #define PTRS_PER_PUD (1UL << PUD_BITS) |
f5e706ad SR |
93 | #define PTRS_PER_PGD (1UL << PGDIR_BITS) |
94 | ||
95 | /* Kernel has a separate 44bit address space. */ | |
d016bf7e | 96 | #define FIRST_USER_ADDRESS 0UL |
f5e706ad | 97 | |
fe866433 DM |
98 | #define pmd_ERROR(e) \ |
99 | pr_err("%s:%d: bad pmd %p(%016lx) seen at (%pS)\n", \ | |
100 | __FILE__, __LINE__, &(e), pmd_val(e), __builtin_return_address(0)) | |
ac55c768 DM |
101 | #define pud_ERROR(e) \ |
102 | pr_err("%s:%d: bad pud %p(%016lx) seen at (%pS)\n", \ | |
103 | __FILE__, __LINE__, &(e), pud_val(e), __builtin_return_address(0)) | |
fe866433 DM |
104 | #define pgd_ERROR(e) \ |
105 | pr_err("%s:%d: bad pgd %p(%016lx) seen at (%pS)\n", \ | |
106 | __FILE__, __LINE__, &(e), pgd_val(e), __builtin_return_address(0)) | |
f5e706ad SR |
107 | |
108 | #endif /* !(__ASSEMBLY__) */ | |
109 | ||
110 | /* PTE bits which are the same in SUN4U and SUN4V format. */ | |
111 | #define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */ | |
112 | #define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/ | |
683d2fa6 | 113 | #define _PAGE_SPECIAL _AC(0x0200000000000000,UL) /* Special page */ |
a7b9403f | 114 | #define _PAGE_PMD_HUGE _AC(0x0100000000000000,UL) /* Huge page */ |
0dd5b7b0 | 115 | #define _PAGE_PUD_HUGE _PAGE_PMD_HUGE |
683d2fa6 DM |
116 | |
117 | /* Advertise support for _PAGE_SPECIAL */ | |
118 | #define __HAVE_ARCH_PTE_SPECIAL | |
f5e706ad SR |
119 | |
120 | /* SUN4U pte bits... */ | |
121 | #define _PAGE_SZ4MB_4U _AC(0x6000000000000000,UL) /* 4MB Page */ | |
122 | #define _PAGE_SZ512K_4U _AC(0x4000000000000000,UL) /* 512K Page */ | |
123 | #define _PAGE_SZ64K_4U _AC(0x2000000000000000,UL) /* 64K Page */ | |
124 | #define _PAGE_SZ8K_4U _AC(0x0000000000000000,UL) /* 8K Page */ | |
125 | #define _PAGE_NFO_4U _AC(0x1000000000000000,UL) /* No Fault Only */ | |
126 | #define _PAGE_IE_4U _AC(0x0800000000000000,UL) /* Invert Endianness */ | |
127 | #define _PAGE_SOFT2_4U _AC(0x07FC000000000000,UL) /* Software bits, set 2 */ | |
683d2fa6 | 128 | #define _PAGE_SPECIAL_4U _AC(0x0200000000000000,UL) /* Special page */ |
a7b9403f | 129 | #define _PAGE_PMD_HUGE_4U _AC(0x0100000000000000,UL) /* Huge page */ |
f5e706ad SR |
130 | #define _PAGE_RES1_4U _AC(0x0002000000000000,UL) /* Reserved */ |
131 | #define _PAGE_SZ32MB_4U _AC(0x0001000000000000,UL) /* (Panther) 32MB page */ | |
132 | #define _PAGE_SZ256MB_4U _AC(0x2001000000000000,UL) /* (Panther) 256MB page */ | |
133 | #define _PAGE_SZALL_4U _AC(0x6001000000000000,UL) /* All pgsz bits */ | |
134 | #define _PAGE_SN_4U _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */ | |
135 | #define _PAGE_RES2_4U _AC(0x0000780000000000,UL) /* Reserved */ | |
136 | #define _PAGE_PADDR_4U _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13] */ | |
137 | #define _PAGE_SOFT_4U _AC(0x0000000000001F80,UL) /* Software bits: */ | |
138 | #define _PAGE_EXEC_4U _AC(0x0000000000001000,UL) /* Executable SW bit */ | |
139 | #define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty) */ | |
f5e706ad SR |
140 | #define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd) */ |
141 | #define _PAGE_READ_4U _AC(0x0000000000000200,UL) /* Readable SW Bit */ | |
142 | #define _PAGE_WRITE_4U _AC(0x0000000000000100,UL) /* Writable SW Bit */ | |
143 | #define _PAGE_PRESENT_4U _AC(0x0000000000000080,UL) /* Present */ | |
144 | #define _PAGE_L_4U _AC(0x0000000000000040,UL) /* Locked TTE */ | |
145 | #define _PAGE_CP_4U _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */ | |
146 | #define _PAGE_CV_4U _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */ | |
147 | #define _PAGE_E_4U _AC(0x0000000000000008,UL) /* side-Effect */ | |
148 | #define _PAGE_P_4U _AC(0x0000000000000004,UL) /* Privileged Page */ | |
149 | #define _PAGE_W_4U _AC(0x0000000000000002,UL) /* Writable */ | |
150 | ||
151 | /* SUN4V pte bits... */ | |
152 | #define _PAGE_NFO_4V _AC(0x4000000000000000,UL) /* No Fault Only */ | |
153 | #define _PAGE_SOFT2_4V _AC(0x3F00000000000000,UL) /* Software bits, set 2 */ | |
154 | #define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty) */ | |
155 | #define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd) */ | |
156 | #define _PAGE_READ_4V _AC(0x0800000000000000,UL) /* Readable SW Bit */ | |
157 | #define _PAGE_WRITE_4V _AC(0x0400000000000000,UL) /* Writable SW Bit */ | |
683d2fa6 | 158 | #define _PAGE_SPECIAL_4V _AC(0x0200000000000000,UL) /* Special page */ |
a7b9403f | 159 | #define _PAGE_PMD_HUGE_4V _AC(0x0100000000000000,UL) /* Huge page */ |
f5e706ad SR |
160 | #define _PAGE_PADDR_4V _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13] */ |
161 | #define _PAGE_IE_4V _AC(0x0000000000001000,UL) /* Invert Endianness */ | |
162 | #define _PAGE_E_4V _AC(0x0000000000000800,UL) /* side-Effect */ | |
163 | #define _PAGE_CP_4V _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */ | |
164 | #define _PAGE_CV_4V _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */ | |
165 | #define _PAGE_P_4V _AC(0x0000000000000100,UL) /* Privileged Page */ | |
166 | #define _PAGE_EXEC_4V _AC(0x0000000000000080,UL) /* Executable Page */ | |
167 | #define _PAGE_W_4V _AC(0x0000000000000040,UL) /* Writable */ | |
168 | #define _PAGE_SOFT_4V _AC(0x0000000000000030,UL) /* Software bits */ | |
f5e706ad SR |
169 | #define _PAGE_PRESENT_4V _AC(0x0000000000000010,UL) /* Present */ |
170 | #define _PAGE_RESV_4V _AC(0x0000000000000008,UL) /* Reserved */ | |
171 | #define _PAGE_SZ16GB_4V _AC(0x0000000000000007,UL) /* 16GB Page */ | |
172 | #define _PAGE_SZ2GB_4V _AC(0x0000000000000006,UL) /* 2GB Page */ | |
173 | #define _PAGE_SZ256MB_4V _AC(0x0000000000000005,UL) /* 256MB Page */ | |
174 | #define _PAGE_SZ32MB_4V _AC(0x0000000000000004,UL) /* 32MB Page */ | |
175 | #define _PAGE_SZ4MB_4V _AC(0x0000000000000003,UL) /* 4MB Page */ | |
176 | #define _PAGE_SZ512K_4V _AC(0x0000000000000002,UL) /* 512K Page */ | |
177 | #define _PAGE_SZ64K_4V _AC(0x0000000000000001,UL) /* 64K Page */ | |
178 | #define _PAGE_SZ8K_4V _AC(0x0000000000000000,UL) /* 8K Page */ | |
179 | #define _PAGE_SZALL_4V _AC(0x0000000000000007,UL) /* All pgsz bits */ | |
180 | ||
f5e706ad SR |
181 | #define _PAGE_SZBITS_4U _PAGE_SZ8K_4U |
182 | #define _PAGE_SZBITS_4V _PAGE_SZ8K_4V | |
15b9350a | 183 | |
37b3a8ff DM |
184 | #if REAL_HPAGE_SHIFT != 22 |
185 | #error REAL_HPAGE_SHIFT and _PAGE_SZHUGE_foo must match up | |
186 | #endif | |
187 | ||
f5e706ad SR |
188 | #define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U |
189 | #define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V | |
f5e706ad SR |
190 | |
191 | /* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */ | |
192 | #define __P000 __pgprot(0) | |
193 | #define __P001 __pgprot(0) | |
194 | #define __P010 __pgprot(0) | |
195 | #define __P011 __pgprot(0) | |
196 | #define __P100 __pgprot(0) | |
197 | #define __P101 __pgprot(0) | |
198 | #define __P110 __pgprot(0) | |
199 | #define __P111 __pgprot(0) | |
200 | ||
201 | #define __S000 __pgprot(0) | |
202 | #define __S001 __pgprot(0) | |
203 | #define __S010 __pgprot(0) | |
204 | #define __S011 __pgprot(0) | |
205 | #define __S100 __pgprot(0) | |
206 | #define __S101 __pgprot(0) | |
207 | #define __S110 __pgprot(0) | |
208 | #define __S111 __pgprot(0) | |
209 | ||
210 | #ifndef __ASSEMBLY__ | |
211 | ||
f05a6865 | 212 | pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long); |
f5e706ad | 213 | |
f05a6865 | 214 | unsigned long pte_sz_bits(unsigned long size); |
f5e706ad SR |
215 | |
216 | extern pgprot_t PAGE_KERNEL; | |
217 | extern pgprot_t PAGE_KERNEL_LOCKED; | |
218 | extern pgprot_t PAGE_COPY; | |
219 | extern pgprot_t PAGE_SHARED; | |
220 | ||
08f80073 | 221 | /* XXX This ugliness is for the atyfb driver's sparc mmap() support. XXX */ |
f5e706ad SR |
222 | extern unsigned long _PAGE_IE; |
223 | extern unsigned long _PAGE_E; | |
224 | extern unsigned long _PAGE_CACHE; | |
225 | ||
226 | extern unsigned long pg_iobits; | |
227 | extern unsigned long _PAGE_ALL_SZ_BITS; | |
f5e706ad SR |
228 | |
229 | extern struct page *mem_map_zero; | |
230 | #define ZERO_PAGE(vaddr) (mem_map_zero) | |
231 | ||
232 | /* PFNs are real physical page numbers. However, mem_map only begins to record | |
233 | * per-page information starting at pfn_base. This is to handle systems where | |
234 | * the first physical page in the machine is at some huge physical address, | |
235 | * such as 4GB. This is common on a partitioned E10000, for example. | |
236 | */ | |
237 | static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) | |
238 | { | |
239 | unsigned long paddr = pfn << PAGE_SHIFT; | |
15b9350a DM |
240 | |
241 | BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL); | |
242 | return __pte(paddr | pgprot_val(prot)); | |
f5e706ad SR |
243 | } |
244 | #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) | |
245 | ||
9e695d2e | 246 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
a7b9403f | 247 | static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot) |
9e695d2e | 248 | { |
a7b9403f DM |
249 | pte_t pte = pfn_pte(page_nr, pgprot); |
250 | ||
251 | return __pmd(pte_val(pte)); | |
9e695d2e | 252 | } |
a7b9403f | 253 | #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) |
9e695d2e DM |
254 | #endif |
255 | ||
f5e706ad SR |
256 | /* This one can be done with two shifts. */ |
257 | static inline unsigned long pte_pfn(pte_t pte) | |
258 | { | |
259 | unsigned long ret; | |
260 | ||
261 | __asm__ __volatile__( | |
262 | "\n661: sllx %1, %2, %0\n" | |
263 | " srlx %0, %3, %0\n" | |
264 | " .section .sun4v_2insn_patch, \"ax\"\n" | |
265 | " .word 661b\n" | |
266 | " sllx %1, %4, %0\n" | |
267 | " srlx %0, %5, %0\n" | |
268 | " .previous\n" | |
269 | : "=r" (ret) | |
270 | : "r" (pte_val(pte)), | |
271 | "i" (21), "i" (21 + PAGE_SHIFT), | |
272 | "i" (8), "i" (8 + PAGE_SHIFT)); | |
273 | ||
274 | return ret; | |
275 | } | |
276 | #define pte_page(x) pfn_to_page(pte_pfn(x)) | |
277 | ||
278 | static inline pte_t pte_modify(pte_t pte, pgprot_t prot) | |
279 | { | |
280 | unsigned long mask, tmp; | |
281 | ||
eaf85da8 DM |
282 | /* SUN4U: 0x630107ffffffec38 (negated == 0x9cfef800000013c7) |
283 | * SUN4V: 0x33ffffffffffee07 (negated == 0xcc000000000011f8) | |
f5e706ad SR |
284 | * |
285 | * Even if we use negation tricks the result is still a 6 | |
286 | * instruction sequence, so don't try to play fancy and just | |
287 | * do the most straightforward implementation. | |
288 | * | |
289 | * Note: We encode this into 3 sun4v 2-insn patch sequences. | |
290 | */ | |
291 | ||
15b9350a | 292 | BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL); |
f5e706ad SR |
293 | __asm__ __volatile__( |
294 | "\n661: sethi %%uhi(%2), %1\n" | |
295 | " sethi %%hi(%2), %0\n" | |
296 | "\n662: or %1, %%ulo(%2), %1\n" | |
297 | " or %0, %%lo(%2), %0\n" | |
298 | "\n663: sllx %1, 32, %1\n" | |
299 | " or %0, %1, %0\n" | |
300 | " .section .sun4v_2insn_patch, \"ax\"\n" | |
301 | " .word 661b\n" | |
302 | " sethi %%uhi(%3), %1\n" | |
303 | " sethi %%hi(%3), %0\n" | |
304 | " .word 662b\n" | |
305 | " or %1, %%ulo(%3), %1\n" | |
306 | " or %0, %%lo(%3), %0\n" | |
307 | " .word 663b\n" | |
308 | " sllx %1, 32, %1\n" | |
309 | " or %0, %1, %0\n" | |
310 | " .previous\n" | |
494e5b6f KA |
311 | " .section .sun_m7_2insn_patch, \"ax\"\n" |
312 | " .word 661b\n" | |
313 | " sethi %%uhi(%4), %1\n" | |
314 | " sethi %%hi(%4), %0\n" | |
315 | " .word 662b\n" | |
316 | " or %1, %%ulo(%4), %1\n" | |
317 | " or %0, %%lo(%4), %0\n" | |
318 | " .word 663b\n" | |
319 | " sllx %1, 32, %1\n" | |
320 | " or %0, %1, %0\n" | |
321 | " .previous\n" | |
f5e706ad SR |
322 | : "=r" (mask), "=r" (tmp) |
323 | : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U | | |
eaf85da8 | 324 | _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U | |
a7b9403f | 325 | _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4U), |
f5e706ad | 326 | "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V | |
eaf85da8 | 327 | _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V | |
494e5b6f KA |
328 | _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4V), |
329 | "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V | | |
330 | _PAGE_CP_4V | _PAGE_E_4V | | |
a7b9403f | 331 | _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4V)); |
f5e706ad SR |
332 | |
333 | return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask)); | |
334 | } | |
335 | ||
a7b9403f DM |
336 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
337 | static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) | |
338 | { | |
339 | pte_t pte = __pte(pmd_val(pmd)); | |
340 | ||
341 | pte = pte_modify(pte, newprot); | |
342 | ||
343 | return __pmd(pte_val(pte)); | |
344 | } | |
345 | #endif | |
346 | ||
f5e706ad SR |
347 | static inline pgprot_t pgprot_noncached(pgprot_t prot) |
348 | { | |
349 | unsigned long val = pgprot_val(prot); | |
350 | ||
351 | __asm__ __volatile__( | |
352 | "\n661: andn %0, %2, %0\n" | |
353 | " or %0, %3, %0\n" | |
354 | " .section .sun4v_2insn_patch, \"ax\"\n" | |
355 | " .word 661b\n" | |
356 | " andn %0, %4, %0\n" | |
357 | " or %0, %5, %0\n" | |
358 | " .previous\n" | |
494e5b6f KA |
359 | " .section .sun_m7_2insn_patch, \"ax\"\n" |
360 | " .word 661b\n" | |
361 | " andn %0, %6, %0\n" | |
362 | " or %0, %5, %0\n" | |
363 | " .previous\n" | |
f5e706ad SR |
364 | : "=r" (val) |
365 | : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U), | |
494e5b6f KA |
366 | "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V), |
367 | "i" (_PAGE_CP_4V)); | |
f5e706ad SR |
368 | |
369 | return __pgprot(val); | |
370 | } | |
371 | /* Various pieces of code check for platform support by ifdef testing | |
372 | * on "pgprot_noncached". That's broken and should be fixed, but for | |
373 | * now... | |
374 | */ | |
375 | #define pgprot_noncached pgprot_noncached | |
376 | ||
a7b9403f | 377 | #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) |
c7d9f77d NG |
378 | extern pte_t arch_make_huge_pte(pte_t entry, struct vm_area_struct *vma, |
379 | struct page *page, int writable); | |
380 | #define arch_make_huge_pte arch_make_huge_pte | |
381 | static inline unsigned long __pte_default_huge_mask(void) | |
f5e706ad SR |
382 | { |
383 | unsigned long mask; | |
384 | ||
385 | __asm__ __volatile__( | |
386 | "\n661: sethi %%uhi(%1), %0\n" | |
387 | " sllx %0, 32, %0\n" | |
388 | " .section .sun4v_2insn_patch, \"ax\"\n" | |
389 | " .word 661b\n" | |
390 | " mov %2, %0\n" | |
391 | " nop\n" | |
392 | " .previous\n" | |
393 | : "=r" (mask) | |
394 | : "i" (_PAGE_SZHUGE_4U), "i" (_PAGE_SZHUGE_4V)); | |
395 | ||
24e49ee3 NG |
396 | return mask; |
397 | } | |
398 | ||
399 | static inline pte_t pte_mkhuge(pte_t pte) | |
400 | { | |
c7d9f77d | 401 | return __pte(pte_val(pte) | __pte_default_huge_mask()); |
24e49ee3 NG |
402 | } |
403 | ||
c7d9f77d | 404 | static inline bool is_default_hugetlb_pte(pte_t pte) |
24e49ee3 | 405 | { |
c7d9f77d NG |
406 | unsigned long mask = __pte_default_huge_mask(); |
407 | ||
408 | return (pte_val(pte) & mask) == mask; | |
f5e706ad | 409 | } |
24e49ee3 | 410 | |
7bc3777c NG |
411 | static inline bool is_hugetlb_pmd(pmd_t pmd) |
412 | { | |
413 | return !!(pmd_val(pmd) & _PAGE_PMD_HUGE); | |
414 | } | |
415 | ||
a7b9403f DM |
416 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
417 | static inline pmd_t pmd_mkhuge(pmd_t pmd) | |
418 | { | |
419 | pte_t pte = __pte(pmd_val(pmd)); | |
420 | ||
421 | pte = pte_mkhuge(pte); | |
422 | pte_val(pte) |= _PAGE_PMD_HUGE; | |
423 | ||
424 | return __pmd(pte_val(pte)); | |
425 | } | |
426 | #endif | |
24e49ee3 NG |
427 | #else |
428 | static inline bool is_hugetlb_pte(pte_t pte) | |
429 | { | |
430 | return false; | |
431 | } | |
f5e706ad SR |
432 | #endif |
433 | ||
434 | static inline pte_t pte_mkdirty(pte_t pte) | |
435 | { | |
436 | unsigned long val = pte_val(pte), tmp; | |
437 | ||
438 | __asm__ __volatile__( | |
439 | "\n661: or %0, %3, %0\n" | |
440 | " nop\n" | |
441 | "\n662: nop\n" | |
442 | " nop\n" | |
443 | " .section .sun4v_2insn_patch, \"ax\"\n" | |
444 | " .word 661b\n" | |
445 | " sethi %%uhi(%4), %1\n" | |
446 | " sllx %1, 32, %1\n" | |
447 | " .word 662b\n" | |
448 | " or %1, %%lo(%4), %1\n" | |
449 | " or %0, %1, %0\n" | |
450 | " .previous\n" | |
451 | : "=r" (val), "=r" (tmp) | |
452 | : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U), | |
453 | "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V)); | |
454 | ||
455 | return __pte(val); | |
456 | } | |
457 | ||
458 | static inline pte_t pte_mkclean(pte_t pte) | |
459 | { | |
460 | unsigned long val = pte_val(pte), tmp; | |
461 | ||
462 | __asm__ __volatile__( | |
463 | "\n661: andn %0, %3, %0\n" | |
464 | " nop\n" | |
465 | "\n662: nop\n" | |
466 | " nop\n" | |
467 | " .section .sun4v_2insn_patch, \"ax\"\n" | |
468 | " .word 661b\n" | |
469 | " sethi %%uhi(%4), %1\n" | |
470 | " sllx %1, 32, %1\n" | |
471 | " .word 662b\n" | |
472 | " or %1, %%lo(%4), %1\n" | |
473 | " andn %0, %1, %0\n" | |
474 | " .previous\n" | |
475 | : "=r" (val), "=r" (tmp) | |
476 | : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U), | |
477 | "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V)); | |
478 | ||
479 | return __pte(val); | |
480 | } | |
481 | ||
482 | static inline pte_t pte_mkwrite(pte_t pte) | |
483 | { | |
484 | unsigned long val = pte_val(pte), mask; | |
485 | ||
486 | __asm__ __volatile__( | |
487 | "\n661: mov %1, %0\n" | |
488 | " nop\n" | |
489 | " .section .sun4v_2insn_patch, \"ax\"\n" | |
490 | " .word 661b\n" | |
491 | " sethi %%uhi(%2), %0\n" | |
492 | " sllx %0, 32, %0\n" | |
493 | " .previous\n" | |
494 | : "=r" (mask) | |
495 | : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V)); | |
496 | ||
497 | return __pte(val | mask); | |
498 | } | |
499 | ||
500 | static inline pte_t pte_wrprotect(pte_t pte) | |
501 | { | |
502 | unsigned long val = pte_val(pte), tmp; | |
503 | ||
504 | __asm__ __volatile__( | |
505 | "\n661: andn %0, %3, %0\n" | |
506 | " nop\n" | |
507 | "\n662: nop\n" | |
508 | " nop\n" | |
509 | " .section .sun4v_2insn_patch, \"ax\"\n" | |
510 | " .word 661b\n" | |
511 | " sethi %%uhi(%4), %1\n" | |
512 | " sllx %1, 32, %1\n" | |
513 | " .word 662b\n" | |
514 | " or %1, %%lo(%4), %1\n" | |
515 | " andn %0, %1, %0\n" | |
516 | " .previous\n" | |
517 | : "=r" (val), "=r" (tmp) | |
518 | : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U), | |
519 | "i" (_PAGE_WRITE_4V | _PAGE_W_4V)); | |
520 | ||
521 | return __pte(val); | |
522 | } | |
523 | ||
524 | static inline pte_t pte_mkold(pte_t pte) | |
525 | { | |
526 | unsigned long mask; | |
527 | ||
528 | __asm__ __volatile__( | |
529 | "\n661: mov %1, %0\n" | |
530 | " nop\n" | |
531 | " .section .sun4v_2insn_patch, \"ax\"\n" | |
532 | " .word 661b\n" | |
533 | " sethi %%uhi(%2), %0\n" | |
534 | " sllx %0, 32, %0\n" | |
535 | " .previous\n" | |
536 | : "=r" (mask) | |
537 | : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); | |
538 | ||
539 | mask |= _PAGE_R; | |
540 | ||
541 | return __pte(pte_val(pte) & ~mask); | |
542 | } | |
543 | ||
544 | static inline pte_t pte_mkyoung(pte_t pte) | |
545 | { | |
546 | unsigned long mask; | |
547 | ||
548 | __asm__ __volatile__( | |
549 | "\n661: mov %1, %0\n" | |
550 | " nop\n" | |
551 | " .section .sun4v_2insn_patch, \"ax\"\n" | |
552 | " .word 661b\n" | |
553 | " sethi %%uhi(%2), %0\n" | |
554 | " sllx %0, 32, %0\n" | |
555 | " .previous\n" | |
556 | : "=r" (mask) | |
557 | : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); | |
558 | ||
559 | mask |= _PAGE_R; | |
560 | ||
561 | return __pte(pte_val(pte) | mask); | |
562 | } | |
563 | ||
564 | static inline pte_t pte_mkspecial(pte_t pte) | |
565 | { | |
683d2fa6 | 566 | pte_val(pte) |= _PAGE_SPECIAL; |
f5e706ad SR |
567 | return pte; |
568 | } | |
569 | ||
570 | static inline unsigned long pte_young(pte_t pte) | |
571 | { | |
572 | unsigned long mask; | |
573 | ||
574 | __asm__ __volatile__( | |
575 | "\n661: mov %1, %0\n" | |
576 | " nop\n" | |
577 | " .section .sun4v_2insn_patch, \"ax\"\n" | |
578 | " .word 661b\n" | |
579 | " sethi %%uhi(%2), %0\n" | |
580 | " sllx %0, 32, %0\n" | |
581 | " .previous\n" | |
582 | : "=r" (mask) | |
583 | : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); | |
584 | ||
585 | return (pte_val(pte) & mask); | |
586 | } | |
587 | ||
588 | static inline unsigned long pte_dirty(pte_t pte) | |
589 | { | |
590 | unsigned long mask; | |
591 | ||
592 | __asm__ __volatile__( | |
593 | "\n661: mov %1, %0\n" | |
594 | " nop\n" | |
595 | " .section .sun4v_2insn_patch, \"ax\"\n" | |
596 | " .word 661b\n" | |
597 | " sethi %%uhi(%2), %0\n" | |
598 | " sllx %0, 32, %0\n" | |
599 | " .previous\n" | |
600 | : "=r" (mask) | |
601 | : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V)); | |
602 | ||
603 | return (pte_val(pte) & mask); | |
604 | } | |
605 | ||
606 | static inline unsigned long pte_write(pte_t pte) | |
607 | { | |
608 | unsigned long mask; | |
609 | ||
610 | __asm__ __volatile__( | |
611 | "\n661: mov %1, %0\n" | |
612 | " nop\n" | |
613 | " .section .sun4v_2insn_patch, \"ax\"\n" | |
614 | " .word 661b\n" | |
615 | " sethi %%uhi(%2), %0\n" | |
616 | " sllx %0, 32, %0\n" | |
617 | " .previous\n" | |
618 | : "=r" (mask) | |
619 | : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V)); | |
620 | ||
621 | return (pte_val(pte) & mask); | |
622 | } | |
623 | ||
624 | static inline unsigned long pte_exec(pte_t pte) | |
625 | { | |
626 | unsigned long mask; | |
627 | ||
628 | __asm__ __volatile__( | |
629 | "\n661: sethi %%hi(%1), %0\n" | |
630 | " .section .sun4v_1insn_patch, \"ax\"\n" | |
631 | " .word 661b\n" | |
632 | " mov %2, %0\n" | |
633 | " .previous\n" | |
634 | : "=r" (mask) | |
635 | : "i" (_PAGE_EXEC_4U), "i" (_PAGE_EXEC_4V)); | |
636 | ||
637 | return (pte_val(pte) & mask); | |
638 | } | |
639 | ||
f5e706ad SR |
640 | static inline unsigned long pte_present(pte_t pte) |
641 | { | |
642 | unsigned long val = pte_val(pte); | |
643 | ||
644 | __asm__ __volatile__( | |
645 | "\n661: and %0, %2, %0\n" | |
646 | " .section .sun4v_1insn_patch, \"ax\"\n" | |
647 | " .word 661b\n" | |
648 | " and %0, %3, %0\n" | |
649 | " .previous\n" | |
650 | : "=r" (val) | |
651 | : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V)); | |
652 | ||
653 | return val; | |
654 | } | |
655 | ||
4a9d1946 | 656 | #define pte_accessible pte_accessible |
20841405 | 657 | static inline unsigned long pte_accessible(struct mm_struct *mm, pte_t a) |
4a9d1946 DM |
658 | { |
659 | return pte_val(a) & _PAGE_VALID; | |
660 | } | |
661 | ||
683d2fa6 | 662 | static inline unsigned long pte_special(pte_t pte) |
f5e706ad | 663 | { |
683d2fa6 | 664 | return pte_val(pte) & _PAGE_SPECIAL; |
f5e706ad SR |
665 | } |
666 | ||
a7b9403f | 667 | static inline unsigned long pmd_large(pmd_t pmd) |
89a77915 | 668 | { |
a7b9403f DM |
669 | pte_t pte = __pte(pmd_val(pmd)); |
670 | ||
04df419d | 671 | return pte_val(pte) & _PAGE_PMD_HUGE; |
89a77915 DM |
672 | } |
673 | ||
0dd5b7b0 | 674 | static inline unsigned long pmd_pfn(pmd_t pmd) |
9e695d2e | 675 | { |
a7b9403f DM |
676 | pte_t pte = __pte(pmd_val(pmd)); |
677 | ||
0dd5b7b0 | 678 | return pte_pfn(pte); |
9e695d2e DM |
679 | } |
680 | ||
0dd5b7b0 | 681 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
c164e038 KS |
682 | static inline unsigned long pmd_dirty(pmd_t pmd) |
683 | { | |
684 | pte_t pte = __pte(pmd_val(pmd)); | |
685 | ||
686 | return pte_dirty(pte); | |
687 | } | |
688 | ||
0dd5b7b0 | 689 | static inline unsigned long pmd_young(pmd_t pmd) |
9e695d2e | 690 | { |
a7b9403f DM |
691 | pte_t pte = __pte(pmd_val(pmd)); |
692 | ||
0dd5b7b0 | 693 | return pte_young(pte); |
9e695d2e DM |
694 | } |
695 | ||
0dd5b7b0 | 696 | static inline unsigned long pmd_write(pmd_t pmd) |
9e695d2e | 697 | { |
a7b9403f | 698 | pte_t pte = __pte(pmd_val(pmd)); |
9e695d2e | 699 | |
0dd5b7b0 | 700 | return pte_write(pte); |
9e695d2e DM |
701 | } |
702 | ||
a7b9403f | 703 | static inline unsigned long pmd_trans_huge(pmd_t pmd) |
9e695d2e | 704 | { |
a7b9403f DM |
705 | pte_t pte = __pte(pmd_val(pmd)); |
706 | ||
707 | return pte_val(pte) & _PAGE_PMD_HUGE; | |
9e695d2e DM |
708 | } |
709 | ||
9e695d2e DM |
710 | static inline pmd_t pmd_mkold(pmd_t pmd) |
711 | { | |
a7b9403f DM |
712 | pte_t pte = __pte(pmd_val(pmd)); |
713 | ||
714 | pte = pte_mkold(pte); | |
715 | ||
716 | return __pmd(pte_val(pte)); | |
9e695d2e DM |
717 | } |
718 | ||
719 | static inline pmd_t pmd_wrprotect(pmd_t pmd) | |
720 | { | |
a7b9403f DM |
721 | pte_t pte = __pte(pmd_val(pmd)); |
722 | ||
723 | pte = pte_wrprotect(pte); | |
724 | ||
725 | return __pmd(pte_val(pte)); | |
9e695d2e DM |
726 | } |
727 | ||
728 | static inline pmd_t pmd_mkdirty(pmd_t pmd) | |
729 | { | |
a7b9403f DM |
730 | pte_t pte = __pte(pmd_val(pmd)); |
731 | ||
732 | pte = pte_mkdirty(pte); | |
733 | ||
734 | return __pmd(pte_val(pte)); | |
9e695d2e DM |
735 | } |
736 | ||
79cedb8f MK |
737 | static inline pmd_t pmd_mkclean(pmd_t pmd) |
738 | { | |
739 | pte_t pte = __pte(pmd_val(pmd)); | |
740 | ||
741 | pte = pte_mkclean(pte); | |
742 | ||
743 | return __pmd(pte_val(pte)); | |
744 | } | |
745 | ||
9e695d2e DM |
746 | static inline pmd_t pmd_mkyoung(pmd_t pmd) |
747 | { | |
a7b9403f DM |
748 | pte_t pte = __pte(pmd_val(pmd)); |
749 | ||
750 | pte = pte_mkyoung(pte); | |
751 | ||
752 | return __pmd(pte_val(pte)); | |
9e695d2e DM |
753 | } |
754 | ||
755 | static inline pmd_t pmd_mkwrite(pmd_t pmd) | |
756 | { | |
a7b9403f DM |
757 | pte_t pte = __pte(pmd_val(pmd)); |
758 | ||
759 | pte = pte_mkwrite(pte); | |
760 | ||
a7b9403f | 761 | return __pmd(pte_val(pte)); |
9e695d2e DM |
762 | } |
763 | ||
a7b9403f DM |
764 | static inline pgprot_t pmd_pgprot(pmd_t entry) |
765 | { | |
766 | unsigned long val = pmd_val(entry); | |
767 | ||
768 | return __pgprot(val); | |
769 | } | |
9e695d2e DM |
770 | #endif |
771 | ||
772 | static inline int pmd_present(pmd_t pmd) | |
773 | { | |
2b77933c | 774 | return pmd_val(pmd) != 0UL; |
9e695d2e DM |
775 | } |
776 | ||
777 | #define pmd_none(pmd) (!pmd_val(pmd)) | |
778 | ||
26cf4325 DM |
779 | /* pmd_bad() is only called on non-trans-huge PMDs. Our encoding is |
780 | * very simple, it's just the physical address. PTE tables are of | |
781 | * size PAGE_SIZE so make sure the sub-PAGE_SIZE bits are clear and | |
782 | * the top bits outside of the range of any physical address size we | |
783 | * support are clear as well. We also validate the physical itself. | |
784 | */ | |
0dd5b7b0 | 785 | #define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK) |
26cf4325 DM |
786 | |
787 | #define pud_none(pud) (!pud_val(pud)) | |
788 | ||
0dd5b7b0 | 789 | #define pud_bad(pud) (pud_val(pud) & ~PAGE_MASK) |
26cf4325 | 790 | |
ac55c768 DM |
791 | #define pgd_none(pgd) (!pgd_val(pgd)) |
792 | ||
0dd5b7b0 | 793 | #define pgd_bad(pgd) (pgd_val(pgd) & ~PAGE_MASK) |
ac55c768 | 794 | |
9e695d2e | 795 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
f05a6865 SR |
796 | void set_pmd_at(struct mm_struct *mm, unsigned long addr, |
797 | pmd_t *pmdp, pmd_t pmd); | |
9e695d2e DM |
798 | #else |
799 | static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, | |
800 | pmd_t *pmdp, pmd_t pmd) | |
801 | { | |
802 | *pmdp = pmd; | |
803 | } | |
804 | #endif | |
805 | ||
806 | static inline void pmd_set(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep) | |
807 | { | |
a7b9403f | 808 | unsigned long val = __pa((unsigned long) (ptep)); |
9e695d2e DM |
809 | |
810 | pmd_val(*pmdp) = val; | |
811 | } | |
812 | ||
f5e706ad | 813 | #define pud_set(pudp, pmdp) \ |
a7b9403f | 814 | (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)))) |
9e695d2e DM |
815 | static inline unsigned long __pmd_page(pmd_t pmd) |
816 | { | |
a7b9403f DM |
817 | pte_t pte = __pte(pmd_val(pmd)); |
818 | unsigned long pfn; | |
819 | ||
820 | pfn = pte_pfn(pte); | |
821 | ||
822 | return ((unsigned long) __va(pfn << PAGE_SHIFT)); | |
9e695d2e | 823 | } |
f5e706ad SR |
824 | #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd)) |
825 | #define pud_page_vaddr(pud) \ | |
a7b9403f | 826 | ((unsigned long) __va(pud_val(pud))) |
f5e706ad | 827 | #define pud_page(pud) virt_to_page((void *)pud_page_vaddr(pud)) |
2b77933c | 828 | #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL) |
f5e706ad | 829 | #define pud_present(pud) (pud_val(pud) != 0U) |
2b77933c | 830 | #define pud_clear(pudp) (pud_val(*(pudp)) = 0UL) |
ac55c768 DM |
831 | #define pgd_page_vaddr(pgd) \ |
832 | ((unsigned long) __va(pgd_val(pgd))) | |
833 | #define pgd_present(pgd) (pgd_val(pgd) != 0U) | |
acff7fdb | 834 | #define pgd_clear(pgdp) (pgd_val(*(pgdp)) = 0UL) |
f5e706ad | 835 | |
0dd5b7b0 DM |
836 | static inline unsigned long pud_large(pud_t pud) |
837 | { | |
838 | pte_t pte = __pte(pud_val(pud)); | |
839 | ||
840 | return pte_val(pte) & _PAGE_PMD_HUGE; | |
841 | } | |
842 | ||
843 | static inline unsigned long pud_pfn(pud_t pud) | |
844 | { | |
845 | pte_t pte = __pte(pud_val(pud)); | |
846 | ||
847 | return pte_pfn(pte); | |
848 | } | |
849 | ||
f5e706ad SR |
850 | /* Same in both SUN4V and SUN4U. */ |
851 | #define pte_none(pte) (!pte_val(pte)) | |
852 | ||
ac55c768 DM |
853 | #define pgd_set(pgdp, pudp) \ |
854 | (pgd_val(*(pgdp)) = (__pa((unsigned long) (pudp)))) | |
855 | ||
f5e706ad SR |
856 | /* to find an entry in a page-table-directory. */ |
857 | #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) | |
858 | #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) | |
859 | ||
860 | /* to find an entry in a kernel page-table-directory */ | |
861 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | |
862 | ||
ac55c768 DM |
863 | /* Find an entry in the third-level page table.. */ |
864 | #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) | |
865 | #define pud_offset(pgdp, address) \ | |
866 | ((pud_t *) pgd_page_vaddr(*(pgdp)) + pud_index(address)) | |
867 | ||
f5e706ad SR |
868 | /* Find an entry in the second-level page table.. */ |
869 | #define pmd_offset(pudp, address) \ | |
870 | ((pmd_t *) pud_page_vaddr(*(pudp)) + \ | |
871 | (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))) | |
872 | ||
873 | /* Find an entry in the third-level page table.. */ | |
874 | #define pte_index(dir, address) \ | |
875 | ((pte_t *) __pmd_page(*(dir)) + \ | |
876 | ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))) | |
877 | #define pte_offset_kernel pte_index | |
878 | #define pte_offset_map pte_index | |
f5e706ad | 879 | #define pte_unmap(pte) do { } while (0) |
f5e706ad | 880 | |
589ee628 IM |
881 | /* We cannot include <linux/mm_types.h> at this point yet: */ |
882 | extern struct mm_struct init_mm; | |
883 | ||
f5e706ad | 884 | /* Actual page table PTE updates. */ |
f05a6865 | 885 | void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, |
c7d9f77d NG |
886 | pte_t *ptep, pte_t orig, int fullmm, |
887 | unsigned int hugepage_shift); | |
f5e706ad | 888 | |
24e49ee3 | 889 | static void maybe_tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, |
c7d9f77d NG |
890 | pte_t *ptep, pte_t orig, int fullmm, |
891 | unsigned int hugepage_shift) | |
24e49ee3 NG |
892 | { |
893 | /* It is more efficient to let flush_tlb_kernel_range() | |
894 | * handle init_mm tlb flushes. | |
895 | * | |
896 | * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U | |
897 | * and SUN4V pte layout, so this inline test is fine. | |
898 | */ | |
899 | if (likely(mm != &init_mm) && pte_accessible(mm, orig)) | |
c7d9f77d | 900 | tlb_batch_add(mm, vaddr, ptep, orig, fullmm, hugepage_shift); |
24e49ee3 NG |
901 | } |
902 | ||
8809aa2d AK |
903 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR |
904 | static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, | |
905 | unsigned long addr, | |
906 | pmd_t *pmdp) | |
9e695d2e DM |
907 | { |
908 | pmd_t pmd = *pmdp; | |
2b77933c | 909 | set_pmd_at(mm, addr, pmdp, __pmd(0UL)); |
9e695d2e DM |
910 | return pmd; |
911 | } | |
912 | ||
90f08e39 PZ |
913 | static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, |
914 | pte_t *ptep, pte_t pte, int fullmm) | |
f5e706ad SR |
915 | { |
916 | pte_t orig = *ptep; | |
917 | ||
918 | *ptep = pte; | |
c7d9f77d | 919 | maybe_tlb_batch_add(mm, addr, ptep, orig, fullmm, PAGE_SHIFT); |
f5e706ad SR |
920 | } |
921 | ||
90f08e39 PZ |
922 | #define set_pte_at(mm,addr,ptep,pte) \ |
923 | __set_pte_at((mm), (addr), (ptep), (pte), 0) | |
924 | ||
f5e706ad SR |
925 | #define pte_clear(mm,addr,ptep) \ |
926 | set_pte_at((mm), (addr), (ptep), __pte(0UL)) | |
927 | ||
90f08e39 PZ |
928 | #define __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL |
929 | #define pte_clear_not_present_full(mm,addr,ptep,fullmm) \ | |
930 | __set_pte_at((mm), (addr), (ptep), __pte(0UL), (fullmm)) | |
931 | ||
f5e706ad SR |
932 | #ifdef DCACHE_ALIASING_POSSIBLE |
933 | #define __HAVE_ARCH_MOVE_PTE | |
934 | #define move_pte(pte, prot, old_addr, new_addr) \ | |
935 | ({ \ | |
936 | pte_t newpte = (pte); \ | |
937 | if (tlb_type != hypervisor && pte_present(pte)) { \ | |
938 | unsigned long this_pfn = pte_pfn(pte); \ | |
939 | \ | |
940 | if (pfn_valid(this_pfn) && \ | |
941 | (((old_addr) ^ (new_addr)) & (1 << 13))) \ | |
942 | flush_dcache_page_all(current->mm, \ | |
943 | pfn_to_page(this_pfn)); \ | |
944 | } \ | |
945 | newpte; \ | |
946 | }) | |
947 | #endif | |
948 | ||
2b77933c | 949 | extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; |
f5e706ad | 950 | |
f05a6865 SR |
951 | void paging_init(void); |
952 | unsigned long find_ecache_flush_span(unsigned long size); | |
f5e706ad | 953 | |
cb1b8209 | 954 | struct seq_file; |
f05a6865 | 955 | void mmu_info(struct seq_file *); |
cb1b8209 | 956 | |
f5e706ad | 957 | struct vm_area_struct; |
f05a6865 | 958 | void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *); |
9e695d2e | 959 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
f05a6865 SR |
960 | void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, |
961 | pmd_t *pmd); | |
9e695d2e | 962 | |
51e5ef1b DM |
963 | #define __HAVE_ARCH_PMDP_INVALIDATE |
964 | extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, | |
965 | pmd_t *pmdp); | |
966 | ||
9e695d2e | 967 | #define __HAVE_ARCH_PGTABLE_DEPOSIT |
f05a6865 SR |
968 | void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, |
969 | pgtable_t pgtable); | |
9e695d2e DM |
970 | |
971 | #define __HAVE_ARCH_PGTABLE_WITHDRAW | |
f05a6865 | 972 | pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); |
9e695d2e | 973 | #endif |
f5e706ad SR |
974 | |
975 | /* Encode and de-code a swap entry */ | |
976 | #define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL) | |
977 | #define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL)) | |
978 | #define __swp_entry(type, offset) \ | |
979 | ( (swp_entry_t) \ | |
980 | { \ | |
981 | (((long)(type) << PAGE_SHIFT) | \ | |
982 | ((long)(offset) << (PAGE_SHIFT + 8UL))) \ | |
983 | } ) | |
984 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | |
985 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) | |
986 | ||
f05a6865 | 987 | int page_in_phys_avail(unsigned long paddr); |
f5e706ad | 988 | |
f5e706ad SR |
989 | /* |
990 | * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in | |
991 | * its high 4 bits. These macros/functions put it there or get it from there. | |
992 | */ | |
993 | #define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4))) | |
994 | #define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4)) | |
995 | #define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL) | |
996 | ||
f05a6865 SR |
997 | int remap_pfn_range(struct vm_area_struct *, unsigned long, unsigned long, |
998 | unsigned long, pgprot_t); | |
3e37fd31 DM |
999 | |
1000 | static inline int io_remap_pfn_range(struct vm_area_struct *vma, | |
1001 | unsigned long from, unsigned long pfn, | |
1002 | unsigned long size, pgprot_t prot) | |
1003 | { | |
1004 | unsigned long offset = GET_PFN(pfn) << PAGE_SHIFT; | |
1005 | int space = GET_IOSPACE(pfn); | |
1006 | unsigned long phys_base; | |
1007 | ||
1008 | phys_base = offset | (((unsigned long) space) << 32UL); | |
1009 | ||
1010 | return remap_pfn_range(vma, from, phys_base >> PAGE_SHIFT, size, prot); | |
1011 | } | |
40d158e6 | 1012 | #define io_remap_pfn_range io_remap_pfn_range |
3e37fd31 | 1013 | |
f36391d2 | 1014 | #include <asm/tlbflush.h> |
f5e706ad SR |
1015 | #include <asm-generic/pgtable.h> |
1016 | ||
1017 | /* We provide our own get_unmapped_area to cope with VA holes and | |
1018 | * SHM area cache aliasing for userland. | |
1019 | */ | |
1020 | #define HAVE_ARCH_UNMAPPED_AREA | |
1021 | #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN | |
1022 | ||
1023 | /* We provide a special get_unmapped_area for framebuffer mmaps to try and use | |
1024 | * the largest alignment possible such that larget PTEs can be used. | |
1025 | */ | |
f05a6865 SR |
1026 | unsigned long get_fb_unmapped_area(struct file *filp, unsigned long, |
1027 | unsigned long, unsigned long, | |
1028 | unsigned long); | |
f5e706ad SR |
1029 | #define HAVE_ARCH_FB_UNMAPPED_AREA |
1030 | ||
f05a6865 SR |
1031 | void pgtable_cache_init(void); |
1032 | void sun4v_register_fault_status(void); | |
1033 | void sun4v_ktsb_register(void); | |
1034 | void __init cheetah_ecache_flush_init(void); | |
1035 | void sun4v_patch_tlb_handlers(void); | |
f5e706ad SR |
1036 | |
1037 | extern unsigned long cmdline_memory_size; | |
1038 | ||
f05a6865 | 1039 | asmlinkage void do_sparc64_fault(struct pt_regs *regs); |
b539c467 | 1040 | |
f5e706ad SR |
1041 | #endif /* !(__ASSEMBLY__) */ |
1042 | ||
1043 | #endif /* !(_SPARC64_PGTABLE_H) */ |