[linux-block.git] / arch / sparc / include / asm / pgtable_32.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _SPARC_PGTABLE_H
#define _SPARC_PGTABLE_H

/*  asm/pgtable.h:  Defines and functions used to work
 *                        with Sparc page tables.
 *
 *  Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
 *  Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 */

#include <linux/const.h>

#ifndef __ASSEMBLY__
#include <asm-generic/4level-fixup.h>

#include <linux/spinlock.h>
#include <linux/mm_types.h>
#include <asm/types.h>
#include <asm/pgtsrmmu.h>
#include <asm/vaddrs.h>
#include <asm/oplib.h>
#include <asm/cpu_type.h>


struct vm_area_struct;
struct page;

void load_mmu(void);
unsigned long calc_highpages(void);
unsigned long __init bootmem_init(unsigned long *pages_avail);

#define pte_ERROR(e)   __builtin_trap()
#define pmd_ERROR(e)   __builtin_trap()
#define pgd_ERROR(e)   __builtin_trap()

#define PMD_SHIFT		22
#define PMD_SIZE        	(1UL << PMD_SHIFT)
#define PMD_MASK        	(~(PMD_SIZE-1))
#define PMD_ALIGN(__addr) 	(((__addr) + ~PMD_MASK) & PMD_MASK)
#define PGDIR_SHIFT     	SRMMU_PGDIR_SHIFT
#define PGDIR_SIZE      	SRMMU_PGDIR_SIZE
#define PGDIR_MASK      	SRMMU_PGDIR_MASK
#define PTRS_PER_PTE    	1024
#define PTRS_PER_PMD    	SRMMU_PTRS_PER_PMD
#define PTRS_PER_PGD    	SRMMU_PTRS_PER_PGD
#define USER_PTRS_PER_PGD	PAGE_OFFSET / SRMMU_PGDIR_SIZE
#define FIRST_USER_ADDRESS	0UL
#define PTE_SIZE		(PTRS_PER_PTE*4)

#define PAGE_NONE	SRMMU_PAGE_NONE
#define PAGE_SHARED	SRMMU_PAGE_SHARED
#define PAGE_COPY	SRMMU_PAGE_COPY
#define PAGE_READONLY	SRMMU_PAGE_RDONLY
#define PAGE_KERNEL	SRMMU_PAGE_KERNEL

/* Top-level page directory - dummy used by init-mm.
 * srmmu.c will assign the real one (which is dynamically sized) */
#define swapper_pg_dir NULL

void paging_init(void);

extern unsigned long ptr_in_current_pgd;

/*         xwr */
#define __P000  PAGE_NONE
#define __P001  PAGE_READONLY
#define __P010  PAGE_COPY
#define __P011  PAGE_COPY
#define __P100  PAGE_READONLY
#define __P101  PAGE_READONLY
#define __P110  PAGE_COPY
#define __P111  PAGE_COPY

#define __S000	PAGE_NONE
#define __S001	PAGE_READONLY
#define __S010	PAGE_SHARED
#define __S011	PAGE_SHARED
#define __S100	PAGE_READONLY
#define __S101	PAGE_READONLY
#define __S110	PAGE_SHARED
#define __S111	PAGE_SHARED

/* First physical page can be anywhere, the following is needed so that
 * va-->pa and vice versa conversions work properly without performance
 * hit for all __pa()/__va() operations.
 */
extern unsigned long phys_base;
extern unsigned long pfn_base;

/*
 * ZERO_PAGE is a global shared page that is always zero: used
 * for zero-mapped memory areas etc..
 */
extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];

#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))

/*
 * In general all page table modifications should use the V8 atomic
 * swap instruction.  This insures the mmu and the cpu are in sync
 * with respect to ref/mod bits in the page tables.
 */
static inline unsigned long srmmu_swap(unsigned long *addr, unsigned long value)
{
	__asm__ __volatile__("swap [%2], %0" :
			"=&r" (value) : "0" (value), "r" (addr) : "memory");
	return value;
}

/* Certain architectures need to do special things when pte's
 * within a page table are directly modified.  Thus, the following
 * hook is made available.
 */

static inline void set_pte(pte_t *ptep, pte_t pteval)
{
	srmmu_swap((unsigned long *)ptep, pte_val(pteval));
}

#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)

static inline int srmmu_device_memory(unsigned long x)
{
	return ((x & 0xF0000000) != 0);
}

static inline struct page *pmd_page(pmd_t pmd)
{
	if (srmmu_device_memory(pmd_val(pmd)))
		BUG();
	return pfn_to_page((pmd_val(pmd) & SRMMU_PTD_PMASK) >> (PAGE_SHIFT-4));
}

static inline unsigned long pgd_page_vaddr(pgd_t pgd)
{
	if (srmmu_device_memory(pgd_val(pgd))) {
		return ~0;
	} else {
		unsigned long v = pgd_val(pgd) & SRMMU_PTD_PMASK;
		return (unsigned long)__nocache_va(v << 4);
	}
}

static inline int pte_present(pte_t pte)
{
	return ((pte_val(pte) & SRMMU_ET_MASK) == SRMMU_ET_PTE);
}

static inline int pte_none(pte_t pte)
{
	return !pte_val(pte);
}

static inline void __pte_clear(pte_t *ptep)
{
	set_pte(ptep, __pte(0));
}

static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
{
	__pte_clear(ptep);
}

static inline int pmd_bad(pmd_t pmd)
{
	return (pmd_val(pmd) & SRMMU_ET_MASK) != SRMMU_ET_PTD;
}

static inline int pmd_present(pmd_t pmd)
{
	return ((pmd_val(pmd) & SRMMU_ET_MASK) == SRMMU_ET_PTD);
}

static inline int pmd_none(pmd_t pmd)
{
	return !pmd_val(pmd);
}

static inline void pmd_clear(pmd_t *pmdp)
{
	int i;
	for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++)
		set_pte((pte_t *)&pmdp->pmdv[i], __pte(0));
}

static inline int pgd_none(pgd_t pgd)          
{
	return !(pgd_val(pgd) & 0xFFFFFFF);
}

static inline int pgd_bad(pgd_t pgd)
{
	return (pgd_val(pgd) & SRMMU_ET_MASK) != SRMMU_ET_PTD;
}

static inline int pgd_present(pgd_t pgd)
{
	return ((pgd_val(pgd) & SRMMU_ET_MASK) == SRMMU_ET_PTD);
}

static inline void pgd_clear(pgd_t *pgdp)
{
	set_pte((pte_t *)pgdp, __pte(0));
}

/*
 * The following only work if pte_present() is true.
 * Undefined behaviour if not..
 */
static inline int pte_write(pte_t pte)
{
	return pte_val(pte) & SRMMU_WRITE;
}

static inline int pte_dirty(pte_t pte)
{
	return pte_val(pte) & SRMMU_DIRTY;
}

static inline int pte_young(pte_t pte)
{
	return pte_val(pte) & SRMMU_REF;
}

static inline int pte_special(pte_t pte)
{
	return 0;
}

static inline pte_t pte_wrprotect(pte_t pte)
{
	return __pte(pte_val(pte) & ~SRMMU_WRITE);
}

static inline pte_t pte_mkclean(pte_t pte)
{
	return __pte(pte_val(pte) & ~SRMMU_DIRTY);
}

static inline pte_t pte_mkold(pte_t pte)
{
	return __pte(pte_val(pte) & ~SRMMU_REF);
}

static inline pte_t pte_mkwrite(pte_t pte)
{
	return __pte(pte_val(pte) | SRMMU_WRITE);
}

static inline pte_t pte_mkdirty(pte_t pte)
{
	return __pte(pte_val(pte) | SRMMU_DIRTY);
}

static inline pte_t pte_mkyoung(pte_t pte)
{
	return __pte(pte_val(pte) | SRMMU_REF);
}

#define pte_mkspecial(pte)    (pte)

#define pfn_pte(pfn, prot)		mk_pte(pfn_to_page(pfn), prot)

static inline unsigned long pte_pfn(pte_t pte)
{
	if (srmmu_device_memory(pte_val(pte))) {
		/* Just return something that will cause
		 * pfn_valid() to return false.  This makes
		 * copy_one_pte() to just directly copy to
		 * PTE over.
		 */
		return ~0UL;
	}
	return (pte_val(pte) & SRMMU_PTE_PMASK) >> (PAGE_SHIFT-4);
}

#define pte_page(pte)	pfn_to_page(pte_pfn(pte))

/*
 * Conversion functions: convert a page and protection to a page entry,
 * and a page entry and page directory to the page they refer to.
 */
static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
{
	return __pte((page_to_pfn(page) << (PAGE_SHIFT-4)) | pgprot_val(pgprot));
}

static inline pte_t mk_pte_phys(unsigned long page, pgprot_t pgprot)
{
	return __pte(((page) >> 4) | pgprot_val(pgprot));
}

static inline pte_t mk_pte_io(unsigned long page, pgprot_t pgprot, int space)
{
	return __pte(((page) >> 4) | (space << 28) | pgprot_val(pgprot));
}

#define pgprot_noncached pgprot_noncached
static inline pgprot_t pgprot_noncached(pgprot_t prot)
{
	pgprot_val(prot) &= ~pgprot_val(__pgprot(SRMMU_CACHE));
	return prot;
}

static pte_t pte_modify(pte_t pte, pgprot_t newprot) __attribute_const__;
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{
	return __pte((pte_val(pte) & SRMMU_CHG_MASK) |
		pgprot_val(newprot));
}

#define pgd_index(address) ((address) >> PGDIR_SHIFT)

/* to find an entry in a page-table-directory */
#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))

/* to find an entry in a kernel page-table-directory */
#define pgd_offset_k(address) pgd_offset(&init_mm, address)

/* Find an entry in the second-level page table.. */
static inline pmd_t *pmd_offset(pgd_t * dir, unsigned long address)
{
	return (pmd_t *) pgd_page_vaddr(*dir) +
		((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1));
}

/* Find an entry in the third-level page table.. */
pte_t *pte_offset_kernel(pmd_t * dir, unsigned long address);

/*
 * This shortcut works on sun4m (and sun4d) because the nocache area is static.
 */
#define pte_offset_map(d, a)		pte_offset_kernel(d,a)
#define pte_unmap(pte)		do{}while(0)

struct seq_file;
void mmu_info(struct seq_file *m);

/* Fault handler stuff... */
#define FAULT_CODE_PROT     0x1
#define FAULT_CODE_WRITE    0x2
#define FAULT_CODE_USER     0x4

#define update_mmu_cache(vma, address, ptep) do { } while (0)

void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
                      unsigned long xva, unsigned int len);
void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len);

/* Encode and de-code a swap entry */
static inline unsigned long __swp_type(swp_entry_t entry)
{
	return (entry.val >> SRMMU_SWP_TYPE_SHIFT) & SRMMU_SWP_TYPE_MASK;
}

static inline unsigned long __swp_offset(swp_entry_t entry)
{
	return (entry.val >> SRMMU_SWP_OFF_SHIFT) & SRMMU_SWP_OFF_MASK;
}

static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset)
{
	return (swp_entry_t) {
		(type & SRMMU_SWP_TYPE_MASK) << SRMMU_SWP_TYPE_SHIFT
		| (offset & SRMMU_SWP_OFF_MASK) << SRMMU_SWP_OFF_SHIFT };
}

#define __pte_to_swp_entry(pte)		((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x)		((pte_t) { (x).val })

static inline unsigned long
__get_phys (unsigned long addr)
{
	switch (sparc_cpu_model){
	case sun4m:
	case sun4d:
		return ((srmmu_get_pte (addr) & 0xffffff00) << 4);
	default:
		return 0;
	}
}

static inline int
__get_iospace (unsigned long addr)
{
	switch (sparc_cpu_model){
	case sun4m:
	case sun4d:
		return (srmmu_get_pte (addr) >> 28);
	default:
		return -1;
	}
}

extern unsigned long *sparc_valid_addr_bitmap;

/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
#define kern_addr_valid(addr) \
	(test_bit(__pa((unsigned long)(addr))>>20, sparc_valid_addr_bitmap))

/*
 * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
 * its high 4 bits.  These macros/functions put it there or get it from there.
 */
#define MK_IOSPACE_PFN(space, pfn)	(pfn | (space << (BITS_PER_LONG - 4)))
#define GET_IOSPACE(pfn)		(pfn >> (BITS_PER_LONG - 4))
#define GET_PFN(pfn)			(pfn & 0x0fffffffUL)

int remap_pfn_range(struct vm_area_struct *, unsigned long, unsigned long,
		    unsigned long, pgprot_t);

static inline int io_remap_pfn_range(struct vm_area_struct *vma,
				     unsigned long from, unsigned long pfn,
				     unsigned long size, pgprot_t prot)
{
	unsigned long long offset, space, phys_base;

	offset = ((unsigned long long) GET_PFN(pfn)) << PAGE_SHIFT;
	space = GET_IOSPACE(pfn);
	phys_base = offset | (space << 32ULL);

	return remap_pfn_range(vma, from, phys_base >> PAGE_SHIFT, size, prot);
}
#define io_remap_pfn_range io_remap_pfn_range 

#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
({									  \
	int __changed = !pte_same(*(__ptep), __entry);			  \
	if (__changed) {						  \
		set_pte_at((__vma)->vm_mm, (__address), __ptep, __entry); \
		flush_tlb_page(__vma, __address);			  \
	}								  \
	__changed;							  \
})

#include <asm-generic/pgtable.h>

#endif /* !(__ASSEMBLY__) */

#define VMALLOC_START           _AC(0xfe600000,UL)
#define VMALLOC_END             _AC(0xffc00000,UL)

/* We provide our own get_unmapped_area to cope with VA holes for userland */
#define HAVE_ARCH_UNMAPPED_AREA

/*
 * No page table caches to initialise
 */
#define pgtable_cache_init()	do { } while (0)

#endif /* !(_SPARC_PGTABLE_H) */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
f5e706ad SR	2	#ifndef _SPARC_PGTABLE_H
	3	#define _SPARC_PGTABLE_H
	4
a439fe51	5	/* asm/pgtable.h: Defines and functions used to work
f5e706ad SR	6	* with Sparc page tables.
	7	*
	8	* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
	9	* Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
	10	*/
	11
eb485d64 SR	12	#include <linux/const.h>
eb485d64 SR	13
f5e706ad SR	14	#ifndef __ASSEMBLY__
	15	#include <asm-generic/4level-fixup.h>
	16
	17	#include <linux/spinlock.h>
b3d9ed3f	18	#include <linux/mm_types.h>
f5e706ad	19	#include <asm/types.h>
f5e706ad	20	#include <asm/pgtsrmmu.h>
9701b264	21	#include <asm/vaddrs.h>
f5e706ad	22	#include <asm/oplib.h>
d550bbd4	23	#include <asm/cpu_type.h>
f5e706ad SR	24
	25
	26	struct vm_area_struct;
	27	struct page;
	28
f05a6865 SR	29	void load_mmu(void);
f05a6865 SR	30	unsigned long calc_highpages(void);
4c9660f7	31	unsigned long __init bootmem_init(unsigned long *pages_avail);
f5e706ad	32
f5e706ad SR	33	#define pte_ERROR(e) __builtin_trap()
	34	#define pmd_ERROR(e) __builtin_trap()
	35	#define pgd_ERROR(e) __builtin_trap()
	36
1ee0e144	37	#define PMD_SHIFT 22
f5e706ad SR	38	#define PMD_SIZE (1UL << PMD_SHIFT)
	39	#define PMD_MASK (~(PMD_SIZE-1))
	40	#define PMD_ALIGN(__addr) (((__addr) + ~PMD_MASK) & PMD_MASK)
3d386c0e DM	41	#define PGDIR_SHIFT SRMMU_PGDIR_SHIFT
	42	#define PGDIR_SIZE SRMMU_PGDIR_SIZE
	43	#define PGDIR_MASK SRMMU_PGDIR_MASK
f5e706ad	44	#define PTRS_PER_PTE 1024
3d386c0e DM	45	#define PTRS_PER_PMD SRMMU_PTRS_PER_PMD
	46	#define PTRS_PER_PGD SRMMU_PTRS_PER_PGD
	47	#define USER_PTRS_PER_PGD PAGE_OFFSET / SRMMU_PGDIR_SIZE
d016bf7e	48	#define FIRST_USER_ADDRESS 0UL
f5e706ad SR	49	#define PTE_SIZE (PTRS_PER_PTE*4)
f5e706ad SR	50
6439d1c6 DM	51	#define PAGE_NONE SRMMU_PAGE_NONE
	52	#define PAGE_SHARED SRMMU_PAGE_SHARED
	53	#define PAGE_COPY SRMMU_PAGE_COPY
	54	#define PAGE_READONLY SRMMU_PAGE_RDONLY
	55	#define PAGE_KERNEL SRMMU_PAGE_KERNEL
f5e706ad	56
881e02d2 SR	57	/* Top-level page directory - dummy used by init-mm.
	58	* srmmu.c will assign the real one (which is dynamically sized) */
	59	#define swapper_pg_dir NULL
f5e706ad	60
f05a6865	61	void paging_init(void);
f5e706ad	62
f5e706ad SR	63	extern unsigned long ptr_in_current_pgd;
f5e706ad SR	64
6439d1c6 DM	65	/* xwr */
	66	#define __P000 PAGE_NONE
	67	#define __P001 PAGE_READONLY
	68	#define __P010 PAGE_COPY
	69	#define __P011 PAGE_COPY
	70	#define __P100 PAGE_READONLY
	71	#define __P101 PAGE_READONLY
	72	#define __P110 PAGE_COPY
	73	#define __P111 PAGE_COPY
	74
	75	#define __S000 PAGE_NONE
	76	#define __S001 PAGE_READONLY
	77	#define __S010 PAGE_SHARED
	78	#define __S011 PAGE_SHARED
	79	#define __S100 PAGE_READONLY
	80	#define __S101 PAGE_READONLY
	81	#define __S110 PAGE_SHARED
	82	#define __S111 PAGE_SHARED
f5e706ad	83
f5e706ad SR	84	/* First physical page can be anywhere, the following is needed so that
	85	* va-->pa and vice versa conversions work properly without performance
	86	* hit for all __pa()/__va() operations.
	87	*/
	88	extern unsigned long phys_base;
	89	extern unsigned long pfn_base;
	90
	91	/*
f5e706ad SR	92	* ZERO_PAGE is a global shared page that is always zero: used
	93	* for zero-mapped memory areas etc..
	94	*/
deba804c	95	extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
f5e706ad	96
deba804c	97	#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
f5e706ad	98
a46d6056 DM	99	/*
	100	* In general all page table modifications should use the V8 atomic
	101	* swap instruction. This insures the mmu and the cpu are in sync
	102	* with respect to ref/mod bits in the page tables.
	103	*/
	104	static inline unsigned long srmmu_swap(unsigned long *addr, unsigned long value)
	105	{
4ecf8860 KS	106	__asm__ __volatile__("swap [%2], %0" :
4ecf8860 KS	107	"=&r" (value) : "0" (value), "r" (addr) : "memory");
a46d6056 DM	108	return value;
	109	}
	110
62875cff DM	111	/* Certain architectures need to do special things when pte's
	112	* within a page table are directly modified. Thus, the following
	113	* hook is made available.
	114	*/
	115
	116	static inline void set_pte(pte_t *ptep, pte_t pteval)
a46d6056 DM	117	{
	118	srmmu_swap((unsigned long *)ptep, pte_val(pteval));
	119	}
	120
62875cff DM	121	#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
62875cff DM	122
3d827367 DM	123	static inline int srmmu_device_memory(unsigned long x)
	124	{
	125	return ((x & 0xF0000000) != 0);
	126	}
	127
	128	static inline struct page *pmd_page(pmd_t pmd)
	129	{
	130	if (srmmu_device_memory(pmd_val(pmd)))
	131	BUG();
	132	return pfn_to_page((pmd_val(pmd) & SRMMU_PTD_PMASK) >> (PAGE_SHIFT-4));
	133	}
	134
9701b264 SR	135	static inline unsigned long pgd_page_vaddr(pgd_t pgd)
	136	{
	137	if (srmmu_device_memory(pgd_val(pgd))) {
	138	return ~0;
	139	} else {
	140	unsigned long v = pgd_val(pgd) & SRMMU_PTD_PMASK;
	141	return (unsigned long)__nocache_va(v << 4);
	142	}
	143	}
f5e706ad	144
62875cff DM	145	static inline int pte_present(pte_t pte)
	146	{
	147	return ((pte_val(pte) & SRMMU_ET_MASK) == SRMMU_ET_PTE);
	148	}
f5e706ad SR	149
	150	static inline int pte_none(pte_t pte)
	151	{
c87fe1c0	152	return !pte_val(pte);
f5e706ad SR	153	}
f5e706ad SR	154
a46d6056 DM	155	static inline void __pte_clear(pte_t *ptep)
a46d6056 DM	156	{
62875cff	157	set_pte(ptep, __pte(0));
a46d6056 DM	158	}
	159
	160	static inline void pte_clear(struct mm_struct mm, unsigned long addr, pte_t ptep)
	161	{
	162	__pte_clear(ptep);
	163	}
f5e706ad	164
f167edae DM	165	static inline int pmd_bad(pmd_t pmd)
	166	{
	167	return (pmd_val(pmd) & SRMMU_ET_MASK) != SRMMU_ET_PTD;
	168	}
	169
	170	static inline int pmd_present(pmd_t pmd)
	171	{
	172	return ((pmd_val(pmd) & SRMMU_ET_MASK) == SRMMU_ET_PTD);
	173	}
f5e706ad SR	174
	175	static inline int pmd_none(pmd_t pmd)
	176	{
c87fe1c0	177	return !pmd_val(pmd);
f5e706ad SR	178	}
f5e706ad SR	179
a46d6056 DM	180	static inline void pmd_clear(pmd_t *pmdp)
	181	{
	182	int i;
	183	for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++)
62875cff	184	set_pte((pte_t *)&pmdp->pmdv[i], __pte(0));
a46d6056	185	}
f5e706ad	186
7d9fa4aa DM	187	static inline int pgd_none(pgd_t pgd)
	188	{
	189	return !(pgd_val(pgd) & 0xFFFFFFF);
	190	}
f5e706ad	191
7d9fa4aa DM	192	static inline int pgd_bad(pgd_t pgd)
	193	{
	194	return (pgd_val(pgd) & SRMMU_ET_MASK) != SRMMU_ET_PTD;
	195	}
	196
	197	static inline int pgd_present(pgd_t pgd)
	198	{
	199	return ((pgd_val(pgd) & SRMMU_ET_MASK) == SRMMU_ET_PTD);
	200	}
a46d6056 DM	201
	202	static inline void pgd_clear(pgd_t *pgdp)
	203	{
62875cff	204	set_pte((pte_t *)pgdp, __pte(0));
a46d6056	205	}
f5e706ad SR	206
	207	/*
	208	* The following only work if pte_present() is true.
	209	* Undefined behaviour if not..
	210	*/
f5e706ad SR	211	static inline int pte_write(pte_t pte)
f5e706ad SR	212	{
f755f77a	213	return pte_val(pte) & SRMMU_WRITE;
f5e706ad SR	214	}
f5e706ad SR	215
f5e706ad SR	216	static inline int pte_dirty(pte_t pte)
f5e706ad SR	217	{
f755f77a	218	return pte_val(pte) & SRMMU_DIRTY;
f5e706ad SR	219	}
f5e706ad SR	220
f5e706ad SR	221	static inline int pte_young(pte_t pte)
f5e706ad SR	222	{
f755f77a	223	return pte_val(pte) & SRMMU_REF;
f5e706ad SR	224	}
f5e706ad SR	225
f5e706ad SR	226	static inline int pte_special(pte_t pte)
	227	{
	228	return 0;
	229	}
	230
f5e706ad SR	231	static inline pte_t pte_wrprotect(pte_t pte)
f5e706ad SR	232	{
301d5bbb	233	return __pte(pte_val(pte) & ~SRMMU_WRITE);
f5e706ad SR	234	}
f5e706ad SR	235
f5e706ad SR	236	static inline pte_t pte_mkclean(pte_t pte)
f5e706ad SR	237	{
301d5bbb	238	return __pte(pte_val(pte) & ~SRMMU_DIRTY);
f5e706ad SR	239	}
f5e706ad SR	240
f5e706ad SR	241	static inline pte_t pte_mkold(pte_t pte)
f5e706ad SR	242	{
301d5bbb	243	return __pte(pte_val(pte) & ~SRMMU_REF);
f5e706ad SR	244	}
f5e706ad SR	245
301d5bbb DM	246	static inline pte_t pte_mkwrite(pte_t pte)
	247	{
	248	return __pte(pte_val(pte) \| SRMMU_WRITE);
	249	}
f5e706ad	250
301d5bbb DM	251	static inline pte_t pte_mkdirty(pte_t pte)
	252	{
	253	return __pte(pte_val(pte) \| SRMMU_DIRTY);
	254	}
	255
	256	static inline pte_t pte_mkyoung(pte_t pte)
	257	{
	258	return __pte(pte_val(pte) \| SRMMU_REF);
	259	}
f5e706ad SR	260
	261	#define pte_mkspecial(pte) (pte)
	262
	263	#define pfn_pte(pfn, prot) mk_pte(pfn_to_page(pfn), prot)
	264
3d827367 DM	265	static inline unsigned long pte_pfn(pte_t pte)
	266	{
	267	if (srmmu_device_memory(pte_val(pte))) {
	268	/* Just return something that will cause
	269	* pfn_valid() to return false. This makes
	270	* copy_one_pte() to just directly copy to
	271	* PTE over.
	272	*/
	273	return ~0UL;
	274	}
	275	return (pte_val(pte) & SRMMU_PTE_PMASK) >> (PAGE_SHIFT-4);
	276	}
	277
f5e706ad SR	278	#define pte_page(pte) pfn_to_page(pte_pfn(pte))
	279
	280	/*
	281	* Conversion functions: convert a page and protection to a page entry,
	282	* and a page entry and page directory to the page they refer to.
	283	*/
62875cff DM	284	static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
	285	{
	286	return __pte((page_to_pfn(page) << (PAGE_SHIFT-4)) \| pgprot_val(pgprot));
	287	}
f5e706ad	288
62875cff DM	289	static inline pte_t mk_pte_phys(unsigned long page, pgprot_t pgprot)
	290	{
	291	return __pte(((page) >> 4) \| pgprot_val(pgprot));
	292	}
f5e706ad	293
62875cff DM	294	static inline pte_t mk_pte_io(unsigned long page, pgprot_t pgprot, int space)
	295	{
	296	return __pte(((page) >> 4) \| (space << 28) \| pgprot_val(pgprot));
	297	}
f5e706ad	298
afaedde7 SR	299	#define pgprot_noncached pgprot_noncached
	300	static inline pgprot_t pgprot_noncached(pgprot_t prot)
	301	{
6e6e4187	302	pgprot_val(prot) &= ~pgprot_val(__pgprot(SRMMU_CACHE));
afaedde7 SR	303	return prot;
afaedde7 SR	304	}
f5e706ad	305
f5e706ad SR	306	static pte_t pte_modify(pte_t pte, pgprot_t newprot) __attribute_const__;
	307	static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
	308	{
9701b264	309	return __pte((pte_val(pte) & SRMMU_CHG_MASK) \|
f5e706ad SR	310	pgprot_val(newprot));
	311	}
	312
	313	#define pgd_index(address) ((address) >> PGDIR_SHIFT)
	314
	315	/* to find an entry in a page-table-directory */
	316	#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
	317
	318	/* to find an entry in a kernel page-table-directory */
	319	#define pgd_offset_k(address) pgd_offset(&init_mm, address)
	320
	321	/* Find an entry in the second-level page table.. */
9701b264 SR	322	static inline pmd_t pmd_offset(pgd_t dir, unsigned long address)
	323	{
	324	return (pmd_t ) pgd_page_vaddr(dir) +
	325	((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1));
	326	}
f5e706ad SR	327
f5e706ad SR	328	/* Find an entry in the third-level page table.. */
9701b264	329	pte_t pte_offset_kernel(pmd_t dir, unsigned long address);
f5e706ad SR	330
f5e706ad SR	331	/*
ee906c9e	332	* This shortcut works on sun4m (and sun4d) because the nocache area is static.
f5e706ad SR	333	*/
f5e706ad SR	334	#define pte_offset_map(d, a) pte_offset_kernel(d,a)
f5e706ad	335	#define pte_unmap(pte) do{}while(0)
f5e706ad	336
f5e706ad	337	struct seq_file;
9701b264	338	void mmu_info(struct seq_file *m);
f5e706ad SR	339
	340	/* Fault handler stuff... */
	341	#define FAULT_CODE_PROT 0x1
	342	#define FAULT_CODE_WRITE 0x2
	343	#define FAULT_CODE_USER 0x4
	344
f613914e	345	#define update_mmu_cache(vma, address, ptep) do { } while (0)
f5e706ad	346
9701b264 SR	347	void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
	348	unsigned long xva, unsigned int len);
	349	void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len);
f5e706ad	350
f5e706ad	351	/* Encode and de-code a swap entry */
9701b264 SR	352	static inline unsigned long __swp_type(swp_entry_t entry)
	353	{
	354	return (entry.val >> SRMMU_SWP_TYPE_SHIFT) & SRMMU_SWP_TYPE_MASK;
	355	}
f5e706ad	356
9701b264 SR	357	static inline unsigned long __swp_offset(swp_entry_t entry)
	358	{
	359	return (entry.val >> SRMMU_SWP_OFF_SHIFT) & SRMMU_SWP_OFF_MASK;
	360	}
	361
	362	static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset)
	363	{
	364	return (swp_entry_t) {
	365	(type & SRMMU_SWP_TYPE_MASK) << SRMMU_SWP_TYPE_SHIFT
	366	\| (offset & SRMMU_SWP_OFF_MASK) << SRMMU_SWP_OFF_SHIFT };
	367	}
f5e706ad SR	368
	369	#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
	370	#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
	371
f5e706ad SR	372	static inline unsigned long
	373	__get_phys (unsigned long addr)
	374	{
	375	switch (sparc_cpu_model){
f5e706ad SR	376	case sun4m:
	377	case sun4d:
	378	return ((srmmu_get_pte (addr) & 0xffffff00) << 4);
	379	default:
	380	return 0;
	381	}
	382	}
	383
	384	static inline int
	385	__get_iospace (unsigned long addr)
	386	{
	387	switch (sparc_cpu_model){
f5e706ad SR	388	case sun4m:
	389	case sun4d:
	390	return (srmmu_get_pte (addr) >> 28);
	391	default:
	392	return -1;
	393	}
	394	}
	395
	396	extern unsigned long *sparc_valid_addr_bitmap;
	397
	398	/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
	399	#define kern_addr_valid(addr) \
	400	(test_bit(__pa((unsigned long)(addr))>>20, sparc_valid_addr_bitmap))
	401
f5e706ad SR	402	/*
	403	* For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
	404	* its high 4 bits. These macros/functions put it there or get it from there.
	405	*/
	406	#define MK_IOSPACE_PFN(space, pfn) (pfn \| (space << (BITS_PER_LONG - 4)))
	407	#define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4))
	408	#define GET_PFN(pfn) (pfn & 0x0fffffffUL)
	409
f05a6865 SR	410	int remap_pfn_range(struct vm_area_struct *, unsigned long, unsigned long,
f05a6865 SR	411	unsigned long, pgprot_t);
3e37fd31 DM	412
	413	static inline int io_remap_pfn_range(struct vm_area_struct *vma,
	414	unsigned long from, unsigned long pfn,
	415	unsigned long size, pgprot_t prot)
	416	{
	417	unsigned long long offset, space, phys_base;
	418
	419	offset = ((unsigned long long) GET_PFN(pfn)) << PAGE_SHIFT;
	420	space = GET_IOSPACE(pfn);
	421	phys_base = offset \| (space << 32ULL);
	422
	423	return remap_pfn_range(vma, from, phys_base >> PAGE_SHIFT, size, prot);
	424	}
40d158e6	425	#define io_remap_pfn_range io_remap_pfn_range
3e37fd31	426
f5e706ad SR	427	#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
	428	#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
	429	({ \
	430	int __changed = !pte_same(*(__ptep), __entry); \
	431	if (__changed) { \
	432	set_pte_at((__vma)->vm_mm, (__address), __ptep, __entry); \
	433	flush_tlb_page(__vma, __address); \
	434	} \
1ee0e144	435	__changed; \
f5e706ad SR	436	})
	437
	438	#include <asm-generic/pgtable.h>
	439
	440	#endif /* !(__ASSEMBLY__) */
	441
eb485d64	442	#define VMALLOC_START _AC(0xfe600000,UL)
eb485d64	443	#define VMALLOC_END _AC(0xffc00000,UL)
f5e706ad	444
f5e706ad SR	445	/* We provide our own get_unmapped_area to cope with VA holes for userland */
	446	#define HAVE_ARCH_UNMAPPED_AREA
	447
	448	/*
	449	* No page table caches to initialise
	450	*/
	451	#define pgtable_cache_init() do { } while (0)
	452
	453	#endif /* !(_SPARC_PGTABLE_H) */