[linux-2.6-block.git] / arch / sh / mm / tlb-sh4.c

/*
 * arch/sh/mm/tlb-sh4.c
 *
 * SH-4 specific TLB operations
 *
 * Copyright (C) 1999  Niibe Yutaka
 * Copyright (C) 2002 - 2007 Paul Mundt
 *
 * Released under the terms of the GNU GPL v2.0.
 */
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/io.h>
#include <asm/system.h>
#include <asm/mmu_context.h>
#include <asm/cacheflush.h>

void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
{
	unsigned long flags, pteval, vpn;

	/*
	 * Handle debugger faulting in for debugee.
	 */
	if (vma && current->active_mm != vma->vm_mm)
		return;

	local_irq_save(flags);

	/* Set PTEH register */
	vpn = (address & MMU_VPN_MASK) | get_asid();
	__raw_writel(vpn, MMU_PTEH);

	pteval = pte.pte_low;

	/* Set PTEA register */
#ifdef CONFIG_X2TLB
	/*
	 * For the extended mode TLB this is trivial, only the ESZ and
	 * EPR bits need to be written out to PTEA, with the remainder of
	 * the protection bits (with the exception of the compat-mode SZ
	 * and PR bits, which are cleared) being written out in PTEL.
	 */
	__raw_writel(pte.pte_high, MMU_PTEA);
#else
	if (cpu_data->flags & CPU_HAS_PTEA) {
		/* The last 3 bits and the first one of pteval contains
		 * the PTEA timing control and space attribute bits
		 */
		__raw_writel(copy_ptea_attributes(pteval), MMU_PTEA);
	}
#endif

	/* Set PTEL register */
	pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
#ifdef CONFIG_CACHE_WRITETHROUGH
	pteval |= _PAGE_WT;
#endif
	/* conveniently, we want all the software flags to be 0 anyway */
	__raw_writel(pteval, MMU_PTEL);

	/* Load the TLB */
	asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
	local_irq_restore(flags);
}

void local_flush_tlb_one(unsigned long asid, unsigned long page)
{
	unsigned long addr, data;

	/*
	 * NOTE: PTEH.ASID should be set to this MM
	 *       _AND_ we need to write ASID to the array.
	 *
	 * It would be simple if we didn't need to set PTEH.ASID...
	 */
	addr = MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT;
	data = page | asid; /* VALID bit is off */
	jump_to_uncached();
	__raw_writel(data, addr);
	back_to_cached();
}

void local_flush_tlb_all(void)
{
	unsigned long flags, status;
	int i;

	/*
	 * Flush all the TLB.
	 */
	local_irq_save(flags);
	jump_to_uncached();

	status = __raw_readl(MMUCR);
	status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT);

	if (status == 0)
		status = MMUCR_URB_NENTRIES;

	for (i = 0; i < status; i++)
		__raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));

	for (i = 0; i < 4; i++)
		__raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8));

	back_to_cached();
	ctrl_barrier();
	local_irq_restore(flags);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* arch/sh/mm/tlb-sh4.c
	3	*
	4	* SH-4 specific TLB operations
	5	*
	6	* Copyright (C) 1999 Niibe Yutaka
d04a0f79	7	* Copyright (C) 2002 - 2007 Paul Mundt
1da177e4 LT	8	*
	9	* Released under the terms of the GNU GPL v2.0.
	10	*/
39e688a9	11	#include <linux/kernel.h>
39e688a9	12	#include <linux/mm.h>
d04a0f79	13	#include <linux/io.h>
1da177e4	14	#include <asm/system.h>
1da177e4	15	#include <asm/mmu_context.h>
39e688a9 PM	16	#include <asm/cacheflush.h>
39e688a9 PM	17
9cef7492	18	void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
39e688a9	19	{
9cef7492	20	unsigned long flags, pteval, vpn;
39e688a9	21
9cef7492 PM	22	/*
	23	* Handle debugger faulting in for debugee.
	24	*/
3ed6e129	25	if (vma && current->active_mm != vma->vm_mm)
39e688a9 PM	26	return;
39e688a9 PM	27
39e688a9 PM	28	local_irq_save(flags);
	29
	30	/* Set PTEH register */
	31	vpn = (address & MMU_VPN_MASK) \| get_asid();
9d56dd3b	32	__raw_writel(vpn, MMU_PTEH);
39e688a9	33
d04a0f79	34	pteval = pte.pte_low;
39e688a9 PM	35
39e688a9 PM	36	/* Set PTEA register */
d04a0f79 PM	37	#ifdef CONFIG_X2TLB
	38	/*
	39	* For the extended mode TLB this is trivial, only the ESZ and
	40	* EPR bits need to be written out to PTEA, with the remainder of
	41	* the protection bits (with the exception of the compat-mode SZ
	42	* and PR bits, which are cleared) being written out in PTEL.
	43	*/
9d56dd3b	44	__raw_writel(pte.pte_high, MMU_PTEA);
d04a0f79	45	#else
6503fe4a MT	46	if (cpu_data->flags & CPU_HAS_PTEA) {
	47	/* The last 3 bits and the first one of pteval contains
	48	* the PTEA timing control and space attribute bits
	49	*/
9d56dd3b	50	__raw_writel(copy_ptea_attributes(pteval), MMU_PTEA);
6503fe4a	51	}
d04a0f79	52	#endif
39e688a9 PM	53
	54	/* Set PTEL register */
	55	pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
e7bd34a1	56	#ifdef CONFIG_CACHE_WRITETHROUGH
39e688a9 PM	57	pteval \|= _PAGE_WT;
	58	#endif
	59	/* conveniently, we want all the software flags to be 0 anyway */
9d56dd3b	60	__raw_writel(pteval, MMU_PTEL);
39e688a9 PM	61
	62	/* Load the TLB */
	63	asm volatile("ldtlb": /* no output / : / no input */ : "memory");
	64	local_irq_restore(flags);
	65	}
1da177e4	66
2dc2f8e0	67	void local_flush_tlb_one(unsigned long asid, unsigned long page)
1da177e4 LT	68	{
	69	unsigned long addr, data;
	70
	71	/*
	72	* NOTE: PTEH.ASID should be set to this MM
	73	* _AND_ we need to write ASID to the array.
	74	*
	75	* It would be simple if we didn't need to set PTEH.ASID...
	76	*/
	77	addr = MMU_UTLB_ADDRESS_ARRAY \| MMU_PAGE_ASSOC_BIT;
	78	data = page \| asid; /* VALID bit is off */
cbaa118e	79	jump_to_uncached();
9d56dd3b	80	__raw_writel(data, addr);
cbaa118e	81	back_to_cached();
1da177e4	82	}
be97d758 PM	83
	84	void local_flush_tlb_all(void)
	85	{
	86	unsigned long flags, status;
	87	int i;
	88
	89	/*
	90	* Flush all the TLB.
	91	*/
	92	local_irq_save(flags);
	93	jump_to_uncached();
	94
	95	status = __raw_readl(MMUCR);
	96	status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT);
	97
	98	if (status == 0)
	99	status = MMUCR_URB_NENTRIES;
	100
	101	for (i = 0; i < status; i++)
	102	__raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY \| (i << 8));
	103
	104	for (i = 0; i < 4; i++)
	105	__raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY \| (i << 8));
	106
	107	back_to_cached();
	108	ctrl_barrier();
	109	local_irq_restore(flags);
	110	}