[linux-2.6-block.git] / arch / sh / mm / tlb-sh3.c

/*
 * arch/sh/mm/tlb-sh3.c
 *
 * SH-3 specific TLB operations
 *
 * Copyright (C) 1999  Niibe Yutaka
 * Copyright (C) 2002  Paul Mundt
 *
 * Released under the terms of the GNU GPL v2.0.
 */
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/types.h>
#include <linux/ptrace.h>
#include <linux/mman.h>
#include <linux/mm.h>
#include <linux/smp.h>
#include <linux/interrupt.h>

#include <asm/system.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <asm/pgalloc.h>
#include <asm/mmu_context.h>
#include <asm/cacheflush.h>

void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
{
	unsigned long flags, pteval, vpn;

	/*
	 * Handle debugger faulting in for debugee.
	 */
	if (vma && current->active_mm != vma->vm_mm)
		return;

	local_irq_save(flags);

	/* Set PTEH register */
	vpn = (address & MMU_VPN_MASK) | get_asid();
	__raw_writel(vpn, MMU_PTEH);

	pteval = pte_val(pte);

	/* Set PTEL register */
	pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
	/* conveniently, we want all the software flags to be 0 anyway */
	__raw_writel(pteval, MMU_PTEL);

	/* Load the TLB */
	asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
	local_irq_restore(flags);
}

void local_flush_tlb_one(unsigned long asid, unsigned long page)
{
	unsigned long addr, data;
	int i, ways = MMU_NTLB_WAYS;

	/*
	 * NOTE: PTEH.ASID should be set to this MM
	 *       _AND_ we need to write ASID to the array.
	 *
	 * It would be simple if we didn't need to set PTEH.ASID...
	 */
	addr = MMU_TLB_ADDRESS_ARRAY | (page & 0x1F000);
	data = (page & 0xfffe0000) | asid; /* VALID bit is off */

	if ((current_cpu_data.flags & CPU_HAS_MMU_PAGE_ASSOC)) {
		addr |= MMU_PAGE_ASSOC_BIT;
		ways = 1;	/* we already know the way .. */
	}

	for (i = 0; i < ways; i++)
		__raw_writel(data, addr + (i << 8));
}

void local_flush_tlb_all(void)
{
	unsigned long flags, status;

	/*
	 * Flush all the TLB.
	 *
	 * Write to the MMU control register's bit:
	 *	TF-bit for SH-3, TI-bit for SH-4.
	 *      It's same position, bit #2.
	 */
	local_irq_save(flags);
	status = __raw_readl(MMUCR);
	status |= 0x04;
	__raw_writel(status, MMUCR);
	ctrl_barrier();
	local_irq_restore(flags);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* arch/sh/mm/tlb-sh3.c
	3	*
	4	* SH-3 specific TLB operations
	5	*
	6	* Copyright (C) 1999 Niibe Yutaka
	7	* Copyright (C) 2002 Paul Mundt
	8	*
	9	* Released under the terms of the GNU GPL v2.0.
	10	*/
39e688a9 PM	11	#include <linux/signal.h>
	12	#include <linux/sched.h>
	13	#include <linux/kernel.h>
	14	#include <linux/errno.h>
	15	#include <linux/string.h>
	16	#include <linux/types.h>
	17	#include <linux/ptrace.h>
	18	#include <linux/mman.h>
	19	#include <linux/mm.h>
	20	#include <linux/smp.h>
39e688a9 PM	21	#include <linux/interrupt.h>
39e688a9 PM	22
1da177e4	23	#include <asm/system.h>
39e688a9 PM	24	#include <asm/io.h>
	25	#include <asm/uaccess.h>
	26	#include <asm/pgalloc.h>
1da177e4	27	#include <asm/mmu_context.h>
39e688a9 PM	28	#include <asm/cacheflush.h>
39e688a9 PM	29
9cef7492	30	void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
39e688a9	31	{
9cef7492	32	unsigned long flags, pteval, vpn;
39e688a9	33
9cef7492 PM	34	/*
	35	* Handle debugger faulting in for debugee.
	36	*/
3ed6e129	37	if (vma && current->active_mm != vma->vm_mm)
39e688a9 PM	38	return;
39e688a9 PM	39
39e688a9 PM	40	local_irq_save(flags);
	41
	42	/* Set PTEH register */
	43	vpn = (address & MMU_VPN_MASK) \| get_asid();
9d56dd3b	44	__raw_writel(vpn, MMU_PTEH);
39e688a9 PM	45
	46	pteval = pte_val(pte);
	47
	48	/* Set PTEL register */
	49	pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
	50	/* conveniently, we want all the software flags to be 0 anyway */
9d56dd3b	51	__raw_writel(pteval, MMU_PTEL);
39e688a9 PM	52
	53	/* Load the TLB */
	54	asm volatile("ldtlb": /* no output / : / no input */ : "memory");
	55	local_irq_restore(flags);
	56	}
1da177e4	57
ea9af694	58	void local_flush_tlb_one(unsigned long asid, unsigned long page)
1da177e4 LT	59	{
	60	unsigned long addr, data;
	61	int i, ways = MMU_NTLB_WAYS;
	62
	63	/*
	64	* NOTE: PTEH.ASID should be set to this MM
	65	* _AND_ we need to write ASID to the array.
	66	*
	67	* It would be simple if we didn't need to set PTEH.ASID...
	68	*/
	69	addr = MMU_TLB_ADDRESS_ARRAY \| (page & 0x1F000);
	70	data = (page & 0xfffe0000) \| asid; /* VALID bit is off */
0d6d82b6	71
11c19656	72	if ((current_cpu_data.flags & CPU_HAS_MMU_PAGE_ASSOC)) {
1da177e4 LT	73	addr \|= MMU_PAGE_ASSOC_BIT;
	74	ways = 1; /* we already know the way .. */
	75	}
	76
	77	for (i = 0; i < ways; i++)
9d56dd3b	78	__raw_writel(data, addr + (i << 8));
1da177e4	79	}
be97d758 PM	80
	81	void local_flush_tlb_all(void)
	82	{
	83	unsigned long flags, status;
	84
	85	/*
	86	* Flush all the TLB.
	87	*
	88	* Write to the MMU control register's bit:
	89	* TF-bit for SH-3, TI-bit for SH-4.
	90	* It's same position, bit #2.
	91	*/
	92	local_irq_save(flags);
	93	status = __raw_readl(MMUCR);
	94	status \|= 0x04;
	95	__raw_writel(status, MMUCR);
	96	ctrl_barrier();
	97	local_irq_restore(flags);
	98	}