[linux-2.6-block.git] / arch / sh / mm / flush-sh4.c

// SPDX-License-Identifier: GPL-2.0
#include <linux/mm.h>
#include <asm/mmu_context.h>
#include <asm/cache_insns.h>
#include <asm/cacheflush.h>
#include <asm/traps.h>

/*
 * Write back the dirty D-caches, but not invalidate them.
 *
 * START: Virtual Address (U0, P1, or P3)
 * SIZE: Size of the region.
 */
static void sh4__flush_wback_region(void *start, int size)
{
	reg_size_t aligned_start, v, cnt, end;

	aligned_start = register_align(start);
	v = aligned_start & ~(L1_CACHE_BYTES-1);
	end = (aligned_start + size + L1_CACHE_BYTES-1)
		& ~(L1_CACHE_BYTES-1);
	cnt = (end - v) / L1_CACHE_BYTES;

	while (cnt >= 8) {
		__ocbwb(v); v += L1_CACHE_BYTES;
		__ocbwb(v); v += L1_CACHE_BYTES;
		__ocbwb(v); v += L1_CACHE_BYTES;
		__ocbwb(v); v += L1_CACHE_BYTES;
		__ocbwb(v); v += L1_CACHE_BYTES;
		__ocbwb(v); v += L1_CACHE_BYTES;
		__ocbwb(v); v += L1_CACHE_BYTES;
		__ocbwb(v); v += L1_CACHE_BYTES;
		cnt -= 8;
	}

	while (cnt) {
		__ocbwb(v); v += L1_CACHE_BYTES;
		cnt--;
	}
}

/*
 * Write back the dirty D-caches and invalidate them.
 *
 * START: Virtual Address (U0, P1, or P3)
 * SIZE: Size of the region.
 */
static void sh4__flush_purge_region(void *start, int size)
{
	reg_size_t aligned_start, v, cnt, end;

	aligned_start = register_align(start);
	v = aligned_start & ~(L1_CACHE_BYTES-1);
	end = (aligned_start + size + L1_CACHE_BYTES-1)
		& ~(L1_CACHE_BYTES-1);
	cnt = (end - v) / L1_CACHE_BYTES;

	while (cnt >= 8) {
		__ocbp(v); v += L1_CACHE_BYTES;
		__ocbp(v); v += L1_CACHE_BYTES;
		__ocbp(v); v += L1_CACHE_BYTES;
		__ocbp(v); v += L1_CACHE_BYTES;
		__ocbp(v); v += L1_CACHE_BYTES;
		__ocbp(v); v += L1_CACHE_BYTES;
		__ocbp(v); v += L1_CACHE_BYTES;
		__ocbp(v); v += L1_CACHE_BYTES;
		cnt -= 8;
	}
	while (cnt) {
		__ocbp(v); v += L1_CACHE_BYTES;
		cnt--;
	}
}

/*
 * No write back please
 */
static void sh4__flush_invalidate_region(void *start, int size)
{
	reg_size_t aligned_start, v, cnt, end;

	aligned_start = register_align(start);
	v = aligned_start & ~(L1_CACHE_BYTES-1);
	end = (aligned_start + size + L1_CACHE_BYTES-1)
		& ~(L1_CACHE_BYTES-1);
	cnt = (end - v) / L1_CACHE_BYTES;

	while (cnt >= 8) {
		__ocbi(v); v += L1_CACHE_BYTES;
		__ocbi(v); v += L1_CACHE_BYTES;
		__ocbi(v); v += L1_CACHE_BYTES;
		__ocbi(v); v += L1_CACHE_BYTES;
		__ocbi(v); v += L1_CACHE_BYTES;
		__ocbi(v); v += L1_CACHE_BYTES;
		__ocbi(v); v += L1_CACHE_BYTES;
		__ocbi(v); v += L1_CACHE_BYTES;
		cnt -= 8;
	}

	while (cnt) {
		__ocbi(v); v += L1_CACHE_BYTES;
		cnt--;
	}
}

void __init sh4__flush_region_init(void)
{
	__flush_wback_region		= sh4__flush_wback_region;
	__flush_invalidate_region	= sh4__flush_invalidate_region;
	__flush_purge_region		= sh4__flush_purge_region;
}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
81742527 PM	2	#include <linux/mm.h>
81742527 PM	3	#include <asm/mmu_context.h>
f03c4866	4	#include <asm/cache_insns.h>
81742527	5	#include <asm/cacheflush.h>
e839ca52	6	#include <asm/traps.h>
81742527 PM	7
	8	/*
	9	* Write back the dirty D-caches, but not invalidate them.
	10	*
	11	* START: Virtual Address (U0, P1, or P3)
	12	* SIZE: Size of the region.
	13	*/
37443ef3	14	static void sh4__flush_wback_region(void *start, int size)
81742527	15	{
43bc61d8	16	reg_size_t aligned_start, v, cnt, end;
81742527	17
43bc61d8 PM	18	aligned_start = register_align(start);
	19	v = aligned_start & ~(L1_CACHE_BYTES-1);
	20	end = (aligned_start + size + L1_CACHE_BYTES-1)
81742527	21	& ~(L1_CACHE_BYTES-1);
0837f524 PM	22	cnt = (end - v) / L1_CACHE_BYTES;
	23
	24	while (cnt >= 8) {
94ecd224 PM	25	__ocbwb(v); v += L1_CACHE_BYTES;
	26	__ocbwb(v); v += L1_CACHE_BYTES;
	27	__ocbwb(v); v += L1_CACHE_BYTES;
	28	__ocbwb(v); v += L1_CACHE_BYTES;
	29	__ocbwb(v); v += L1_CACHE_BYTES;
	30	__ocbwb(v); v += L1_CACHE_BYTES;
	31	__ocbwb(v); v += L1_CACHE_BYTES;
	32	__ocbwb(v); v += L1_CACHE_BYTES;
0837f524 PM	33	cnt -= 8;
	34	}
	35
	36	while (cnt) {
94ecd224	37	__ocbwb(v); v += L1_CACHE_BYTES;
0837f524	38	cnt--;
81742527 PM	39	}
	40	}
	41
	42	/*
	43	* Write back the dirty D-caches and invalidate them.
	44	*
	45	* START: Virtual Address (U0, P1, or P3)
	46	* SIZE: Size of the region.
	47	*/
37443ef3	48	static void sh4__flush_purge_region(void *start, int size)
81742527	49	{
43bc61d8	50	reg_size_t aligned_start, v, cnt, end;
81742527	51
43bc61d8 PM	52	aligned_start = register_align(start);
	53	v = aligned_start & ~(L1_CACHE_BYTES-1);
	54	end = (aligned_start + size + L1_CACHE_BYTES-1)
81742527	55	& ~(L1_CACHE_BYTES-1);
0837f524 PM	56	cnt = (end - v) / L1_CACHE_BYTES;
	57
	58	while (cnt >= 8) {
94ecd224 PM	59	__ocbp(v); v += L1_CACHE_BYTES;
	60	__ocbp(v); v += L1_CACHE_BYTES;
	61	__ocbp(v); v += L1_CACHE_BYTES;
	62	__ocbp(v); v += L1_CACHE_BYTES;
	63	__ocbp(v); v += L1_CACHE_BYTES;
	64	__ocbp(v); v += L1_CACHE_BYTES;
	65	__ocbp(v); v += L1_CACHE_BYTES;
	66	__ocbp(v); v += L1_CACHE_BYTES;
0837f524 PM	67	cnt -= 8;
	68	}
	69	while (cnt) {
94ecd224	70	__ocbp(v); v += L1_CACHE_BYTES;
0837f524	71	cnt--;
81742527 PM	72	}
	73	}
	74
	75	/*
	76	* No write back please
	77	*/
37443ef3	78	static void sh4__flush_invalidate_region(void *start, int size)
81742527	79	{
43bc61d8	80	reg_size_t aligned_start, v, cnt, end;
81742527	81
43bc61d8 PM	82	aligned_start = register_align(start);
	83	v = aligned_start & ~(L1_CACHE_BYTES-1);
	84	end = (aligned_start + size + L1_CACHE_BYTES-1)
81742527	85	& ~(L1_CACHE_BYTES-1);
0837f524 PM	86	cnt = (end - v) / L1_CACHE_BYTES;
	87
	88	while (cnt >= 8) {
94ecd224 PM	89	__ocbi(v); v += L1_CACHE_BYTES;
	90	__ocbi(v); v += L1_CACHE_BYTES;
	91	__ocbi(v); v += L1_CACHE_BYTES;
	92	__ocbi(v); v += L1_CACHE_BYTES;
	93	__ocbi(v); v += L1_CACHE_BYTES;
	94	__ocbi(v); v += L1_CACHE_BYTES;
	95	__ocbi(v); v += L1_CACHE_BYTES;
	96	__ocbi(v); v += L1_CACHE_BYTES;
0837f524 PM	97	cnt -= 8;
	98	}
	99
	100	while (cnt) {
94ecd224	101	__ocbi(v); v += L1_CACHE_BYTES;
0837f524	102	cnt--;
81742527 PM	103	}
81742527 PM	104	}
37443ef3 PM	105
	106	void __init sh4__flush_region_init(void)
	107	{
	108	__flush_wback_region = sh4__flush_wback_region;
	109	__flush_invalidate_region = sh4__flush_invalidate_region;
	110	__flush_purge_region = sh4__flush_purge_region;
	111	}