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81742527 PM |
1 | #include <linux/mm.h> |
2 | #include <asm/mmu_context.h> | |
f03c4866 | 3 | #include <asm/cache_insns.h> |
81742527 | 4 | #include <asm/cacheflush.h> |
e839ca52 | 5 | #include <asm/traps.h> |
81742527 PM |
6 | |
7 | /* | |
8 | * Write back the dirty D-caches, but not invalidate them. | |
9 | * | |
10 | * START: Virtual Address (U0, P1, or P3) | |
11 | * SIZE: Size of the region. | |
12 | */ | |
37443ef3 | 13 | static void sh4__flush_wback_region(void *start, int size) |
81742527 | 14 | { |
43bc61d8 | 15 | reg_size_t aligned_start, v, cnt, end; |
81742527 | 16 | |
43bc61d8 PM |
17 | aligned_start = register_align(start); |
18 | v = aligned_start & ~(L1_CACHE_BYTES-1); | |
19 | end = (aligned_start + size + L1_CACHE_BYTES-1) | |
81742527 | 20 | & ~(L1_CACHE_BYTES-1); |
0837f524 PM |
21 | cnt = (end - v) / L1_CACHE_BYTES; |
22 | ||
23 | while (cnt >= 8) { | |
94ecd224 PM |
24 | __ocbwb(v); v += L1_CACHE_BYTES; |
25 | __ocbwb(v); v += L1_CACHE_BYTES; | |
26 | __ocbwb(v); v += L1_CACHE_BYTES; | |
27 | __ocbwb(v); v += L1_CACHE_BYTES; | |
28 | __ocbwb(v); v += L1_CACHE_BYTES; | |
29 | __ocbwb(v); v += L1_CACHE_BYTES; | |
30 | __ocbwb(v); v += L1_CACHE_BYTES; | |
31 | __ocbwb(v); v += L1_CACHE_BYTES; | |
0837f524 PM |
32 | cnt -= 8; |
33 | } | |
34 | ||
35 | while (cnt) { | |
94ecd224 | 36 | __ocbwb(v); v += L1_CACHE_BYTES; |
0837f524 | 37 | cnt--; |
81742527 PM |
38 | } |
39 | } | |
40 | ||
41 | /* | |
42 | * Write back the dirty D-caches and invalidate them. | |
43 | * | |
44 | * START: Virtual Address (U0, P1, or P3) | |
45 | * SIZE: Size of the region. | |
46 | */ | |
37443ef3 | 47 | static void sh4__flush_purge_region(void *start, int size) |
81742527 | 48 | { |
43bc61d8 | 49 | reg_size_t aligned_start, v, cnt, end; |
81742527 | 50 | |
43bc61d8 PM |
51 | aligned_start = register_align(start); |
52 | v = aligned_start & ~(L1_CACHE_BYTES-1); | |
53 | end = (aligned_start + size + L1_CACHE_BYTES-1) | |
81742527 | 54 | & ~(L1_CACHE_BYTES-1); |
0837f524 PM |
55 | cnt = (end - v) / L1_CACHE_BYTES; |
56 | ||
57 | while (cnt >= 8) { | |
94ecd224 PM |
58 | __ocbp(v); v += L1_CACHE_BYTES; |
59 | __ocbp(v); v += L1_CACHE_BYTES; | |
60 | __ocbp(v); v += L1_CACHE_BYTES; | |
61 | __ocbp(v); v += L1_CACHE_BYTES; | |
62 | __ocbp(v); v += L1_CACHE_BYTES; | |
63 | __ocbp(v); v += L1_CACHE_BYTES; | |
64 | __ocbp(v); v += L1_CACHE_BYTES; | |
65 | __ocbp(v); v += L1_CACHE_BYTES; | |
0837f524 PM |
66 | cnt -= 8; |
67 | } | |
68 | while (cnt) { | |
94ecd224 | 69 | __ocbp(v); v += L1_CACHE_BYTES; |
0837f524 | 70 | cnt--; |
81742527 PM |
71 | } |
72 | } | |
73 | ||
74 | /* | |
75 | * No write back please | |
76 | */ | |
37443ef3 | 77 | static void sh4__flush_invalidate_region(void *start, int size) |
81742527 | 78 | { |
43bc61d8 | 79 | reg_size_t aligned_start, v, cnt, end; |
81742527 | 80 | |
43bc61d8 PM |
81 | aligned_start = register_align(start); |
82 | v = aligned_start & ~(L1_CACHE_BYTES-1); | |
83 | end = (aligned_start + size + L1_CACHE_BYTES-1) | |
81742527 | 84 | & ~(L1_CACHE_BYTES-1); |
0837f524 PM |
85 | cnt = (end - v) / L1_CACHE_BYTES; |
86 | ||
87 | while (cnt >= 8) { | |
94ecd224 PM |
88 | __ocbi(v); v += L1_CACHE_BYTES; |
89 | __ocbi(v); v += L1_CACHE_BYTES; | |
90 | __ocbi(v); v += L1_CACHE_BYTES; | |
91 | __ocbi(v); v += L1_CACHE_BYTES; | |
92 | __ocbi(v); v += L1_CACHE_BYTES; | |
93 | __ocbi(v); v += L1_CACHE_BYTES; | |
94 | __ocbi(v); v += L1_CACHE_BYTES; | |
95 | __ocbi(v); v += L1_CACHE_BYTES; | |
0837f524 PM |
96 | cnt -= 8; |
97 | } | |
98 | ||
99 | while (cnt) { | |
94ecd224 | 100 | __ocbi(v); v += L1_CACHE_BYTES; |
0837f524 | 101 | cnt--; |
81742527 PM |
102 | } |
103 | } | |
37443ef3 PM |
104 | |
105 | void __init sh4__flush_region_init(void) | |
106 | { | |
107 | __flush_wback_region = sh4__flush_wback_region; | |
108 | __flush_invalidate_region = sh4__flush_invalidate_region; | |
109 | __flush_purge_region = sh4__flush_purge_region; | |
110 | } |