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1 | menu "Memory management options" |
2 | ||
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3 | config QUICKLIST |
4 | def_bool y | |
5 | ||
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6 | config MMU |
7 | bool "Support for memory management hardware" | |
8 | depends on !CPU_SH2 | |
9 | default y | |
10 | help | |
11 | Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to | |
12 | boot on these systems, this option must not be set. | |
13 | ||
14 | On other systems (such as the SH-3 and 4) where an MMU exists, | |
15 | turning this off will boot the kernel on these machines with the | |
16 | MMU implicitly switched off. | |
17 | ||
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18 | config PAGE_OFFSET |
19 | hex | |
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20 | default "0x80000000" if MMU && SUPERH32 |
21 | default "0x20000000" if MMU && SUPERH64 | |
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22 | default "0x00000000" |
23 | ||
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24 | config FORCE_MAX_ZONEORDER |
25 | int "Maximum zone order" | |
26 | range 9 64 if PAGE_SIZE_16KB | |
27 | default "9" if PAGE_SIZE_16KB | |
28 | range 7 64 if PAGE_SIZE_64KB | |
29 | default "7" if PAGE_SIZE_64KB | |
30 | range 11 64 | |
31 | default "14" if !MMU | |
32 | default "11" | |
33 | help | |
34 | The kernel memory allocator divides physically contiguous memory | |
35 | blocks into "zones", where each zone is a power of two number of | |
36 | pages. This option selects the largest power of two that the kernel | |
37 | keeps in the memory allocator. If you need to allocate very large | |
38 | blocks of physically contiguous memory, then you may need to | |
39 | increase this value. | |
40 | ||
41 | This config option is actually maximum order plus one. For example, | |
42 | a value of 11 means that the largest free memory block is 2^10 pages. | |
43 | ||
44 | The page size is not necessarily 4KB. Keep this in mind when | |
45 | choosing a value for this option. | |
46 | ||
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47 | config MEMORY_START |
48 | hex "Physical memory start address" | |
49 | default "0x08000000" | |
50 | ---help--- | |
51 | Computers built with Hitachi SuperH processors always | |
52 | map the ROM starting at address zero. But the processor | |
53 | does not specify the range that RAM takes. | |
54 | ||
55 | The physical memory (RAM) start address will be automatically | |
56 | set to 08000000. Other platforms, such as the Solution Engine | |
57 | boards typically map RAM at 0C000000. | |
58 | ||
59 | Tweak this only when porting to a new machine which does not | |
60 | already have a defconfig. Changing it from the known correct | |
61 | value on any of the known systems will only lead to disaster. | |
62 | ||
63 | config MEMORY_SIZE | |
64 | hex "Physical memory size" | |
711fe436 | 65 | default "0x04000000" |
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66 | help |
67 | This sets the default memory size assumed by your SH kernel. It can | |
68 | be overridden as normal by the 'mem=' argument on the kernel command | |
69 | line. If unsure, consult your board specifications or just leave it | |
711fe436 | 70 | as 0x04000000 which was the default value before this became |
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71 | configurable. |
72 | ||
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73 | # Physical addressing modes |
74 | ||
75 | config 29BIT | |
76 | def_bool !32BIT | |
77 | depends on SUPERH32 | |
b0f3ae03 | 78 | select UNCACHED_MAPPING |
36bcd39d | 79 | |
cad82448 | 80 | config 32BIT |
36bcd39d | 81 | bool |
e2fcf74f | 82 | default y if CPU_SH5 || !MMU |
36bcd39d | 83 | |
2f47f447 | 84 | config PMB |
a0ab3668 | 85 | bool "Support 32-bit physical addressing through PMB" |
b4e2a2a2 | 86 | depends on MMU && EXPERIMENTAL && CPU_SH4A && !CPU_SH4AL_DSP |
a0ab3668 | 87 | select 32BIT |
b0f3ae03 | 88 | select UNCACHED_MAPPING |
2f47f447 YS |
89 | help |
90 | If you say Y here, physical addressing will be extended to | |
91 | 32-bits through the SH-4A PMB. If this is not set, legacy | |
92 | 29-bit physical addressing will be used. | |
93 | ||
21440cf0 | 94 | config X2TLB |
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95 | def_bool y |
96 | depends on (CPU_SHX2 || CPU_SHX3) && MMU | |
21440cf0 | 97 | |
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98 | config VSYSCALL |
99 | bool "Support vsyscall page" | |
a09063da | 100 | depends on MMU && (CPU_SH3 || CPU_SH4) |
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101 | default y |
102 | help | |
103 | This will enable support for the kernel mapping a vDSO page | |
104 | in process space, and subsequently handing down the entry point | |
105 | to the libc through the ELF auxiliary vector. | |
106 | ||
107 | From the kernel side this is used for the signal trampoline. | |
108 | For systems with an MMU that can afford to give up a page, | |
109 | (the default value) say Y. | |
110 | ||
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111 | config NUMA |
112 | bool "Non Uniform Memory Access (NUMA) Support" | |
357d5946 | 113 | depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL |
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114 | default n |
115 | help | |
116 | Some SH systems have many various memories scattered around | |
117 | the address space, each with varying latencies. This enables | |
118 | support for these blocks by binding them to nodes and allowing | |
119 | memory policies to be used for prioritizing and controlling | |
120 | allocation behaviour. | |
121 | ||
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122 | config NODES_SHIFT |
123 | int | |
9904494d | 124 | default "3" if CPU_SUBTYPE_SHX3 |
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125 | default "1" |
126 | depends on NEED_MULTIPLE_NODES | |
127 | ||
128 | config ARCH_FLATMEM_ENABLE | |
129 | def_bool y | |
357d5946 | 130 | depends on !NUMA |
01066625 | 131 | |
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132 | config ARCH_SPARSEMEM_ENABLE |
133 | def_bool y | |
134 | select SPARSEMEM_STATIC | |
135 | ||
136 | config ARCH_SPARSEMEM_DEFAULT | |
137 | def_bool y | |
138 | ||
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139 | config MAX_ACTIVE_REGIONS |
140 | int | |
7da3b8ef | 141 | default "6" if (CPU_SUBTYPE_SHX3 && SPARSEMEM) |
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142 | default "2" if SPARSEMEM && (CPU_SUBTYPE_SH7722 || \ |
143 | CPU_SUBTYPE_SH7785) | |
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144 | default "1" |
145 | ||
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146 | config ARCH_POPULATES_NODE_MAP |
147 | def_bool y | |
148 | ||
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149 | config ARCH_SELECT_MEMORY_MODEL |
150 | def_bool y | |
151 | ||
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152 | config ARCH_ENABLE_MEMORY_HOTPLUG |
153 | def_bool y | |
b85641bd | 154 | depends on SPARSEMEM && MMU |
33d63bd8 | 155 | |
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156 | config ARCH_ENABLE_MEMORY_HOTREMOVE |
157 | def_bool y | |
b85641bd | 158 | depends on SPARSEMEM && MMU |
3159e7d6 | 159 | |
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160 | config ARCH_MEMORY_PROBE |
161 | def_bool y | |
162 | depends on MEMORY_HOTPLUG | |
163 | ||
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164 | config IOREMAP_FIXED |
165 | def_bool y | |
166 | depends on X2TLB || SUPERH64 | |
167 | ||
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168 | config UNCACHED_MAPPING |
169 | bool | |
170 | ||
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171 | config HAVE_SRAM_POOL |
172 | bool | |
173 | select GENERIC_ALLOCATOR | |
174 | ||
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175 | choice |
176 | prompt "Kernel page size" | |
177 | default PAGE_SIZE_4KB | |
178 | ||
179 | config PAGE_SIZE_4KB | |
180 | bool "4kB" | |
181 | help | |
182 | This is the default page size used by all SuperH CPUs. | |
183 | ||
184 | config PAGE_SIZE_8KB | |
185 | bool "8kB" | |
3f5ab768 | 186 | depends on !MMU || X2TLB |
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187 | help |
188 | This enables 8kB pages as supported by SH-X2 and later MMUs. | |
189 | ||
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190 | config PAGE_SIZE_16KB |
191 | bool "16kB" | |
192 | depends on !MMU | |
193 | help | |
194 | This enables 16kB pages on MMU-less SH systems. | |
195 | ||
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196 | config PAGE_SIZE_64KB |
197 | bool "64kB" | |
3f5ab768 | 198 | depends on !MMU || CPU_SH4 || CPU_SH5 |
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199 | help |
200 | This enables support for 64kB pages, possible on all SH-4 | |
4d2cab7c | 201 | CPUs and later. |
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202 | |
203 | endchoice | |
204 | ||
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205 | choice |
206 | prompt "HugeTLB page size" | |
ffb4a73d | 207 | depends on HUGETLB_PAGE |
68b7c24c | 208 | default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB |
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209 | default HUGETLB_PAGE_SIZE_64K |
210 | ||
211 | config HUGETLB_PAGE_SIZE_64K | |
21440cf0 | 212 | bool "64kB" |
68b7c24c | 213 | depends on !PAGE_SIZE_64KB |
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214 | |
215 | config HUGETLB_PAGE_SIZE_256K | |
216 | bool "256kB" | |
217 | depends on X2TLB | |
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218 | |
219 | config HUGETLB_PAGE_SIZE_1MB | |
220 | bool "1MB" | |
221 | ||
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222 | config HUGETLB_PAGE_SIZE_4MB |
223 | bool "4MB" | |
224 | depends on X2TLB | |
225 | ||
226 | config HUGETLB_PAGE_SIZE_64MB | |
227 | bool "64MB" | |
228 | depends on X2TLB | |
229 | ||
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230 | config HUGETLB_PAGE_SIZE_512MB |
231 | bool "512MB" | |
232 | depends on CPU_SH5 | |
233 | ||
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234 | endchoice |
235 | ||
236 | source "mm/Kconfig" | |
237 | ||
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238 | config SCHED_MC |
239 | bool "Multi-core scheduler support" | |
240 | depends on SMP | |
241 | default y | |
242 | help | |
243 | Multi-core scheduler support improves the CPU scheduler's decision | |
244 | making when dealing with multi-core CPU chips at a cost of slightly | |
245 | increased overhead in some places. If unsure say N here. | |
246 | ||
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247 | endmenu |
248 | ||
249 | menu "Cache configuration" | |
250 | ||
251 | config SH7705_CACHE_32KB | |
252 | bool "Enable 32KB cache size for SH7705" | |
253 | depends on CPU_SUBTYPE_SH7705 | |
254 | default y | |
255 | ||
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256 | choice |
257 | prompt "Cache mode" | |
a09063da | 258 | default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5 |
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259 | default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A) |
260 | ||
261 | config CACHE_WRITEBACK | |
262 | bool "Write-back" | |
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263 | |
264 | config CACHE_WRITETHROUGH | |
265 | bool "Write-through" | |
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266 | help |
267 | Selecting this option will configure the caches in write-through | |
268 | mode, as opposed to the default write-back configuration. | |
269 | ||
270 | Since there's sill some aliasing issues on SH-4, this option will | |
271 | unfortunately still require the majority of flushing functions to | |
272 | be implemented to deal with aliasing. | |
273 | ||
274 | If unsure, say N. | |
275 | ||
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276 | config CACHE_OFF |
277 | bool "Off" | |
278 | ||
279 | endchoice | |
280 | ||
cad82448 | 281 | endmenu |