Commit | Line | Data |
---|---|---|
6b002230 PM |
1 | /* |
2 | * 'traps.c' handles hardware traps and faults after we have saved some | |
3 | * state in 'entry.S'. | |
1da177e4 LT |
4 | * |
5 | * SuperH version: Copyright (C) 1999 Niibe Yutaka | |
6 | * Copyright (C) 2000 Philipp Rumpf | |
7 | * Copyright (C) 2000 David Howells | |
3a2e117e | 8 | * Copyright (C) 2002 - 2007 Paul Mundt |
6b002230 PM |
9 | * |
10 | * This file is subject to the terms and conditions of the GNU General Public | |
11 | * License. See the file "COPYING" in the main directory of this archive | |
12 | * for more details. | |
1da177e4 | 13 | */ |
1da177e4 | 14 | #include <linux/kernel.h> |
1da177e4 | 15 | #include <linux/ptrace.h> |
ba84be23 | 16 | #include <linux/hardirq.h> |
1da177e4 | 17 | #include <linux/init.h> |
1da177e4 LT |
18 | #include <linux/spinlock.h> |
19 | #include <linux/module.h> | |
20 | #include <linux/kallsyms.h> | |
1f666587 | 21 | #include <linux/io.h> |
fa691511 | 22 | #include <linux/bug.h> |
9b8c90eb | 23 | #include <linux/debug_locks.h> |
b118ca57 | 24 | #include <linux/kdebug.h> |
e1132766 | 25 | #include <linux/kexec.h> |
dc34d312 | 26 | #include <linux/limits.h> |
1da177e4 LT |
27 | #include <asm/system.h> |
28 | #include <asm/uaccess.h> | |
fad0f901 | 29 | #include <asm/fpu.h> |
d39f5450 | 30 | #include <asm/kprobes.h> |
1da177e4 | 31 | |
1da177e4 | 32 | #ifdef CONFIG_CPU_SH2 |
0983b318 YS |
33 | # define TRAP_RESERVED_INST 4 |
34 | # define TRAP_ILLEGAL_SLOT_INST 6 | |
35 | # define TRAP_ADDRESS_ERROR 9 | |
36 | # ifdef CONFIG_CPU_SH2A | |
6e80f5e8 | 37 | # define TRAP_FPU_ERROR 13 |
0983b318 YS |
38 | # define TRAP_DIVZERO_ERROR 17 |
39 | # define TRAP_DIVOVF_ERROR 18 | |
40 | # endif | |
1da177e4 LT |
41 | #else |
42 | #define TRAP_RESERVED_INST 12 | |
43 | #define TRAP_ILLEGAL_SLOT_INST 13 | |
44 | #endif | |
45 | ||
6b002230 PM |
46 | static void dump_mem(const char *str, unsigned long bottom, unsigned long top) |
47 | { | |
48 | unsigned long p; | |
49 | int i; | |
50 | ||
51 | printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top); | |
52 | ||
53 | for (p = bottom & ~31; p < top; ) { | |
54 | printk("%04lx: ", p & 0xffff); | |
55 | ||
56 | for (i = 0; i < 8; i++, p += 4) { | |
57 | unsigned int val; | |
58 | ||
59 | if (p < bottom || p >= top) | |
60 | printk(" "); | |
61 | else { | |
62 | if (__get_user(val, (unsigned int __user *)p)) { | |
63 | printk("\n"); | |
64 | return; | |
65 | } | |
66 | printk("%08x ", val); | |
67 | } | |
68 | } | |
69 | printk("\n"); | |
70 | } | |
71 | } | |
1da177e4 | 72 | |
3a2e117e | 73 | static DEFINE_SPINLOCK(die_lock); |
1da177e4 LT |
74 | |
75 | void die(const char * str, struct pt_regs * regs, long err) | |
76 | { | |
77 | static int die_counter; | |
78 | ||
55273982 PM |
79 | oops_enter(); |
80 | ||
1da177e4 LT |
81 | console_verbose(); |
82 | spin_lock_irq(&die_lock); | |
6b002230 PM |
83 | bust_spinlocks(1); |
84 | ||
1da177e4 | 85 | printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter); |
6b002230 | 86 | |
6b002230 | 87 | print_modules(); |
1da177e4 | 88 | show_regs(regs); |
6b002230 | 89 | |
19c5870c AD |
90 | printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm, |
91 | task_pid_nr(current), task_stack_page(current) + 1); | |
6b002230 PM |
92 | |
93 | if (!user_mode(regs) || in_interrupt()) | |
94 | dump_mem("Stack: ", regs->regs[15], THREAD_SIZE + | |
b5a1bcbe | 95 | (unsigned long)task_stack_page(current)); |
6b002230 | 96 | |
c9306f0e PM |
97 | notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV); |
98 | ||
6b002230 | 99 | bust_spinlocks(0); |
bcdcd8e7 | 100 | add_taint(TAINT_DIE); |
1da177e4 | 101 | spin_unlock_irq(&die_lock); |
e1132766 PM |
102 | |
103 | if (kexec_should_crash(current)) | |
104 | crash_kexec(regs); | |
105 | ||
106 | if (in_interrupt()) | |
107 | panic("Fatal exception in interrupt"); | |
108 | ||
109 | if (panic_on_oops) | |
110 | panic("Fatal exception"); | |
111 | ||
55273982 | 112 | oops_exit(); |
1da177e4 LT |
113 | do_exit(SIGSEGV); |
114 | } | |
115 | ||
6b002230 PM |
116 | static inline void die_if_kernel(const char *str, struct pt_regs *regs, |
117 | long err) | |
1da177e4 LT |
118 | { |
119 | if (!user_mode(regs)) | |
120 | die(str, regs, err); | |
121 | } | |
122 | ||
1da177e4 LT |
123 | /* |
124 | * try and fix up kernelspace address errors | |
125 | * - userspace errors just cause EFAULT to be returned, resulting in SEGV | |
126 | * - kernel/userspace interfaces cause a jump to an appropriate handler | |
127 | * - other kernel errors are bad | |
1da177e4 | 128 | */ |
2afb447f | 129 | static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err) |
1da177e4 | 130 | { |
6b002230 | 131 | if (!user_mode(regs)) { |
1da177e4 LT |
132 | const struct exception_table_entry *fixup; |
133 | fixup = search_exception_tables(regs->pc); | |
134 | if (fixup) { | |
135 | regs->pc = fixup->fixup; | |
2afb447f | 136 | return; |
1da177e4 LT |
137 | } |
138 | die(str, regs, err); | |
139 | } | |
1da177e4 LT |
140 | } |
141 | ||
86c0179c MD |
142 | static inline void sign_extend(unsigned int count, unsigned char *dst) |
143 | { | |
144 | #ifdef __LITTLE_ENDIAN__ | |
4252c659 MD |
145 | if ((count == 1) && dst[0] & 0x80) { |
146 | dst[1] = 0xff; | |
147 | dst[2] = 0xff; | |
148 | dst[3] = 0xff; | |
149 | } | |
86c0179c MD |
150 | if ((count == 2) && dst[1] & 0x80) { |
151 | dst[2] = 0xff; | |
152 | dst[3] = 0xff; | |
153 | } | |
154 | #else | |
4252c659 MD |
155 | if ((count == 1) && dst[3] & 0x80) { |
156 | dst[2] = 0xff; | |
157 | dst[1] = 0xff; | |
86c0179c | 158 | dst[0] = 0xff; |
4252c659 MD |
159 | } |
160 | if ((count == 2) && dst[2] & 0x80) { | |
86c0179c | 161 | dst[1] = 0xff; |
4252c659 | 162 | dst[0] = 0xff; |
86c0179c MD |
163 | } |
164 | #endif | |
165 | } | |
166 | ||
e7cc9a73 MD |
167 | static struct mem_access user_mem_access = { |
168 | copy_from_user, | |
169 | copy_to_user, | |
170 | }; | |
171 | ||
1da177e4 LT |
172 | /* |
173 | * handle an instruction that does an unaligned memory access by emulating the | |
174 | * desired behaviour | |
175 | * - note that PC _may not_ point to the faulting instruction | |
176 | * (if that instruction is in a branch delay slot) | |
177 | * - return 0 if emulation okay, -EFAULT on existential error | |
178 | */ | |
e7cc9a73 MD |
179 | static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs, |
180 | struct mem_access *ma) | |
1da177e4 LT |
181 | { |
182 | int ret, index, count; | |
183 | unsigned long *rm, *rn; | |
184 | unsigned char *src, *dst; | |
fa43972f | 185 | unsigned char __user *srcu, *dstu; |
1da177e4 LT |
186 | |
187 | index = (instruction>>8)&15; /* 0x0F00 */ | |
188 | rn = ®s->regs[index]; | |
189 | ||
190 | index = (instruction>>4)&15; /* 0x00F0 */ | |
191 | rm = ®s->regs[index]; | |
192 | ||
193 | count = 1<<(instruction&3); | |
194 | ||
195 | ret = -EFAULT; | |
196 | switch (instruction>>12) { | |
197 | case 0: /* mov.[bwl] to/from memory via r0+rn */ | |
198 | if (instruction & 8) { | |
199 | /* from memory */ | |
fa43972f PM |
200 | srcu = (unsigned char __user *)*rm; |
201 | srcu += regs->regs[0]; | |
202 | dst = (unsigned char *)rn; | |
203 | *(unsigned long *)dst = 0; | |
1da177e4 | 204 | |
86c0179c | 205 | #if !defined(__LITTLE_ENDIAN__) |
1da177e4 | 206 | dst += 4-count; |
86c0179c | 207 | #endif |
fa43972f | 208 | if (ma->from(dst, srcu, count)) |
1da177e4 LT |
209 | goto fetch_fault; |
210 | ||
86c0179c | 211 | sign_extend(count, dst); |
1da177e4 LT |
212 | } else { |
213 | /* to memory */ | |
fa43972f | 214 | src = (unsigned char *)rm; |
1da177e4 LT |
215 | #if !defined(__LITTLE_ENDIAN__) |
216 | src += 4-count; | |
217 | #endif | |
fa43972f PM |
218 | dstu = (unsigned char __user *)*rn; |
219 | dstu += regs->regs[0]; | |
1da177e4 | 220 | |
fa43972f | 221 | if (ma->to(dstu, src, count)) |
1da177e4 LT |
222 | goto fetch_fault; |
223 | } | |
224 | ret = 0; | |
225 | break; | |
226 | ||
227 | case 1: /* mov.l Rm,@(disp,Rn) */ | |
228 | src = (unsigned char*) rm; | |
fa43972f PM |
229 | dstu = (unsigned char __user *)*rn; |
230 | dstu += (instruction&0x000F)<<2; | |
1da177e4 | 231 | |
fa43972f | 232 | if (ma->to(dstu, src, 4)) |
1da177e4 LT |
233 | goto fetch_fault; |
234 | ret = 0; | |
b5a1bcbe | 235 | break; |
1da177e4 LT |
236 | |
237 | case 2: /* mov.[bwl] to memory, possibly with pre-decrement */ | |
238 | if (instruction & 4) | |
239 | *rn -= count; | |
240 | src = (unsigned char*) rm; | |
fa43972f | 241 | dstu = (unsigned char __user *)*rn; |
1da177e4 LT |
242 | #if !defined(__LITTLE_ENDIAN__) |
243 | src += 4-count; | |
244 | #endif | |
fa43972f | 245 | if (ma->to(dstu, src, count)) |
1da177e4 LT |
246 | goto fetch_fault; |
247 | ret = 0; | |
248 | break; | |
249 | ||
250 | case 5: /* mov.l @(disp,Rm),Rn */ | |
fa43972f PM |
251 | srcu = (unsigned char __user *)*rm; |
252 | srcu += (instruction & 0x000F) << 2; | |
253 | dst = (unsigned char *)rn; | |
254 | *(unsigned long *)dst = 0; | |
1da177e4 | 255 | |
fa43972f | 256 | if (ma->from(dst, srcu, 4)) |
1da177e4 LT |
257 | goto fetch_fault; |
258 | ret = 0; | |
b5a1bcbe | 259 | break; |
1da177e4 LT |
260 | |
261 | case 6: /* mov.[bwl] from memory, possibly with post-increment */ | |
fa43972f | 262 | srcu = (unsigned char __user *)*rm; |
1da177e4 LT |
263 | if (instruction & 4) |
264 | *rm += count; | |
265 | dst = (unsigned char*) rn; | |
266 | *(unsigned long*)dst = 0; | |
b5a1bcbe | 267 | |
86c0179c | 268 | #if !defined(__LITTLE_ENDIAN__) |
1da177e4 | 269 | dst += 4-count; |
86c0179c | 270 | #endif |
fa43972f | 271 | if (ma->from(dst, srcu, count)) |
1da177e4 | 272 | goto fetch_fault; |
86c0179c | 273 | sign_extend(count, dst); |
1da177e4 LT |
274 | ret = 0; |
275 | break; | |
276 | ||
277 | case 8: | |
278 | switch ((instruction&0xFF00)>>8) { | |
279 | case 0x81: /* mov.w R0,@(disp,Rn) */ | |
fa43972f | 280 | src = (unsigned char *) ®s->regs[0]; |
1da177e4 LT |
281 | #if !defined(__LITTLE_ENDIAN__) |
282 | src += 2; | |
283 | #endif | |
fa43972f PM |
284 | dstu = (unsigned char __user *)*rm; /* called Rn in the spec */ |
285 | dstu += (instruction & 0x000F) << 1; | |
1da177e4 | 286 | |
fa43972f | 287 | if (ma->to(dstu, src, 2)) |
1da177e4 LT |
288 | goto fetch_fault; |
289 | ret = 0; | |
290 | break; | |
291 | ||
292 | case 0x85: /* mov.w @(disp,Rm),R0 */ | |
fa43972f PM |
293 | srcu = (unsigned char __user *)*rm; |
294 | srcu += (instruction & 0x000F) << 1; | |
295 | dst = (unsigned char *) ®s->regs[0]; | |
296 | *(unsigned long *)dst = 0; | |
1da177e4 LT |
297 | |
298 | #if !defined(__LITTLE_ENDIAN__) | |
299 | dst += 2; | |
300 | #endif | |
fa43972f | 301 | if (ma->from(dst, srcu, 2)) |
1da177e4 | 302 | goto fetch_fault; |
86c0179c | 303 | sign_extend(2, dst); |
1da177e4 LT |
304 | ret = 0; |
305 | break; | |
306 | } | |
307 | break; | |
308 | } | |
309 | return ret; | |
310 | ||
311 | fetch_fault: | |
312 | /* Argh. Address not only misaligned but also non-existent. | |
313 | * Raise an EFAULT and see if it's trapped | |
314 | */ | |
2afb447f ST |
315 | die_if_no_fixup("Fault in unaligned fixup", regs, 0); |
316 | return -EFAULT; | |
1da177e4 LT |
317 | } |
318 | ||
319 | /* | |
320 | * emulate the instruction in the delay slot | |
321 | * - fetches the instruction from PC+2 | |
322 | */ | |
e7cc9a73 MD |
323 | static inline int handle_delayslot(struct pt_regs *regs, |
324 | opcode_t old_instruction, | |
325 | struct mem_access *ma) | |
1da177e4 | 326 | { |
4b5a9ef5 | 327 | opcode_t instruction; |
fa43972f PM |
328 | void __user *addr = (void __user *)(regs->pc + |
329 | instruction_size(old_instruction)); | |
1da177e4 | 330 | |
4b5a9ef5 | 331 | if (copy_from_user(&instruction, addr, sizeof(instruction))) { |
1da177e4 LT |
332 | /* the instruction-fetch faulted */ |
333 | if (user_mode(regs)) | |
334 | return -EFAULT; | |
335 | ||
336 | /* kernel */ | |
b5a1bcbe SM |
337 | die("delay-slot-insn faulting in handle_unaligned_delayslot", |
338 | regs, 0); | |
1da177e4 LT |
339 | } |
340 | ||
e7cc9a73 | 341 | return handle_unaligned_ins(instruction, regs, ma); |
1da177e4 LT |
342 | } |
343 | ||
344 | /* | |
345 | * handle an instruction that does an unaligned memory access | |
346 | * - have to be careful of branch delay-slot instructions that fault | |
347 | * SH3: | |
348 | * - if the branch would be taken PC points to the branch | |
349 | * - if the branch would not be taken, PC points to delay-slot | |
350 | * SH4: | |
351 | * - PC always points to delayed branch | |
352 | * - return 0 if handled, -EFAULT if failed (may not return if in kernel) | |
353 | */ | |
354 | ||
355 | /* Macros to determine offset from current PC for branch instructions */ | |
356 | /* Explicit type coercion is used to force sign extension where needed */ | |
357 | #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4) | |
358 | #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4) | |
359 | ||
710ee0cc PM |
360 | /* |
361 | * XXX: SH-2A needs this too, but it needs an overhaul thanks to mixed 32-bit | |
362 | * opcodes.. | |
363 | */ | |
4b5a9ef5 | 364 | |
710ee0cc PM |
365 | static int handle_unaligned_notify_count = 10; |
366 | ||
e7cc9a73 MD |
367 | int handle_unaligned_access(opcode_t instruction, struct pt_regs *regs, |
368 | struct mem_access *ma) | |
1da177e4 LT |
369 | { |
370 | u_int rm; | |
371 | int ret, index; | |
372 | ||
373 | index = (instruction>>8)&15; /* 0x0F00 */ | |
374 | rm = regs->regs[index]; | |
375 | ||
376 | /* shout about the first ten userspace fixups */ | |
377 | if (user_mode(regs) && handle_unaligned_notify_count>0) { | |
378 | handle_unaligned_notify_count--; | |
379 | ||
b5a1bcbe SM |
380 | printk(KERN_NOTICE "Fixing up unaligned userspace access " |
381 | "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n", | |
19c5870c | 382 | current->comm, task_pid_nr(current), |
4b5a9ef5 | 383 | (void *)regs->pc, instruction); |
1da177e4 LT |
384 | } |
385 | ||
386 | ret = -EFAULT; | |
387 | switch (instruction&0xF000) { | |
388 | case 0x0000: | |
389 | if (instruction==0x000B) { | |
390 | /* rts */ | |
e7cc9a73 | 391 | ret = handle_delayslot(regs, instruction, ma); |
1da177e4 LT |
392 | if (ret==0) |
393 | regs->pc = regs->pr; | |
394 | } | |
395 | else if ((instruction&0x00FF)==0x0023) { | |
396 | /* braf @Rm */ | |
e7cc9a73 | 397 | ret = handle_delayslot(regs, instruction, ma); |
1da177e4 LT |
398 | if (ret==0) |
399 | regs->pc += rm + 4; | |
400 | } | |
401 | else if ((instruction&0x00FF)==0x0003) { | |
402 | /* bsrf @Rm */ | |
e7cc9a73 | 403 | ret = handle_delayslot(regs, instruction, ma); |
1da177e4 LT |
404 | if (ret==0) { |
405 | regs->pr = regs->pc + 4; | |
406 | regs->pc += rm + 4; | |
407 | } | |
408 | } | |
409 | else { | |
410 | /* mov.[bwl] to/from memory via r0+rn */ | |
411 | goto simple; | |
412 | } | |
413 | break; | |
414 | ||
415 | case 0x1000: /* mov.l Rm,@(disp,Rn) */ | |
416 | goto simple; | |
417 | ||
418 | case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */ | |
419 | goto simple; | |
420 | ||
421 | case 0x4000: | |
422 | if ((instruction&0x00FF)==0x002B) { | |
423 | /* jmp @Rm */ | |
e7cc9a73 | 424 | ret = handle_delayslot(regs, instruction, ma); |
1da177e4 LT |
425 | if (ret==0) |
426 | regs->pc = rm; | |
427 | } | |
428 | else if ((instruction&0x00FF)==0x000B) { | |
429 | /* jsr @Rm */ | |
e7cc9a73 | 430 | ret = handle_delayslot(regs, instruction, ma); |
1da177e4 LT |
431 | if (ret==0) { |
432 | regs->pr = regs->pc + 4; | |
433 | regs->pc = rm; | |
434 | } | |
435 | } | |
436 | else { | |
437 | /* mov.[bwl] to/from memory via r0+rn */ | |
438 | goto simple; | |
439 | } | |
440 | break; | |
441 | ||
442 | case 0x5000: /* mov.l @(disp,Rm),Rn */ | |
443 | goto simple; | |
444 | ||
445 | case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */ | |
446 | goto simple; | |
447 | ||
448 | case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */ | |
449 | switch (instruction&0x0F00) { | |
450 | case 0x0100: /* mov.w R0,@(disp,Rm) */ | |
451 | goto simple; | |
452 | case 0x0500: /* mov.w @(disp,Rm),R0 */ | |
453 | goto simple; | |
454 | case 0x0B00: /* bf lab - no delayslot*/ | |
455 | break; | |
456 | case 0x0F00: /* bf/s lab */ | |
e7cc9a73 | 457 | ret = handle_delayslot(regs, instruction, ma); |
1da177e4 LT |
458 | if (ret==0) { |
459 | #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB) | |
460 | if ((regs->sr & 0x00000001) != 0) | |
461 | regs->pc += 4; /* next after slot */ | |
462 | else | |
463 | #endif | |
464 | regs->pc += SH_PC_8BIT_OFFSET(instruction); | |
465 | } | |
466 | break; | |
467 | case 0x0900: /* bt lab - no delayslot */ | |
468 | break; | |
469 | case 0x0D00: /* bt/s lab */ | |
e7cc9a73 | 470 | ret = handle_delayslot(regs, instruction, ma); |
1da177e4 LT |
471 | if (ret==0) { |
472 | #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB) | |
473 | if ((regs->sr & 0x00000001) == 0) | |
474 | regs->pc += 4; /* next after slot */ | |
475 | else | |
476 | #endif | |
477 | regs->pc += SH_PC_8BIT_OFFSET(instruction); | |
478 | } | |
479 | break; | |
480 | } | |
481 | break; | |
482 | ||
483 | case 0xA000: /* bra label */ | |
e7cc9a73 | 484 | ret = handle_delayslot(regs, instruction, ma); |
1da177e4 LT |
485 | if (ret==0) |
486 | regs->pc += SH_PC_12BIT_OFFSET(instruction); | |
487 | break; | |
488 | ||
489 | case 0xB000: /* bsr label */ | |
e7cc9a73 | 490 | ret = handle_delayslot(regs, instruction, ma); |
1da177e4 LT |
491 | if (ret==0) { |
492 | regs->pr = regs->pc + 4; | |
493 | regs->pc += SH_PC_12BIT_OFFSET(instruction); | |
494 | } | |
495 | break; | |
496 | } | |
497 | return ret; | |
498 | ||
499 | /* handle non-delay-slot instruction */ | |
500 | simple: | |
e7cc9a73 | 501 | ret = handle_unaligned_ins(instruction, regs, ma); |
1da177e4 | 502 | if (ret==0) |
53f983a9 | 503 | regs->pc += instruction_size(instruction); |
1da177e4 LT |
504 | return ret; |
505 | } | |
506 | ||
507 | /* | |
b5a1bcbe SM |
508 | * Handle various address error exceptions: |
509 | * - instruction address error: | |
510 | * misaligned PC | |
511 | * PC >= 0x80000000 in user mode | |
512 | * - data address error (read and write) | |
513 | * misaligned data access | |
514 | * access to >= 0x80000000 is user mode | |
515 | * Unfortuntaly we can't distinguish between instruction address error | |
e868d612 | 516 | * and data address errors caused by read accesses. |
1da177e4 | 517 | */ |
f0bc814c | 518 | asmlinkage void do_address_error(struct pt_regs *regs, |
1da177e4 LT |
519 | unsigned long writeaccess, |
520 | unsigned long address) | |
521 | { | |
0983b318 | 522 | unsigned long error_code = 0; |
1da177e4 | 523 | mm_segment_t oldfs; |
b5a1bcbe | 524 | siginfo_t info; |
4b5a9ef5 | 525 | opcode_t instruction; |
1da177e4 LT |
526 | int tmp; |
527 | ||
0983b318 YS |
528 | /* Intentional ifdef */ |
529 | #ifdef CONFIG_CPU_HAS_SR_RB | |
4c59e294 | 530 | error_code = lookup_exception_vector(); |
0983b318 | 531 | #endif |
1da177e4 LT |
532 | |
533 | oldfs = get_fs(); | |
534 | ||
535 | if (user_mode(regs)) { | |
b5a1bcbe SM |
536 | int si_code = BUS_ADRERR; |
537 | ||
1da177e4 | 538 | local_irq_enable(); |
1da177e4 LT |
539 | |
540 | /* bad PC is not something we can fix */ | |
b5a1bcbe SM |
541 | if (regs->pc & 1) { |
542 | si_code = BUS_ADRALN; | |
1da177e4 | 543 | goto uspace_segv; |
b5a1bcbe | 544 | } |
1da177e4 LT |
545 | |
546 | set_fs(USER_DS); | |
fa43972f | 547 | if (copy_from_user(&instruction, (void __user *)(regs->pc), |
4b5a9ef5 | 548 | sizeof(instruction))) { |
1da177e4 LT |
549 | /* Argh. Fault on the instruction itself. |
550 | This should never happen non-SMP | |
551 | */ | |
552 | set_fs(oldfs); | |
553 | goto uspace_segv; | |
554 | } | |
555 | ||
e7cc9a73 MD |
556 | tmp = handle_unaligned_access(instruction, regs, |
557 | &user_mem_access); | |
1da177e4 LT |
558 | set_fs(oldfs); |
559 | ||
560 | if (tmp==0) | |
561 | return; /* sorted */ | |
b5a1bcbe SM |
562 | uspace_segv: |
563 | printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned " | |
564 | "access (PC %lx PR %lx)\n", current->comm, regs->pc, | |
565 | regs->pr); | |
566 | ||
567 | info.si_signo = SIGBUS; | |
568 | info.si_errno = 0; | |
569 | info.si_code = si_code; | |
e08f457c | 570 | info.si_addr = (void __user *)address; |
b5a1bcbe | 571 | force_sig_info(SIGBUS, &info, current); |
1da177e4 LT |
572 | } else { |
573 | if (regs->pc & 1) | |
574 | die("unaligned program counter", regs, error_code); | |
575 | ||
576 | set_fs(KERNEL_DS); | |
fa43972f | 577 | if (copy_from_user(&instruction, (void __user *)(regs->pc), |
4b5a9ef5 | 578 | sizeof(instruction))) { |
1da177e4 LT |
579 | /* Argh. Fault on the instruction itself. |
580 | This should never happen non-SMP | |
581 | */ | |
582 | set_fs(oldfs); | |
583 | die("insn faulting in do_address_error", regs, 0); | |
584 | } | |
585 | ||
e7cc9a73 | 586 | handle_unaligned_access(instruction, regs, &user_mem_access); |
1da177e4 LT |
587 | set_fs(oldfs); |
588 | } | |
589 | } | |
590 | ||
591 | #ifdef CONFIG_SH_DSP | |
592 | /* | |
593 | * SH-DSP support gerg@snapgear.com. | |
594 | */ | |
595 | int is_dsp_inst(struct pt_regs *regs) | |
596 | { | |
882c12c4 | 597 | unsigned short inst = 0; |
1da177e4 | 598 | |
f0bc814c | 599 | /* |
1da177e4 LT |
600 | * Safe guard if DSP mode is already enabled or we're lacking |
601 | * the DSP altogether. | |
602 | */ | |
11c19656 | 603 | if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP)) |
1da177e4 LT |
604 | return 0; |
605 | ||
606 | get_user(inst, ((unsigned short *) regs->pc)); | |
607 | ||
608 | inst &= 0xf000; | |
609 | ||
610 | /* Check for any type of DSP or support instruction */ | |
611 | if ((inst == 0xf000) || (inst == 0x4000)) | |
612 | return 1; | |
613 | ||
614 | return 0; | |
615 | } | |
616 | #else | |
617 | #define is_dsp_inst(regs) (0) | |
618 | #endif /* CONFIG_SH_DSP */ | |
619 | ||
0983b318 YS |
620 | #ifdef CONFIG_CPU_SH2A |
621 | asmlinkage void do_divide_error(unsigned long r4, unsigned long r5, | |
622 | unsigned long r6, unsigned long r7, | |
f0bc814c | 623 | struct pt_regs __regs) |
0983b318 YS |
624 | { |
625 | siginfo_t info; | |
626 | ||
0983b318 YS |
627 | switch (r4) { |
628 | case TRAP_DIVZERO_ERROR: | |
629 | info.si_code = FPE_INTDIV; | |
630 | break; | |
631 | case TRAP_DIVOVF_ERROR: | |
632 | info.si_code = FPE_INTOVF; | |
633 | break; | |
634 | } | |
635 | ||
636 | force_sig_info(SIGFPE, &info, current); | |
637 | } | |
638 | #endif | |
639 | ||
4b565680 TY |
640 | asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5, |
641 | unsigned long r6, unsigned long r7, | |
f0bc814c | 642 | struct pt_regs __regs) |
4b565680 | 643 | { |
f0bc814c | 644 | struct pt_regs *regs = RELOC_HIDE(&__regs, 0); |
4b565680 TY |
645 | unsigned long error_code; |
646 | struct task_struct *tsk = current; | |
647 | ||
648 | #ifdef CONFIG_SH_FPU_EMU | |
0983b318 | 649 | unsigned short inst = 0; |
4b565680 TY |
650 | int err; |
651 | ||
f0bc814c | 652 | get_user(inst, (unsigned short*)regs->pc); |
4b565680 | 653 | |
f0bc814c | 654 | err = do_fpu_inst(inst, regs); |
4b565680 | 655 | if (!err) { |
53f983a9 | 656 | regs->pc += instruction_size(inst); |
4b565680 TY |
657 | return; |
658 | } | |
659 | /* not a FPU inst. */ | |
660 | #endif | |
661 | ||
662 | #ifdef CONFIG_SH_DSP | |
663 | /* Check if it's a DSP instruction */ | |
b5a1bcbe | 664 | if (is_dsp_inst(regs)) { |
4b565680 | 665 | /* Enable DSP mode, and restart instruction. */ |
f0bc814c | 666 | regs->sr |= SR_DSP; |
01ab1039 MT |
667 | /* Save DSP mode */ |
668 | tsk->thread.dsp_status.status |= SR_DSP; | |
4b565680 TY |
669 | return; |
670 | } | |
671 | #endif | |
672 | ||
4c59e294 | 673 | error_code = lookup_exception_vector(); |
0983b318 | 674 | |
4b565680 | 675 | local_irq_enable(); |
4b565680 | 676 | force_sig(SIGILL, tsk); |
f0bc814c | 677 | die_if_no_fixup("reserved instruction", regs, error_code); |
4b565680 TY |
678 | } |
679 | ||
680 | #ifdef CONFIG_SH_FPU_EMU | |
edfd6da0 | 681 | static int emulate_branch(unsigned short inst, struct pt_regs *regs) |
4b565680 TY |
682 | { |
683 | /* | |
684 | * bfs: 8fxx: PC+=d*2+4; | |
685 | * bts: 8dxx: PC+=d*2+4; | |
686 | * bra: axxx: PC+=D*2+4; | |
687 | * bsr: bxxx: PC+=D*2+4 after PR=PC+4; | |
688 | * braf:0x23: PC+=Rn*2+4; | |
689 | * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4; | |
690 | * jmp: 4x2b: PC=Rn; | |
691 | * jsr: 4x0b: PC=Rn after PR=PC+4; | |
692 | * rts: 000b: PC=PR; | |
693 | */ | |
edfd6da0 PM |
694 | if (((inst & 0xf000) == 0xb000) || /* bsr */ |
695 | ((inst & 0xf0ff) == 0x0003) || /* bsrf */ | |
696 | ((inst & 0xf0ff) == 0x400b)) /* jsr */ | |
697 | regs->pr = regs->pc + 4; | |
698 | ||
699 | if ((inst & 0xfd00) == 0x8d00) { /* bfs, bts */ | |
4b565680 TY |
700 | regs->pc += SH_PC_8BIT_OFFSET(inst); |
701 | return 0; | |
702 | } | |
703 | ||
edfd6da0 | 704 | if ((inst & 0xe000) == 0xa000) { /* bra, bsr */ |
4b565680 TY |
705 | regs->pc += SH_PC_12BIT_OFFSET(inst); |
706 | return 0; | |
707 | } | |
708 | ||
edfd6da0 | 709 | if ((inst & 0xf0df) == 0x0003) { /* braf, bsrf */ |
4b565680 TY |
710 | regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4; |
711 | return 0; | |
712 | } | |
713 | ||
edfd6da0 | 714 | if ((inst & 0xf0df) == 0x400b) { /* jmp, jsr */ |
4b565680 TY |
715 | regs->pc = regs->regs[(inst & 0x0f00) >> 8]; |
716 | return 0; | |
717 | } | |
718 | ||
edfd6da0 | 719 | if ((inst & 0xffff) == 0x000b) { /* rts */ |
4b565680 TY |
720 | regs->pc = regs->pr; |
721 | return 0; | |
722 | } | |
723 | ||
724 | return 1; | |
725 | } | |
726 | #endif | |
727 | ||
728 | asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5, | |
729 | unsigned long r6, unsigned long r7, | |
f0bc814c | 730 | struct pt_regs __regs) |
4b565680 | 731 | { |
f0bc814c | 732 | struct pt_regs *regs = RELOC_HIDE(&__regs, 0); |
b3d765f5 | 733 | unsigned long inst; |
4b565680 | 734 | struct task_struct *tsk = current; |
d39f5450 CS |
735 | |
736 | if (kprobe_handle_illslot(regs->pc) == 0) | |
737 | return; | |
738 | ||
4b565680 | 739 | #ifdef CONFIG_SH_FPU_EMU |
f0bc814c SM |
740 | get_user(inst, (unsigned short *)regs->pc + 1); |
741 | if (!do_fpu_inst(inst, regs)) { | |
742 | get_user(inst, (unsigned short *)regs->pc); | |
743 | if (!emulate_branch(inst, regs)) | |
4b565680 TY |
744 | return; |
745 | /* fault in branch.*/ | |
746 | } | |
747 | /* not a FPU inst. */ | |
748 | #endif | |
749 | ||
4c59e294 | 750 | inst = lookup_exception_vector(); |
0983b318 | 751 | |
4b565680 | 752 | local_irq_enable(); |
4b565680 | 753 | force_sig(SIGILL, tsk); |
b3d765f5 | 754 | die_if_no_fixup("illegal slot instruction", regs, inst); |
4b565680 | 755 | } |
1da177e4 LT |
756 | |
757 | asmlinkage void do_exception_error(unsigned long r4, unsigned long r5, | |
758 | unsigned long r6, unsigned long r7, | |
f0bc814c | 759 | struct pt_regs __regs) |
1da177e4 | 760 | { |
f0bc814c | 761 | struct pt_regs *regs = RELOC_HIDE(&__regs, 0); |
1da177e4 | 762 | long ex; |
0983b318 | 763 | |
4c59e294 | 764 | ex = lookup_exception_vector(); |
f0bc814c | 765 | die_if_kernel("exception", regs, ex); |
1da177e4 LT |
766 | } |
767 | ||
768 | #if defined(CONFIG_SH_STANDARD_BIOS) | |
769 | void *gdb_vbr_vector; | |
770 | ||
771 | static inline void __init gdb_vbr_init(void) | |
772 | { | |
773 | register unsigned long vbr; | |
774 | ||
775 | /* | |
776 | * Read the old value of the VBR register to initialise | |
777 | * the vector through which debug and BIOS traps are | |
778 | * delegated by the Linux trap handler. | |
779 | */ | |
780 | asm volatile("stc vbr, %0" : "=r" (vbr)); | |
781 | ||
782 | gdb_vbr_vector = (void *)(vbr + 0x100); | |
783 | printk("Setting GDB trap vector to 0x%08lx\n", | |
784 | (unsigned long)gdb_vbr_vector); | |
785 | } | |
786 | #endif | |
787 | ||
aba1030a | 788 | void __cpuinit per_cpu_trap_init(void) |
1da177e4 LT |
789 | { |
790 | extern void *vbr_base; | |
791 | ||
792 | #ifdef CONFIG_SH_STANDARD_BIOS | |
aba1030a PM |
793 | if (raw_smp_processor_id() == 0) |
794 | gdb_vbr_init(); | |
1da177e4 LT |
795 | #endif |
796 | ||
797 | /* NOTE: The VBR value should be at P1 | |
798 | (or P2, virtural "fixed" address space). | |
799 | It's definitely should not in physical address. */ | |
800 | ||
801 | asm volatile("ldc %0, vbr" | |
802 | : /* no output */ | |
803 | : "r" (&vbr_base) | |
804 | : "memory"); | |
805 | } | |
806 | ||
1f666587 | 807 | void *set_exception_table_vec(unsigned int vec, void *handler) |
1da177e4 LT |
808 | { |
809 | extern void *exception_handling_table[]; | |
1f666587 | 810 | void *old_handler; |
b5a1bcbe | 811 | |
1f666587 PM |
812 | old_handler = exception_handling_table[vec]; |
813 | exception_handling_table[vec] = handler; | |
814 | return old_handler; | |
815 | } | |
1da177e4 | 816 | |
1f666587 PM |
817 | void __init trap_init(void) |
818 | { | |
819 | set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst); | |
820 | set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst); | |
1da177e4 | 821 | |
4b565680 TY |
822 | #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \ |
823 | defined(CONFIG_SH_FPU_EMU) | |
824 | /* | |
825 | * For SH-4 lacking an FPU, treat floating point instructions as | |
826 | * reserved. They'll be handled in the math-emu case, or faulted on | |
827 | * otherwise. | |
828 | */ | |
1f666587 PM |
829 | set_exception_table_evt(0x800, do_reserved_inst); |
830 | set_exception_table_evt(0x820, do_illegal_slot_inst); | |
831 | #elif defined(CONFIG_SH_FPU) | |
e0a3647f | 832 | #ifdef CONFIG_CPU_SUBTYPE_SHX3 |
74d99a5e PM |
833 | set_exception_table_evt(0xd80, fpu_state_restore_trap_handler); |
834 | set_exception_table_evt(0xda0, fpu_state_restore_trap_handler); | |
e0a3647f | 835 | #else |
74d99a5e PM |
836 | set_exception_table_evt(0x800, fpu_state_restore_trap_handler); |
837 | set_exception_table_evt(0x820, fpu_state_restore_trap_handler); | |
1da177e4 | 838 | #endif |
e0a3647f | 839 | #endif |
0983b318 YS |
840 | |
841 | #ifdef CONFIG_CPU_SH2 | |
5a4f7c66 | 842 | set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler); |
0983b318 YS |
843 | #endif |
844 | #ifdef CONFIG_CPU_SH2A | |
845 | set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error); | |
846 | set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error); | |
6e80f5e8 YS |
847 | #ifdef CONFIG_SH_FPU |
848 | set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler); | |
849 | #endif | |
0983b318 | 850 | #endif |
b5a1bcbe | 851 | |
1da177e4 LT |
852 | /* Setup VBR for boot cpu */ |
853 | per_cpu_trap_init(); | |
854 | } | |
855 | ||
6b002230 PM |
856 | void show_trace(struct task_struct *tsk, unsigned long *sp, |
857 | struct pt_regs *regs) | |
1da177e4 | 858 | { |
6b002230 | 859 | unsigned long addr; |
1da177e4 | 860 | |
6b002230 PM |
861 | if (regs && user_mode(regs)) |
862 | return; | |
1da177e4 | 863 | |
75fd24c1 | 864 | printk("\nCall trace:\n"); |
1da177e4 | 865 | |
6b002230 PM |
866 | while (!kstack_end(sp)) { |
867 | addr = *sp++; | |
868 | if (kernel_text_address(addr)) | |
869 | print_ip_sym(addr); | |
1da177e4 LT |
870 | } |
871 | ||
872 | printk("\n"); | |
9b8c90eb PM |
873 | |
874 | if (!tsk) | |
875 | tsk = current; | |
876 | ||
877 | debug_show_held_locks(tsk); | |
1da177e4 LT |
878 | } |
879 | ||
6b002230 | 880 | void show_stack(struct task_struct *tsk, unsigned long *sp) |
1da177e4 | 881 | { |
6b002230 PM |
882 | unsigned long stack; |
883 | ||
884 | if (!tsk) | |
885 | tsk = current; | |
886 | if (tsk == current) | |
887 | sp = (unsigned long *)current_stack_pointer; | |
888 | else | |
889 | sp = (unsigned long *)tsk->thread.sp; | |
890 | ||
891 | stack = (unsigned long)sp; | |
892 | dump_mem("Stack: ", stack, THREAD_SIZE + | |
893 | (unsigned long)task_stack_page(tsk)); | |
894 | show_trace(tsk, sp, NULL); | |
1da177e4 LT |
895 | } |
896 | ||
897 | void dump_stack(void) | |
898 | { | |
899 | show_stack(NULL, NULL); | |
900 | } | |
901 | EXPORT_SYMBOL(dump_stack); |