Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * arch/sh/kernel/smp.c | |
3 | * | |
4 | * SMP support for the SuperH processors. | |
5 | * | |
173a44dd | 6 | * Copyright (C) 2002 - 2008 Paul Mundt |
aba1030a | 7 | * Copyright (C) 2006 - 2007 Akio Idehara |
1da177e4 | 8 | * |
aba1030a PM |
9 | * This file is subject to the terms and conditions of the GNU General Public |
10 | * License. See the file "COPYING" in the main directory of this archive | |
11 | * for more details. | |
1da177e4 | 12 | */ |
66c5227e | 13 | #include <linux/err.h> |
1da177e4 LT |
14 | #include <linux/cache.h> |
15 | #include <linux/cpumask.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/init.h> | |
1da177e4 | 18 | #include <linux/spinlock.h> |
aba1030a | 19 | #include <linux/mm.h> |
1da177e4 | 20 | #include <linux/module.h> |
b56050ae | 21 | #include <linux/cpu.h> |
aba1030a | 22 | #include <linux/interrupt.h> |
1da177e4 LT |
23 | #include <asm/atomic.h> |
24 | #include <asm/processor.h> | |
25 | #include <asm/system.h> | |
26 | #include <asm/mmu_context.h> | |
27 | #include <asm/smp.h> | |
aba1030a PM |
28 | #include <asm/cacheflush.h> |
29 | #include <asm/sections.h> | |
1da177e4 | 30 | |
aba1030a PM |
31 | int __cpu_number_map[NR_CPUS]; /* Map physical to logical */ |
32 | int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */ | |
1da177e4 | 33 | |
1da177e4 LT |
34 | static inline void __init smp_store_cpu_info(unsigned int cpu) |
35 | { | |
aba1030a PM |
36 | struct sh_cpuinfo *c = cpu_data + cpu; |
37 | ||
a66c2ede PM |
38 | memcpy(c, &boot_cpu_data, sizeof(struct sh_cpuinfo)); |
39 | ||
aba1030a | 40 | c->loops_per_jiffy = loops_per_jiffy; |
1da177e4 LT |
41 | } |
42 | ||
43 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
44 | { | |
45 | unsigned int cpu = smp_processor_id(); | |
1da177e4 | 46 | |
aba1030a PM |
47 | init_new_context(current, &init_mm); |
48 | current_thread_info()->cpu = cpu; | |
49 | plat_prepare_cpus(max_cpus); | |
50 | ||
51 | #ifndef CONFIG_HOTPLUG_CPU | |
e09377ba | 52 | init_cpu_present(&cpu_possible_map); |
aba1030a | 53 | #endif |
1da177e4 LT |
54 | } |
55 | ||
56 | void __devinit smp_prepare_boot_cpu(void) | |
57 | { | |
58 | unsigned int cpu = smp_processor_id(); | |
59 | ||
aba1030a PM |
60 | __cpu_number_map[0] = cpu; |
61 | __cpu_logical_map[0] = cpu; | |
62 | ||
e09377ba RR |
63 | set_cpu_online(cpu, true); |
64 | set_cpu_possible(cpu, true); | |
1da177e4 LT |
65 | } |
66 | ||
aba1030a | 67 | asmlinkage void __cpuinit start_secondary(void) |
1da177e4 | 68 | { |
aba1030a PM |
69 | unsigned int cpu; |
70 | struct mm_struct *mm = &init_mm; | |
1da177e4 | 71 | |
4bea3418 | 72 | enable_mmu(); |
aba1030a PM |
73 | atomic_inc(&mm->mm_count); |
74 | atomic_inc(&mm->mm_users); | |
75 | current->active_mm = mm; | |
76 | BUG_ON(current->mm); | |
77 | enter_lazy_tlb(mm, current); | |
78 | ||
79 | per_cpu_trap_init(); | |
80 | ||
81 | preempt_disable(); | |
82 | ||
e545a614 MS |
83 | notify_cpu_starting(smp_processor_id()); |
84 | ||
aba1030a | 85 | local_irq_enable(); |
1da177e4 | 86 | |
8c24594d PM |
87 | cpu = smp_processor_id(); |
88 | ||
89 | /* Enable local timers */ | |
90 | local_timer_setup(cpu); | |
aba1030a PM |
91 | calibrate_delay(); |
92 | ||
aba1030a | 93 | smp_store_cpu_info(cpu); |
1da177e4 LT |
94 | |
95 | cpu_set(cpu, cpu_online_map); | |
96 | ||
aba1030a | 97 | cpu_idle(); |
1da177e4 LT |
98 | } |
99 | ||
aba1030a PM |
100 | extern struct { |
101 | unsigned long sp; | |
102 | unsigned long bss_start; | |
103 | unsigned long bss_end; | |
104 | void *start_kernel_fn; | |
105 | void *cpu_init_fn; | |
106 | void *thread_info; | |
107 | } stack_start; | |
108 | ||
109 | int __cpuinit __cpu_up(unsigned int cpu) | |
1da177e4 | 110 | { |
aba1030a PM |
111 | struct task_struct *tsk; |
112 | unsigned long timeout; | |
5bfb5d69 | 113 | |
aba1030a PM |
114 | tsk = fork_idle(cpu); |
115 | if (IS_ERR(tsk)) { | |
116 | printk(KERN_ERR "Failed forking idle task for cpu %d\n", cpu); | |
117 | return PTR_ERR(tsk); | |
118 | } | |
1da177e4 | 119 | |
aba1030a PM |
120 | /* Fill in data in head.S for secondary cpus */ |
121 | stack_start.sp = tsk->thread.sp; | |
122 | stack_start.thread_info = tsk->stack; | |
123 | stack_start.bss_start = 0; /* don't clear bss for secondary cpus */ | |
124 | stack_start.start_kernel_fn = start_secondary; | |
1da177e4 | 125 | |
d780613a PM |
126 | flush_icache_range((unsigned long)&stack_start, |
127 | (unsigned long)&stack_start + sizeof(stack_start)); | |
128 | wmb(); | |
1da177e4 | 129 | |
aba1030a | 130 | plat_start_cpu(cpu, (unsigned long)_stext); |
1da177e4 | 131 | |
aba1030a PM |
132 | timeout = jiffies + HZ; |
133 | while (time_before(jiffies, timeout)) { | |
134 | if (cpu_online(cpu)) | |
135 | break; | |
136 | ||
137 | udelay(10); | |
138 | } | |
139 | ||
140 | if (cpu_online(cpu)) | |
141 | return 0; | |
142 | ||
143 | return -ENOENT; | |
1da177e4 LT |
144 | } |
145 | ||
146 | void __init smp_cpus_done(unsigned int max_cpus) | |
147 | { | |
aba1030a PM |
148 | unsigned long bogosum = 0; |
149 | int cpu; | |
150 | ||
151 | for_each_online_cpu(cpu) | |
152 | bogosum += cpu_data[cpu].loops_per_jiffy; | |
153 | ||
154 | printk(KERN_INFO "SMP: Total of %d processors activated " | |
155 | "(%lu.%02lu BogoMIPS).\n", num_online_cpus(), | |
156 | bogosum / (500000/HZ), | |
157 | (bogosum / (5000/HZ)) % 100); | |
1da177e4 LT |
158 | } |
159 | ||
160 | void smp_send_reschedule(int cpu) | |
161 | { | |
aba1030a | 162 | plat_send_ipi(cpu, SMP_MSG_RESCHEDULE); |
1da177e4 LT |
163 | } |
164 | ||
1da177e4 LT |
165 | void smp_send_stop(void) |
166 | { | |
8691e5a8 | 167 | smp_call_function(stop_this_cpu, 0, 0); |
1da177e4 LT |
168 | } |
169 | ||
819807df | 170 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
1da177e4 | 171 | { |
490f5de5 | 172 | int cpu; |
1da177e4 | 173 | |
819807df | 174 | for_each_cpu(cpu, mask) |
490f5de5 JA |
175 | plat_send_ipi(cpu, SMP_MSG_FUNCTION); |
176 | } | |
1da177e4 | 177 | |
490f5de5 JA |
178 | void arch_send_call_function_single_ipi(int cpu) |
179 | { | |
180 | plat_send_ipi(cpu, SMP_MSG_FUNCTION_SINGLE); | |
1da177e4 LT |
181 | } |
182 | ||
320ab2b0 | 183 | void smp_timer_broadcast(const struct cpumask *mask) |
6f52707e PM |
184 | { |
185 | int cpu; | |
186 | ||
320ab2b0 | 187 | for_each_cpu(cpu, mask) |
6f52707e PM |
188 | plat_send_ipi(cpu, SMP_MSG_TIMER); |
189 | } | |
190 | ||
191 | static void ipi_timer(void) | |
192 | { | |
193 | irq_enter(); | |
8c24594d | 194 | local_timer_interrupt(); |
6f52707e PM |
195 | irq_exit(); |
196 | } | |
197 | ||
173a44dd PM |
198 | void smp_message_recv(unsigned int msg) |
199 | { | |
200 | switch (msg) { | |
201 | case SMP_MSG_FUNCTION: | |
202 | generic_smp_call_function_interrupt(); | |
203 | break; | |
204 | case SMP_MSG_RESCHEDULE: | |
205 | break; | |
206 | case SMP_MSG_FUNCTION_SINGLE: | |
207 | generic_smp_call_function_single_interrupt(); | |
208 | break; | |
6f52707e PM |
209 | case SMP_MSG_TIMER: |
210 | ipi_timer(); | |
211 | break; | |
173a44dd PM |
212 | default: |
213 | printk(KERN_WARNING "SMP %d: %s(): unknown IPI %d\n", | |
214 | smp_processor_id(), __func__, msg); | |
215 | break; | |
216 | } | |
217 | } | |
218 | ||
1da177e4 LT |
219 | /* Not really SMP stuff ... */ |
220 | int setup_profiling_timer(unsigned int multiplier) | |
221 | { | |
222 | return 0; | |
223 | } | |
224 | ||
9964fa8b PM |
225 | static void flush_tlb_all_ipi(void *info) |
226 | { | |
227 | local_flush_tlb_all(); | |
228 | } | |
229 | ||
230 | void flush_tlb_all(void) | |
231 | { | |
15c8b6c1 | 232 | on_each_cpu(flush_tlb_all_ipi, 0, 1); |
9964fa8b PM |
233 | } |
234 | ||
235 | static void flush_tlb_mm_ipi(void *mm) | |
236 | { | |
237 | local_flush_tlb_mm((struct mm_struct *)mm); | |
238 | } | |
239 | ||
240 | /* | |
241 | * The following tlb flush calls are invoked when old translations are | |
242 | * being torn down, or pte attributes are changing. For single threaded | |
243 | * address spaces, a new context is obtained on the current cpu, and tlb | |
244 | * context on other cpus are invalidated to force a new context allocation | |
245 | * at switch_mm time, should the mm ever be used on other cpus. For | |
246 | * multithreaded address spaces, intercpu interrupts have to be sent. | |
247 | * Another case where intercpu interrupts are required is when the target | |
248 | * mm might be active on another cpu (eg debuggers doing the flushes on | |
249 | * behalf of debugees, kswapd stealing pages from another process etc). | |
250 | * Kanoj 07/00. | |
251 | */ | |
252 | ||
253 | void flush_tlb_mm(struct mm_struct *mm) | |
254 | { | |
255 | preempt_disable(); | |
256 | ||
257 | if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { | |
8691e5a8 | 258 | smp_call_function(flush_tlb_mm_ipi, (void *)mm, 1); |
9964fa8b PM |
259 | } else { |
260 | int i; | |
261 | for (i = 0; i < num_online_cpus(); i++) | |
262 | if (smp_processor_id() != i) | |
263 | cpu_context(i, mm) = 0; | |
264 | } | |
265 | local_flush_tlb_mm(mm); | |
266 | ||
267 | preempt_enable(); | |
268 | } | |
269 | ||
270 | struct flush_tlb_data { | |
271 | struct vm_area_struct *vma; | |
272 | unsigned long addr1; | |
273 | unsigned long addr2; | |
274 | }; | |
275 | ||
276 | static void flush_tlb_range_ipi(void *info) | |
277 | { | |
278 | struct flush_tlb_data *fd = (struct flush_tlb_data *)info; | |
279 | ||
280 | local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2); | |
281 | } | |
282 | ||
283 | void flush_tlb_range(struct vm_area_struct *vma, | |
284 | unsigned long start, unsigned long end) | |
285 | { | |
286 | struct mm_struct *mm = vma->vm_mm; | |
287 | ||
288 | preempt_disable(); | |
289 | if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { | |
290 | struct flush_tlb_data fd; | |
291 | ||
292 | fd.vma = vma; | |
293 | fd.addr1 = start; | |
294 | fd.addr2 = end; | |
8691e5a8 | 295 | smp_call_function(flush_tlb_range_ipi, (void *)&fd, 1); |
9964fa8b PM |
296 | } else { |
297 | int i; | |
298 | for (i = 0; i < num_online_cpus(); i++) | |
299 | if (smp_processor_id() != i) | |
300 | cpu_context(i, mm) = 0; | |
301 | } | |
302 | local_flush_tlb_range(vma, start, end); | |
303 | preempt_enable(); | |
304 | } | |
305 | ||
306 | static void flush_tlb_kernel_range_ipi(void *info) | |
307 | { | |
308 | struct flush_tlb_data *fd = (struct flush_tlb_data *)info; | |
309 | ||
310 | local_flush_tlb_kernel_range(fd->addr1, fd->addr2); | |
311 | } | |
312 | ||
313 | void flush_tlb_kernel_range(unsigned long start, unsigned long end) | |
314 | { | |
315 | struct flush_tlb_data fd; | |
316 | ||
317 | fd.addr1 = start; | |
318 | fd.addr2 = end; | |
15c8b6c1 | 319 | on_each_cpu(flush_tlb_kernel_range_ipi, (void *)&fd, 1); |
9964fa8b PM |
320 | } |
321 | ||
322 | static void flush_tlb_page_ipi(void *info) | |
323 | { | |
324 | struct flush_tlb_data *fd = (struct flush_tlb_data *)info; | |
325 | ||
326 | local_flush_tlb_page(fd->vma, fd->addr1); | |
327 | } | |
328 | ||
329 | void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) | |
330 | { | |
331 | preempt_disable(); | |
332 | if ((atomic_read(&vma->vm_mm->mm_users) != 1) || | |
333 | (current->mm != vma->vm_mm)) { | |
334 | struct flush_tlb_data fd; | |
335 | ||
336 | fd.vma = vma; | |
337 | fd.addr1 = page; | |
8691e5a8 | 338 | smp_call_function(flush_tlb_page_ipi, (void *)&fd, 1); |
9964fa8b PM |
339 | } else { |
340 | int i; | |
341 | for (i = 0; i < num_online_cpus(); i++) | |
342 | if (smp_processor_id() != i) | |
343 | cpu_context(i, vma->vm_mm) = 0; | |
344 | } | |
345 | local_flush_tlb_page(vma, page); | |
346 | preempt_enable(); | |
347 | } | |
348 | ||
349 | static void flush_tlb_one_ipi(void *info) | |
350 | { | |
351 | struct flush_tlb_data *fd = (struct flush_tlb_data *)info; | |
352 | local_flush_tlb_one(fd->addr1, fd->addr2); | |
353 | } | |
354 | ||
355 | void flush_tlb_one(unsigned long asid, unsigned long vaddr) | |
356 | { | |
357 | struct flush_tlb_data fd; | |
358 | ||
359 | fd.addr1 = asid; | |
360 | fd.addr2 = vaddr; | |
361 | ||
8691e5a8 | 362 | smp_call_function(flush_tlb_one_ipi, (void *)&fd, 1); |
9964fa8b PM |
363 | local_flush_tlb_one(asid, vaddr); |
364 | } |