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1da177e4 LT |
1 | /* |
2 | * arch/sh/kernel/early_printk.c | |
3 | * | |
4 | * Copyright (C) 1999, 2000 Niibe Yutaka | |
5 | * Copyright (C) 2002 M. R. Brown | |
a80fd21e | 6 | * Copyright (C) 2004 - 2006 Paul Mundt |
1da177e4 LT |
7 | * |
8 | * This file is subject to the terms and conditions of the GNU General Public | |
9 | * License. See the file "COPYING" in the main directory of this archive | |
10 | * for more details. | |
11 | */ | |
12 | #include <linux/console.h> | |
13 | #include <linux/tty.h> | |
14 | #include <linux/init.h> | |
6fc21b82 | 15 | #include <linux/io.h> |
3ea6bc3d | 16 | #include <linux/delay.h> |
1da177e4 LT |
17 | |
18 | #ifdef CONFIG_SH_STANDARD_BIOS | |
19 | #include <asm/sh_bios.h> | |
20 | ||
21 | /* | |
22 | * Print a string through the BIOS | |
23 | */ | |
24 | static void sh_console_write(struct console *co, const char *s, | |
25 | unsigned count) | |
26 | { | |
27 | sh_bios_console_write(s, count); | |
28 | } | |
29 | ||
30 | /* | |
31 | * Setup initial baud/bits/parity. We do two things here: | |
32 | * - construct a cflag setting for the first rs_open() | |
33 | * - initialize the serial port | |
34 | * Return non-zero if we didn't find a serial port. | |
35 | */ | |
36 | static int __init sh_console_setup(struct console *co, char *options) | |
37 | { | |
38 | int cflag = CREAD | HUPCL | CLOCAL; | |
39 | ||
40 | /* | |
41 | * Now construct a cflag setting. | |
42 | * TODO: this is a totally bogus cflag, as we have | |
43 | * no idea what serial settings the BIOS is using, or | |
44 | * even if its using the serial port at all. | |
45 | */ | |
46 | cflag |= B115200 | CS8 | /*no parity*/0; | |
47 | ||
48 | co->cflag = cflag; | |
49 | ||
50 | return 0; | |
51 | } | |
52 | ||
a80fd21e | 53 | static struct console bios_console = { |
1da177e4 LT |
54 | .name = "bios", |
55 | .write = sh_console_write, | |
56 | .setup = sh_console_setup, | |
57 | .flags = CON_PRINTBUFFER, | |
58 | .index = -1, | |
59 | }; | |
60 | #endif | |
61 | ||
62 | #ifdef CONFIG_EARLY_SCIF_CONSOLE | |
a80fd21e PM |
63 | #include <linux/serial_core.h> |
64 | #include "../../../drivers/serial/sh-sci.h" | |
65 | ||
3ea6bc3d MB |
66 | #if defined(CONFIG_CPU_SUBTYPE_SH7720) |
67 | #define EPK_SCSMR_VALUE 0x000 | |
68 | #define EPK_SCBRR_VALUE 0x00C | |
69 | #define EPK_FIFO_SIZE 64 | |
70 | #define EPK_FIFO_BITS (0x7f00 >> 8) | |
71 | #else | |
72 | #define EPK_FIFO_SIZE 16 | |
73 | #define EPK_FIFO_BITS (0x1f00 >> 8) | |
74 | #endif | |
75 | ||
76 | ||
77 | ||
a80fd21e | 78 | static struct uart_port scif_port = { |
6fc21b82 PM |
79 | .mapbase = CONFIG_EARLY_SCIF_CONSOLE_PORT, |
80 | .membase = (char __iomem *)CONFIG_EARLY_SCIF_CONSOLE_PORT, | |
a80fd21e | 81 | }; |
1da177e4 LT |
82 | |
83 | static void scif_sercon_putc(int c) | |
84 | { | |
3ea6bc3d | 85 | while (((sci_in(&scif_port, SCFDR) & EPK_FIFO_BITS) >= EPK_FIFO_SIZE)) |
a80fd21e | 86 | ; |
1da177e4 | 87 | |
a80fd21e PM |
88 | sci_out(&scif_port, SCxTDR, c); |
89 | sci_in(&scif_port, SCxSR); | |
90 | sci_out(&scif_port, SCxSR, 0xf3 & ~(0x20 | 0x40)); | |
91 | ||
96989d9d | 92 | while ((sci_in(&scif_port, SCxSR) & 0x40) == 0) |
a80fd21e | 93 | ; |
1da177e4 LT |
94 | |
95 | if (c == '\n') | |
96 | scif_sercon_putc('\r'); | |
97 | } | |
98 | ||
a80fd21e PM |
99 | static void scif_sercon_write(struct console *con, const char *s, |
100 | unsigned count) | |
1da177e4 LT |
101 | { |
102 | while (count-- > 0) | |
103 | scif_sercon_putc(*s++); | |
1da177e4 LT |
104 | } |
105 | ||
106 | static int __init scif_sercon_setup(struct console *con, char *options) | |
107 | { | |
108 | con->cflag = CREAD | HUPCL | CLOCAL | B115200 | CS8; | |
109 | ||
110 | return 0; | |
111 | } | |
112 | ||
a80fd21e | 113 | static struct console scif_console = { |
1da177e4 LT |
114 | .name = "sercon", |
115 | .write = scif_sercon_write, | |
116 | .setup = scif_sercon_setup, | |
117 | .flags = CON_PRINTBUFFER, | |
118 | .index = -1, | |
119 | }; | |
120 | ||
3ea6bc3d MB |
121 | #if !defined(CONFIG_SH_STANDARD_BIOS) |
122 | #if defined(CONFIG_CPU_SUBTYPE_SH7720) | |
123 | static void scif_sercon_init(char *s) | |
124 | { | |
125 | sci_out(&scif_port, SCSCR, 0x0000); /* clear TE and RE */ | |
126 | sci_out(&scif_port, SCFCR, 0x4006); /* reset */ | |
127 | sci_out(&scif_port, SCSCR, 0x0000); /* select internal clock */ | |
128 | sci_out(&scif_port, SCSMR, EPK_SCSMR_VALUE); | |
129 | sci_out(&scif_port, SCBRR, EPK_SCBRR_VALUE); | |
130 | ||
131 | mdelay(1); /* wait 1-bit time */ | |
132 | ||
133 | sci_out(&scif_port, SCFCR, 0x0030); /* TTRG=b'11 */ | |
134 | sci_out(&scif_port, SCSCR, 0x0030); /* TE, RE */ | |
135 | } | |
136 | #elif defined(CONFIG_CPU_SH4) | |
703404ea | 137 | #define DEFAULT_BAUD 115200 |
6fc21b82 PM |
138 | /* |
139 | * Simple SCIF init, primarily aimed at SH7750 and other similar SH-4 | |
140 | * devices that aren't using sh-ipl+g. | |
141 | */ | |
703404ea | 142 | static void scif_sercon_init(char *s) |
1da177e4 | 143 | { |
703404ea JL |
144 | unsigned baud = DEFAULT_BAUD; |
145 | char *e; | |
146 | ||
147 | if (*s == ',') | |
148 | ++s; | |
149 | ||
150 | if (*s) { | |
151 | /* ignore ioport/device name */ | |
152 | s += strcspn(s, ","); | |
153 | if (*s == ',') | |
154 | s++; | |
155 | } | |
156 | ||
157 | if (*s) { | |
158 | baud = simple_strtoul(s, &e, 0); | |
159 | if (baud == 0 || s == e) | |
160 | baud = DEFAULT_BAUD; | |
161 | } | |
162 | ||
6fc21b82 PM |
163 | ctrl_outw(0, scif_port.mapbase + 8); |
164 | ctrl_outw(0, scif_port.mapbase); | |
1da177e4 LT |
165 | |
166 | /* Set baud rate */ | |
167 | ctrl_outb((CONFIG_SH_PCLK_FREQ + 16 * baud) / | |
6fc21b82 PM |
168 | (32 * baud) - 1, scif_port.mapbase + 4); |
169 | ||
170 | ctrl_outw(12, scif_port.mapbase + 24); | |
171 | ctrl_outw(8, scif_port.mapbase + 24); | |
172 | ctrl_outw(0, scif_port.mapbase + 32); | |
173 | ctrl_outw(0x60, scif_port.mapbase + 16); | |
174 | ctrl_outw(0, scif_port.mapbase + 36); | |
175 | ctrl_outw(0x30, scif_port.mapbase + 8); | |
1da177e4 | 176 | } |
3ea6bc3d MB |
177 | #endif /* defined(CONFIG_CPU_SUBTYPE_SH7720) */ |
178 | #endif /* !defined(CONFIG_SH_STANDARD_BIOS) */ | |
6fc21b82 | 179 | #endif /* CONFIG_EARLY_SCIF_CONSOLE */ |
1da177e4 | 180 | |
a80fd21e PM |
181 | /* |
182 | * Setup a default console, if more than one is compiled in, rely on the | |
183 | * earlyprintk= parsing to give priority. | |
184 | */ | |
185 | static struct console *early_console = | |
186 | #ifdef CONFIG_SH_STANDARD_BIOS | |
187 | &bios_console | |
188 | #elif defined(CONFIG_EARLY_SCIF_CONSOLE) | |
189 | &scif_console | |
190 | #else | |
191 | NULL | |
192 | #endif | |
193 | ; | |
194 | ||
195 | static int __initdata keep_early; | |
b641fe01 | 196 | static int early_console_initialized; |
a80fd21e | 197 | |
b641fe01 | 198 | int __init setup_early_printk(char *buf) |
1da177e4 | 199 | { |
b641fe01 PM |
200 | if (!buf) |
201 | return 0; | |
a80fd21e | 202 | |
b641fe01 PM |
203 | if (early_console_initialized) |
204 | return 0; | |
205 | early_console_initialized = 1; | |
a80fd21e PM |
206 | |
207 | if (strstr(buf, "keep")) | |
208 | keep_early = 1; | |
209 | ||
210 | #ifdef CONFIG_SH_STANDARD_BIOS | |
211 | if (!strncmp(buf, "bios", 4)) | |
212 | early_console = &bios_console; | |
213 | #endif | |
214 | #if defined(CONFIG_EARLY_SCIF_CONSOLE) | |
215 | if (!strncmp(buf, "serial", 6)) { | |
216 | early_console = &scif_console; | |
217 | ||
3ea6bc3d MB |
218 | #if (defined(CONFIG_CPU_SH4) || defined(CONFIG_CPU_SUBTYPE_SH7720)) && \ |
219 | !defined(CONFIG_SH_STANDARD_BIOS) | |
703404ea | 220 | scif_sercon_init(buf + 6); |
a80fd21e PM |
221 | #endif |
222 | } | |
1da177e4 | 223 | #endif |
a80fd21e | 224 | |
69331af7 GH |
225 | if (likely(early_console)) { |
226 | if (keep_early) | |
227 | early_console->flags &= ~CON_BOOT; | |
228 | else | |
229 | early_console->flags |= CON_BOOT; | |
a80fd21e | 230 | register_console(early_console); |
69331af7 | 231 | } |
a80fd21e | 232 | |
b641fe01 | 233 | return 0; |
1da177e4 | 234 | } |
b641fe01 | 235 | early_param("earlyprintk", setup_early_printk); |