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1 | /* |
2 | * SH5-101/SH5-103 CPU Setup | |
3 | * | |
4 | * Copyright (C) 2009 Paul Mundt | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
10 | #include <linux/platform_device.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/serial.h> | |
13 | #include <linux/serial_sci.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/mm.h> | |
add47067 | 16 | #include <linux/sh_timer.h> |
0fb849b9 PM |
17 | #include <asm/addrspace.h> |
18 | ||
19 | static struct plat_sci_port sci_platform_data[] = { | |
20 | { | |
21 | .mapbase = PHYS_PERIPHERAL_BLOCK + 0x01030000, | |
22 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, | |
23 | .type = PORT_SCIF, | |
24 | .irqs = { 39, 40, 42, 0 }, | |
25 | }, { | |
26 | .flags = 0, | |
27 | } | |
28 | }; | |
29 | ||
30 | static struct platform_device sci_device = { | |
31 | .name = "sh-sci", | |
32 | .id = -1, | |
33 | .dev = { | |
34 | .platform_data = sci_platform_data, | |
35 | }, | |
36 | }; | |
37 | ||
c2ecb4c4 PM |
38 | static struct resource rtc_resources[] = { |
39 | [0] = { | |
40 | .start = PHYS_PERIPHERAL_BLOCK + 0x01040000, | |
41 | .end = PHYS_PERIPHERAL_BLOCK + 0x01040000 + 0x58 - 1, | |
42 | .flags = IORESOURCE_IO, | |
43 | }, | |
44 | [1] = { | |
45 | /* Period IRQ */ | |
46 | .start = IRQ_PRI, | |
47 | .flags = IORESOURCE_IRQ, | |
48 | }, | |
49 | [2] = { | |
50 | /* Carry IRQ */ | |
51 | .start = IRQ_CUI, | |
52 | .flags = IORESOURCE_IRQ, | |
53 | }, | |
54 | [3] = { | |
55 | /* Alarm IRQ */ | |
56 | .start = IRQ_ATI, | |
57 | .flags = IORESOURCE_IRQ, | |
58 | }, | |
59 | }; | |
60 | ||
61 | static struct platform_device rtc_device = { | |
62 | .name = "sh-rtc", | |
63 | .id = -1, | |
64 | .num_resources = ARRAY_SIZE(rtc_resources), | |
65 | .resource = rtc_resources, | |
66 | }; | |
67 | ||
add47067 PM |
68 | #define TMU_BLOCK_OFF 0x01020000 |
69 | #define TMU_BASE PHYS_PERIPHERAL_BLOCK + TMU_BLOCK_OFF | |
70 | #define TMU0_BASE (TMU_BASE + 0x8 + (0xc * 0x0)) | |
71 | #define TMU1_BASE (TMU_BASE + 0x8 + (0xc * 0x1)) | |
72 | #define TMU2_BASE (TMU_BASE + 0x8 + (0xc * 0x2)) | |
73 | ||
74 | static struct sh_timer_config tmu0_platform_data = { | |
75 | .name = "TMU0", | |
76 | .channel_offset = 0x04, | |
77 | .timer_bit = 0, | |
af777ce4 | 78 | .clk = "peripheral_clk", |
add47067 PM |
79 | .clockevent_rating = 200, |
80 | }; | |
81 | ||
82 | static struct resource tmu0_resources[] = { | |
83 | [0] = { | |
84 | .name = "TMU0", | |
85 | .start = TMU0_BASE, | |
86 | .end = TMU0_BASE + 0xc - 1, | |
87 | .flags = IORESOURCE_MEM, | |
88 | }, | |
89 | [1] = { | |
90 | .start = IRQ_TUNI0, | |
91 | .flags = IORESOURCE_IRQ, | |
92 | }, | |
93 | }; | |
94 | ||
95 | static struct platform_device tmu0_device = { | |
96 | .name = "sh_tmu", | |
97 | .id = 0, | |
98 | .dev = { | |
99 | .platform_data = &tmu0_platform_data, | |
100 | }, | |
101 | .resource = tmu0_resources, | |
102 | .num_resources = ARRAY_SIZE(tmu0_resources), | |
103 | }; | |
104 | ||
105 | static struct sh_timer_config tmu1_platform_data = { | |
106 | .name = "TMU1", | |
107 | .channel_offset = 0x10, | |
108 | .timer_bit = 1, | |
af777ce4 | 109 | .clk = "peripheral_clk", |
add47067 PM |
110 | .clocksource_rating = 200, |
111 | }; | |
112 | ||
113 | static struct resource tmu1_resources[] = { | |
114 | [0] = { | |
115 | .name = "TMU1", | |
116 | .start = TMU1_BASE, | |
117 | .end = TMU1_BASE + 0xc - 1, | |
118 | .flags = IORESOURCE_MEM, | |
119 | }, | |
120 | [1] = { | |
121 | .start = IRQ_TUNI1, | |
122 | .flags = IORESOURCE_IRQ, | |
123 | }, | |
124 | }; | |
125 | ||
126 | static struct platform_device tmu1_device = { | |
127 | .name = "sh_tmu", | |
128 | .id = 1, | |
129 | .dev = { | |
130 | .platform_data = &tmu1_platform_data, | |
131 | }, | |
132 | .resource = tmu1_resources, | |
133 | .num_resources = ARRAY_SIZE(tmu1_resources), | |
134 | }; | |
135 | ||
136 | static struct sh_timer_config tmu2_platform_data = { | |
137 | .name = "TMU2", | |
138 | .channel_offset = 0x1c, | |
139 | .timer_bit = 2, | |
af777ce4 | 140 | .clk = "peripheral_clk", |
add47067 PM |
141 | }; |
142 | ||
143 | static struct resource tmu2_resources[] = { | |
144 | [0] = { | |
145 | .name = "TMU2", | |
146 | .start = TMU2_BASE, | |
147 | .end = TMU2_BASE + 0xc - 1, | |
148 | .flags = IORESOURCE_MEM, | |
149 | }, | |
150 | [1] = { | |
151 | .start = IRQ_TUNI2, | |
152 | .flags = IORESOURCE_IRQ, | |
153 | }, | |
154 | }; | |
155 | ||
156 | static struct platform_device tmu2_device = { | |
157 | .name = "sh_tmu", | |
158 | .id = 2, | |
159 | .dev = { | |
160 | .platform_data = &tmu2_platform_data, | |
161 | }, | |
162 | .resource = tmu2_resources, | |
163 | .num_resources = ARRAY_SIZE(tmu2_resources), | |
164 | }; | |
165 | ||
166 | static struct platform_device *sh5_early_devices[] __initdata = { | |
167 | &tmu0_device, | |
168 | &tmu1_device, | |
169 | &tmu2_device, | |
170 | }; | |
171 | ||
0fb849b9 PM |
172 | static struct platform_device *sh5_devices[] __initdata = { |
173 | &sci_device, | |
c2ecb4c4 | 174 | &rtc_device, |
0fb849b9 PM |
175 | }; |
176 | ||
177 | static int __init sh5_devices_setup(void) | |
178 | { | |
add47067 PM |
179 | int ret; |
180 | ||
181 | ret = platform_add_devices(sh5_early_devices, | |
182 | ARRAY_SIZE(sh5_early_devices)); | |
183 | if (unlikely(ret != 0)) | |
184 | return ret; | |
185 | ||
0fb849b9 PM |
186 | return platform_add_devices(sh5_devices, |
187 | ARRAY_SIZE(sh5_devices)); | |
188 | } | |
189 | __initcall(sh5_devices_setup); | |
add47067 PM |
190 | |
191 | void __init plat_early_device_setup(void) | |
192 | { | |
193 | early_platform_add_devices(sh5_early_devices, | |
194 | ARRAY_SIZE(sh5_early_devices)); | |
195 | } |