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Merge branch 'topic/oss' into for-linus
[linux-2.6-block.git] / arch / sh / kernel / cpu / sh4a / setup-sh7786.c
CommitLineData
55ba99eb
KM		 1/*
2 * SH7786 Setup
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
c3d480de 6 * Paul Mundt <paul.mundt@renesas.com>
55ba99eb
KM		 7 *
8 * Based on SH7785 Setup
9 *
10 * Copyright (C) 2007 Paul Mundt
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file "COPYING" in the main directory of this archive
14 * for more details.
15 */
16#include <linux/platform_device.h>
17#include <linux/init.h>
18#include <linux/serial.h>
19#include <linux/serial_sci.h>
20#include <linux/io.h>
21#include <linux/mm.h>
4c3f450b 22#include <linux/dma-mapping.h>
c3d480de 23#include <linux/sh_timer.h>
55ba99eb
KM		 24#include <asm/mmzone.h>
25
26static struct plat_sci_port sci_platform_data[] = {
27 {
28 .mapbase = 0xffea0000,
29 .flags = UPF_BOOT_AUTOCONF,
30 .type = PORT_SCIF,
31 .irqs = { 40, 41, 43, 42 },
32 },
33 /*
34 * The rest of these all have multiplexed IRQs
35 */
36 {
37 .mapbase = 0xffeb0000,
38 .flags = UPF_BOOT_AUTOCONF,
39 .type = PORT_SCIF,
40 .irqs = { 44, 44, 44, 44 },
41 }, {
42 .mapbase = 0xffec0000,
43 .flags = UPF_BOOT_AUTOCONF,
44 .type = PORT_SCIF,
45 .irqs = { 50, 50, 50, 50 },
46 }, {
47 .mapbase = 0xffed0000,
48 .flags = UPF_BOOT_AUTOCONF,
49 .type = PORT_SCIF,
50 .irqs = { 51, 51, 51, 51 },
51 }, {
52 .mapbase = 0xffee0000,
53 .flags = UPF_BOOT_AUTOCONF,
54 .type = PORT_SCIF,
55 .irqs = { 52, 52, 52, 52 },
56 }, {
57 .mapbase = 0xffef0000,
58 .flags = UPF_BOOT_AUTOCONF,
59 .type = PORT_SCIF,
60 .irqs = { 53, 53, 53, 53 },
61 }, {
62 .flags = 0,
63 }
64};
65
66static struct platform_device sci_device = {
67 .name = "sh-sci",
68 .id = -1,
69 .dev = {
70 .platform_data = sci_platform_data,
71 },
72};
73
c3d480de
PM		 74static struct sh_timer_config tmu0_platform_data = {
75 .name = "TMU0",
76 .channel_offset = 0x04,
77 .timer_bit = 0,
af777ce4 78 .clk = "peripheral_clk",
c3d480de
PM		 79 .clockevent_rating = 200,
80};
81
82static struct resource tmu0_resources[] = {
83 [0] = {
84 .name = "TMU0",
85 .start = 0xffd80008,
86 .end = 0xffd80013,
87 .flags = IORESOURCE_MEM,
88 },
89 [1] = {
90 .start = 16,
91 .flags = IORESOURCE_IRQ,
92 },
93};
94
95static struct platform_device tmu0_device = {
96 .name = "sh_tmu",
97 .id = 0,
98 .dev = {
99 .platform_data = &tmu0_platform_data,
100 },
101 .resource = tmu0_resources,
102 .num_resources = ARRAY_SIZE(tmu0_resources),
103};
104
105static struct sh_timer_config tmu1_platform_data = {
106 .name = "TMU1",
107 .channel_offset = 0x10,
108 .timer_bit = 1,
af777ce4 109 .clk = "peripheral_clk",
c3d480de
PM		 110 .clocksource_rating = 200,
111};
112
113static struct resource tmu1_resources[] = {
114 [0] = {
115 .name = "TMU1",
116 .start = 0xffd80014,
117 .end = 0xffd8001f,
118 .flags = IORESOURCE_MEM,
119 },
120 [1] = {
121 .start = 17,
122 .flags = IORESOURCE_IRQ,
123 },
124};
125
126static struct platform_device tmu1_device = {
127 .name = "sh_tmu",
128 .id = 1,
129 .dev = {
130 .platform_data = &tmu1_platform_data,
131 },
132 .resource = tmu1_resources,
133 .num_resources = ARRAY_SIZE(tmu1_resources),
134};
135
136static struct sh_timer_config tmu2_platform_data = {
137 .name = "TMU2",
138 .channel_offset = 0x1c,
139 .timer_bit = 2,
af777ce4 140 .clk = "peripheral_clk",
c3d480de
PM		 141};
142
143static struct resource tmu2_resources[] = {
144 [0] = {
145 .name = "TMU2",
146 .start = 0xffd80020,
147 .end = 0xffd8002f,
148 .flags = IORESOURCE_MEM,
149 },
150 [1] = {
151 .start = 18,
152 .flags = IORESOURCE_IRQ,
153 },
154};
155
156static struct platform_device tmu2_device = {
157 .name = "sh_tmu",
158 .id = 2,
159 .dev = {
160 .platform_data = &tmu2_platform_data,
161 },
162 .resource = tmu2_resources,
163 .num_resources = ARRAY_SIZE(tmu2_resources),
164};
165
166static struct sh_timer_config tmu3_platform_data = {
167 .name = "TMU3",
168 .channel_offset = 0x04,
169 .timer_bit = 0,
af777ce4 170 .clk = "peripheral_clk",
c3d480de
PM		 171};
172
173static struct resource tmu3_resources[] = {
174 [0] = {
175 .name = "TMU3",
176 .start = 0xffda0008,
177 .end = 0xffda0013,
178 .flags = IORESOURCE_MEM,
179 },
180 [1] = {
181 .start = 20,
182 .flags = IORESOURCE_IRQ,
183 },
184};
185
186static struct platform_device tmu3_device = {
187 .name = "sh_tmu",
188 .id = 3,
189 .dev = {
190 .platform_data = &tmu3_platform_data,
191 },
192 .resource = tmu3_resources,
193 .num_resources = ARRAY_SIZE(tmu3_resources),
194};
195
196static struct sh_timer_config tmu4_platform_data = {
197 .name = "TMU4",
198 .channel_offset = 0x10,
199 .timer_bit = 1,
af777ce4 200 .clk = "peripheral_clk",
c3d480de
PM		 201};
202
203static struct resource tmu4_resources[] = {
204 [0] = {
205 .name = "TMU4",
206 .start = 0xffda0014,
207 .end = 0xffda001f,
208 .flags = IORESOURCE_MEM,
209 },
210 [1] = {
211 .start = 21,
212 .flags = IORESOURCE_IRQ,
213 },
214};
215
216static struct platform_device tmu4_device = {
217 .name = "sh_tmu",
218 .id = 4,
219 .dev = {
220 .platform_data = &tmu4_platform_data,
221 },
222 .resource = tmu4_resources,
223 .num_resources = ARRAY_SIZE(tmu4_resources),
224};
225
226static struct sh_timer_config tmu5_platform_data = {
227 .name = "TMU5",
228 .channel_offset = 0x1c,
229 .timer_bit = 2,
af777ce4 230 .clk = "peripheral_clk",
c3d480de
PM		 231};
232
233static struct resource tmu5_resources[] = {
234 [0] = {
235 .name = "TMU5",
236 .start = 0xffda0020,
237 .end = 0xffda002b,
238 .flags = IORESOURCE_MEM,
239 },
240 [1] = {
241 .start = 22,
242 .flags = IORESOURCE_IRQ,
243 },
244};
245
246static struct platform_device tmu5_device = {
247 .name = "sh_tmu",
248 .id = 5,
249 .dev = {
250 .platform_data = &tmu5_platform_data,
251 },
252 .resource = tmu5_resources,
253 .num_resources = ARRAY_SIZE(tmu5_resources),
254};
255
256static struct sh_timer_config tmu6_platform_data = {
257 .name = "TMU6",
258 .channel_offset = 0x04,
259 .timer_bit = 0,
af777ce4 260 .clk = "peripheral_clk",
c3d480de
PM		 261};
262
263static struct resource tmu6_resources[] = {
264 [0] = {
265 .name = "TMU6",
266 .start = 0xffdc0008,
267 .end = 0xffdc0013,
268 .flags = IORESOURCE_MEM,
269 },
270 [1] = {
271 .start = 45,
272 .flags = IORESOURCE_IRQ,
273 },
274};
275
276static struct platform_device tmu6_device = {
277 .name = "sh_tmu",
278 .id = 6,
279 .dev = {
280 .platform_data = &tmu6_platform_data,
281 },
282 .resource = tmu6_resources,
283 .num_resources = ARRAY_SIZE(tmu6_resources),
284};
285
286static struct sh_timer_config tmu7_platform_data = {
287 .name = "TMU7",
288 .channel_offset = 0x10,
289 .timer_bit = 1,
af777ce4 290 .clk = "peripheral_clk",
c3d480de
PM		 291};
292
293static struct resource tmu7_resources[] = {
294 [0] = {
295 .name = "TMU7",
296 .start = 0xffdc0014,
297 .end = 0xffdc001f,
298 .flags = IORESOURCE_MEM,
299 },
300 [1] = {
301 .start = 45,
302 .flags = IORESOURCE_IRQ,
303 },
304};
305
306static struct platform_device tmu7_device = {
307 .name = "sh_tmu",
308 .id = 7,
309 .dev = {
310 .platform_data = &tmu7_platform_data,
311 },
312 .resource = tmu7_resources,
313 .num_resources = ARRAY_SIZE(tmu7_resources),
314};
315
316static struct sh_timer_config tmu8_platform_data = {
317 .name = "TMU8",
318 .channel_offset = 0x1c,
319 .timer_bit = 2,
af777ce4 320 .clk = "peripheral_clk",
c3d480de
PM		 321};
322
323static struct resource tmu8_resources[] = {
324 [0] = {
325 .name = "TMU8",
326 .start = 0xffdc0020,
327 .end = 0xffdc002b,
328 .flags = IORESOURCE_MEM,
329 },
330 [1] = {
331 .start = 45,
332 .flags = IORESOURCE_IRQ,
333 },
334};
335
336static struct platform_device tmu8_device = {
337 .name = "sh_tmu",
338 .id = 8,
339 .dev = {
340 .platform_data = &tmu8_platform_data,
341 },
342 .resource = tmu8_resources,
343 .num_resources = ARRAY_SIZE(tmu8_resources),
344};
345
346static struct sh_timer_config tmu9_platform_data = {
347 .name = "TMU9",
348 .channel_offset = 0x04,
349 .timer_bit = 0,
af777ce4 350 .clk = "peripheral_clk",
c3d480de
PM		 351};
352
353static struct resource tmu9_resources[] = {
354 [0] = {
355 .name = "TMU9",
356 .start = 0xffde0008,
357 .end = 0xffde0013,
358 .flags = IORESOURCE_MEM,
359 },
360 [1] = {
361 .start = 46,
362 .flags = IORESOURCE_IRQ,
363 },
364};
365
366static struct platform_device tmu9_device = {
367 .name = "sh_tmu",
368 .id = 9,
369 .dev = {
370 .platform_data = &tmu9_platform_data,
371 },
372 .resource = tmu9_resources,
373 .num_resources = ARRAY_SIZE(tmu9_resources),
374};
375
376static struct sh_timer_config tmu10_platform_data = {
377 .name = "TMU10",
378 .channel_offset = 0x10,
379 .timer_bit = 1,
af777ce4 380 .clk = "peripheral_clk",
c3d480de
PM		 381};
382
383static struct resource tmu10_resources[] = {
384 [0] = {
385 .name = "TMU10",
386 .start = 0xffde0014,
387 .end = 0xffde001f,
388 .flags = IORESOURCE_MEM,
389 },
390 [1] = {
391 .start = 46,
392 .flags = IORESOURCE_IRQ,
393 },
394};
395
396static struct platform_device tmu10_device = {
397 .name = "sh_tmu",
398 .id = 10,
399 .dev = {
400 .platform_data = &tmu10_platform_data,
401 },
402 .resource = tmu10_resources,
403 .num_resources = ARRAY_SIZE(tmu10_resources),
404};
405
406static struct sh_timer_config tmu11_platform_data = {
407 .name = "TMU11",
408 .channel_offset = 0x1c,
409 .timer_bit = 2,
af777ce4 410 .clk = "peripheral_clk",
c3d480de
PM		 411};
412
413static struct resource tmu11_resources[] = {
414 [0] = {
415 .name = "TMU11",
416 .start = 0xffde0020,
417 .end = 0xffde002b,
418 .flags = IORESOURCE_MEM,
419 },
420 [1] = {
421 .start = 46,
422 .flags = IORESOURCE_IRQ,
423 },
424};
425
426static struct platform_device tmu11_device = {
427 .name = "sh_tmu",
428 .id = 11,
429 .dev = {
430 .platform_data = &tmu11_platform_data,
431 },
432 .resource = tmu11_resources,
433 .num_resources = ARRAY_SIZE(tmu11_resources),
434};
435
4c3f450b
KM		 436static struct resource usb_ohci_resources[] = {
437 [0] = {
438 .start = 0xffe70400,
439 .end = 0xffe704ff,
440 .flags = IORESOURCE_MEM,
441 },
442 [1] = {
443 .start = 77,
444 .end = 77,
445 .flags = IORESOURCE_IRQ,
446 },
447};
448
449static u64 usb_ohci_dma_mask = DMA_BIT_MASK(32);
450static struct platform_device usb_ohci_device = {
451 .name = "sh_ohci",
452 .id = -1,
453 .dev = {
454 .dma_mask = &usb_ohci_dma_mask,
455 .coherent_dma_mask = DMA_BIT_MASK(32),
456 },
457 .num_resources = ARRAY_SIZE(usb_ohci_resources),
458 .resource = usb_ohci_resources,
459};
460
c3d480de
PM		 461static struct platform_device *sh7786_early_devices[] __initdata = {
462 &tmu0_device,
463 &tmu1_device,
464 &tmu2_device,
465 &tmu3_device,
466 &tmu4_device,
467 &tmu5_device,
468 &tmu6_device,
469 &tmu7_device,
470 &tmu8_device,
471 &tmu9_device,
472 &tmu10_device,
473 &tmu11_device,
474};
475
55ba99eb
KM		 476static struct platform_device *sh7786_devices[] __initdata = {
477 &sci_device,
4c3f450b 478 &usb_ohci_device,
55ba99eb
KM		 479};
480
4c3f450b
KM		 481
482/*
483 * Please call this function if your platform board
484 * use external clock for USB
485 * */
486#define USBCTL0 0xffe70858
487#define CLOCK_MODE_MASK 0xffffff7f
488#define EXT_CLOCK_MODE 0x00000080
489void __init sh7786_usb_use_exclock(void)
490{
491 u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK;
492 __raw_writel(val | EXT_CLOCK_MODE, USBCTL0);
493}
494
495#define USBINITREG1 0xffe70094
496#define USBINITREG2 0xffe7009c
497#define USBINITVAL1 0x00ff0040
498#define USBINITVAL2 0x00000001
499
500#define USBPCTL1 0xffe70804
501#define USBST 0xffe70808
502#define PHY_ENB 0x00000001
503#define PLL_ENB 0x00000002
504#define PHY_RST 0x00000004
505#define ACT_PLL_STATUS 0xc0000000
506static void __init sh7786_usb_setup(void)
507{
508 int i = 1000000;
509
510 /*
511 * USB initial settings
512 *
513 * The following settings are necessary
514 * for using the USB modules.
515 *
516 * see "USB Inital Settings" for detail
517 */
518 __raw_writel(USBINITVAL1, USBINITREG1);
519 __raw_writel(USBINITVAL2, USBINITREG2);
520
521 /*
522 * Set the PHY and PLL enable bit
523 */
524 __raw_writel(PHY_ENB | PLL_ENB, USBPCTL1);
0ee50254
KM		 525 while (i--) {
526 if (ACT_PLL_STATUS == (__raw_readl(USBST) & ACT_PLL_STATUS)) {
527 /* Set the PHY RST bit */
528 __raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1);
529 printk(KERN_INFO "sh7786 usb setup done\n");
530 break;
531 }
4c3f450b 532 cpu_relax();
4c3f450b
KM		 533 }
534}
535
55ba99eb
KM		 536static int __init sh7786_devices_setup(void)
537{
c3d480de
PM		 538 int ret;
539
4c3f450b 540 sh7786_usb_setup();
c3d480de
PM		 541
542 ret = platform_add_devices(sh7786_early_devices,
543 ARRAY_SIZE(sh7786_early_devices));
544 if (unlikely(ret != 0))
545 return ret;
546
55ba99eb
KM		 547 return platform_add_devices(sh7786_devices,
548 ARRAY_SIZE(sh7786_devices));
549}
ba9a6337 550arch_initcall(sh7786_devices_setup);
55ba99eb 551
c3d480de
PM		 552void __init plat_early_device_setup(void)
553{
554 early_platform_add_devices(sh7786_early_devices,
555 ARRAY_SIZE(sh7786_early_devices));
556}
557
55ba99eb
KM		 558enum {
559 UNUSED = 0,
560
561 /* interrupt sources */
562
563 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
564 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
565 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
566 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
567
568 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
569 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
570 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
571 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
572
573 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
574 WDT,
575 TMU0_0, TMU0_1, TMU0_2, TMU0_3,
576 TMU1_0, TMU1_1, TMU1_2,
577 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
578 HUDI1, HUDI0,
579 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
580 HPB_0, HPB_1, HPB_2,
581 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
582 SCIF1,
583 TMU2, TMU3,
584 SCIF2, SCIF3, SCIF4, SCIF5,
585 Eth_0, Eth_1,
586 PCIeC0_0, PCIeC0_1, PCIeC0_2,
587 PCIeC1_0, PCIeC1_1, PCIeC1_2,
588 USB,
589 I2C0, I2C1,
590 DU,
591 SSI0, SSI1, SSI2, SSI3,
592 PCIeC2_0, PCIeC2_1, PCIeC2_2,
593 HAC0, HAC1,
594 FLCTL,
595 HSPI,
596 GPIO0, GPIO1,
597 Thermal,
2eb2a436
PM		 598 INTICI0, INTICI1, INTICI2, INTICI3,
599 INTICI4, INTICI5, INTICI6, INTICI7,
55ba99eb
KM		 600};
601
602static struct intc_vect vectors[] __initdata = {
603 INTC_VECT(WDT, 0x3e0),
604 INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
605 INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
606 INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
607 INTC_VECT(TMU1_2, 0x4c0),
608 INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
609 INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
610 INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
611 INTC_VECT(DMAC0_6, 0x5c0),
612 INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
613 INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
614 INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
615 INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
616 INTC_VECT(HPB_2, 0x6e0),
617 INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
618 INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
619 INTC_VECT(SCIF1, 0x780),
620 INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
621 INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
622 INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
623 INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
624 INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
625 INTC_VECT(PCIeC0_2, 0xb20),
626 INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
627 INTC_VECT(PCIeC1_2, 0xb80),
628 INTC_VECT(USB, 0xba0),
629 INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
630 INTC_VECT(DU, 0xd00),
631 INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
632 INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
633 INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
634 INTC_VECT(PCIeC2_2, 0xde0),
635 INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
636 INTC_VECT(FLCTL, 0xe40),
637 INTC_VECT(HSPI, 0xe80),
638 INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
639 INTC_VECT(Thermal, 0xee0),
2eb2a436
PM		 640 INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
641 INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
642 INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
643 INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
55ba99eb
KM		 644};
645
55ba99eb
KM		 646#define CnINTMSK0 0xfe410030
647#define CnINTMSK1 0xfe410040
648#define CnINTMSKCLR0 0xfe410050
649#define CnINTMSKCLR1 0xfe410060
650#define CnINT2MSKR0 0xfe410a20
651#define CnINT2MSKR1 0xfe410a24
652#define CnINT2MSKR2 0xfe410a28
653#define CnINT2MSKR3 0xfe410a2c
654#define CnINT2MSKCR0 0xfe410a30
655#define CnINT2MSKCR1 0xfe410a34
656#define CnINT2MSKCR2 0xfe410a38
657#define CnINT2MSKCR3 0xfe410a3c
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KM		 658#define INTMSK2 0xfe410068
659#define INTMSKCLR2 0xfe41006c
660
661static struct intc_mask_reg mask_registers[] __initdata = {
662 { CnINTMSK0, CnINTMSKCLR0, 32,
663 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
664 { INTMSK2, INTMSKCLR2, 32,
665 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
666 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
667 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
668 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
669 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
670 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
671 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
672 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
673 { CnINT2MSKR0, CnINT2MSKCR0 , 32,
674 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
675 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT } },
676 { CnINT2MSKR1, CnINT2MSKCR1, 32,
677 { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
678 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
679 HUDI1, HUDI0,
680 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
681 HPB_0, HPB_1, HPB_2,
682 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
683 SCIF1,
684 TMU2, TMU3, 0, } },
685 { CnINT2MSKR2, CnINT2MSKCR2, 32,
686 { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
687 Eth_0, Eth_1,
688 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
689 PCIeC0_0, PCIeC0_1, PCIeC0_2,
690 PCIeC1_0, PCIeC1_1, PCIeC1_2,
691 USB, 0, 0 } },
692 { CnINT2MSKR3, CnINT2MSKCR3, 32,
693 { 0, 0, 0, 0, 0, 0,
694 I2C0, I2C1,
695 DU, SSI0, SSI1, SSI2, SSI3,
696 PCIeC2_0, PCIeC2_1, PCIeC2_2,
697 HAC0, HAC1,
698 FLCTL, 0,
699 HSPI, GPIO0, GPIO1, Thermal,
700 0, 0, 0, 0, 0, 0, 0, 0 } },
701};
702
703static struct intc_prio_reg prio_registers[] __initdata = {
704 { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
705 IRQ4, IRQ5, IRQ6, IRQ7 } },
706 { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
707 { 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1,
708 TMU0_2, TMU0_3 } },
709 { 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1,
710 TMU1_2, 0 } },
711 { 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1,
712 DMAC0_2, DMAC0_3 } },
713 { 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5,
714 DMAC0_6, HUDI1 } },
715 { 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0,
716 DMAC1_1, DMAC1_2 } },
717 { 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0,
718 HPB_1, HPB_2 } },
719 { 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1,
720 SCIF0_2, SCIF0_3 } },
721 { 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },
722 { 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } },
723 { 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5,
724 Eth_0, Eth_1 } },
725 { 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } },
726 { 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } },
727 { 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } },
728 { 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } },
729 { 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2,
730 PCIeC1_0, PCIeC1_1 } },
731 { 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } },
732 { 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } },
733 { 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } },
734 { 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
735 { 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0,
736 PCIeC2_1, PCIeC2_2 } },
737 { 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } },
738 { 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0,
739 GPIO1, Thermal } },
740 { 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } },
741 { 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } },
2eb2a436
PM		 742 { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */
743 { INTICI7, INTICI6, INTICI5, INTICI4,
744 INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) },
55ba99eb
KM		 745};
746
747static DECLARE_INTC_DESC(intc_desc, "sh7786", vectors, NULL,
748 mask_registers, prio_registers, NULL);
749
750/* Support for external interrupt pins in IRQ mode */
751
752static struct intc_vect vectors_irq0123[] __initdata = {
753 INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
754 INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
755};
756
757static struct intc_vect vectors_irq4567[] __initdata = {
758 INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
759 INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
760};
761
762static struct intc_sense_reg sense_registers[] __initdata = {
763 { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
764 IRQ4, IRQ5, IRQ6, IRQ7 } },
765};
766
767static struct intc_mask_reg ack_registers[] __initdata = {
768 { 0xfe410024, 0, 32, /* INTREQ */
769 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
770};
771
772static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
773 vectors_irq0123, NULL, mask_registers,
774 prio_registers, sense_registers, ack_registers);
775
776static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
777 vectors_irq4567, NULL, mask_registers,
778 prio_registers, sense_registers, ack_registers);
779
780/* External interrupt pins in IRL mode */
781
782static struct intc_vect vectors_irl0123[] __initdata = {
783 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
784 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
785 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
786 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
787 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
788 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
789 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
790 INTC_VECT(IRL0_HHHL, 0x3c0),
791};
792
793static struct intc_vect vectors_irl4567[] __initdata = {
794 INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
795 INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
796 INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
797 INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
798 INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
799 INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
800 INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
801 INTC_VECT(IRL4_HHHL, 0xac0),
802};
803
804static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
805 NULL, mask_registers, NULL, NULL);
806
807static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
808 NULL, mask_registers, NULL, NULL);
809
810#define INTC_ICR0 0xfe410000
811#define INTC_INTMSK0 CnINTMSK0
812#define INTC_INTMSK1 CnINTMSK1
813#define INTC_INTMSK2 INTMSK2
814#define INTC_INTMSKCLR1 CnINTMSKCLR1
815#define INTC_INTMSKCLR2 INTMSKCLR2
816
817void __init plat_irq_setup(void)
818{
819 /* disable IRQ3-0 + IRQ7-4 */
820 ctrl_outl(0xff000000, INTC_INTMSK0);
821
822 /* disable IRL3-0 + IRL7-4 */
823 ctrl_outl(0xc0000000, INTC_INTMSK1);
824 ctrl_outl(0xfffefffe, INTC_INTMSK2);
825
826 /* select IRL mode for IRL3-0 + IRL7-4 */
827 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
828
829 register_intc_controller(&intc_desc);
830}
831
832void __init plat_irq_setup_pins(int mode)
833{
834 switch (mode) {
835 case IRQ_MODE_IRQ7654:
836 /* select IRQ mode for IRL7-4 */
837 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
838 register_intc_controller(&intc_desc_irq4567);
839 break;
840 case IRQ_MODE_IRQ3210:
841 /* select IRQ mode for IRL3-0 */
842 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
843 register_intc_controller(&intc_desc_irq0123);
844 break;
845 case IRQ_MODE_IRL7654:
846 /* enable IRL7-4 but don't provide any masking */
847 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
848 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
849 break;
850 case IRQ_MODE_IRL3210:
851 /* enable IRL0-3 but don't provide any masking */
852 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
853 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
854 break;
855 case IRQ_MODE_IRL7654_MASK:
856 /* enable IRL7-4 and mask using cpu intc controller */
857 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
858 register_intc_controller(&intc_desc_irl4567);
859 break;
860 case IRQ_MODE_IRL3210_MASK:
861 /* enable IRL0-3 and mask using cpu intc controller */
862 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
863 register_intc_controller(&intc_desc_irl0123);
864 break;
865 default:
866 BUG();
867 }
868}
869
870void __init plat_mem_setup(void)
871{
872}
Linux 6.x block layer and io_uring tree(s)