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sh: invoke oom-killer from page fault
[linux-2.6-block.git] / arch / sh / kernel / cpu / sh4a / setup-sh7786.c
CommitLineData
55ba99eb
KM		 1/*
2 * SH7786 Setup
3 *
050d4cc7 4 * Copyright (C) 2009 - 2010 Renesas Solutions Corp.
55ba99eb 5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
c3d480de 6 * Paul Mundt <paul.mundt@renesas.com>
55ba99eb
KM		 7 *
8 * Based on SH7785 Setup
9 *
10 * Copyright (C) 2007 Paul Mundt
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file "COPYING" in the main directory of this archive
14 * for more details.
15 */
16#include <linux/platform_device.h>
17#include <linux/init.h>
18#include <linux/serial.h>
19#include <linux/serial_sci.h>
20#include <linux/io.h>
21#include <linux/mm.h>
4c3f450b 22#include <linux/dma-mapping.h>
c3d480de 23#include <linux/sh_timer.h>
43b8774d 24#include <linux/sh_intc.h>
050d4cc7 25#include <cpu/dma-register.h>
55ba99eb 26#include <asm/mmzone.h>
050d4cc7 27#include <asm/dmaengine.h>
55ba99eb 28
a9571d7b
MD		 29static struct plat_sci_port scif0_platform_data = {
30 .mapbase = 0xffea0000,
31 .flags = UPF_BOOT_AUTOCONF,
32 .type = PORT_SCIF,
33 .irqs = { 40, 41, 43, 42 },
34};
35
36static struct platform_device scif0_device = {
55ba99eb 37 .name = "sh-sci",
a9571d7b
MD		 38 .id = 0,
39 .dev = {
40 .platform_data = &scif0_platform_data,
41 },
42};
43
44/*
45 * The rest of these all have multiplexed IRQs
46 */
47static struct plat_sci_port scif1_platform_data = {
48 .mapbase = 0xffeb0000,
49 .flags = UPF_BOOT_AUTOCONF,
50 .type = PORT_SCIF,
51 .irqs = { 44, 44, 44, 44 },
52};
53
54static struct platform_device scif1_device = {
55 .name = "sh-sci",
56 .id = 1,
57 .dev = {
58 .platform_data = &scif1_platform_data,
59 },
60};
61
62static struct plat_sci_port scif2_platform_data = {
63 .mapbase = 0xffec0000,
64 .flags = UPF_BOOT_AUTOCONF,
65 .type = PORT_SCIF,
66 .irqs = { 50, 50, 50, 50 },
67};
68
69static struct platform_device scif2_device = {
70 .name = "sh-sci",
71 .id = 2,
72 .dev = {
73 .platform_data = &scif2_platform_data,
74 },
75};
76
77static struct plat_sci_port scif3_platform_data = {
78 .mapbase = 0xffed0000,
79 .flags = UPF_BOOT_AUTOCONF,
80 .type = PORT_SCIF,
81 .irqs = { 51, 51, 51, 51 },
82};
83
84static struct platform_device scif3_device = {
85 .name = "sh-sci",
86 .id = 3,
87 .dev = {
88 .platform_data = &scif3_platform_data,
89 },
90};
91
92static struct plat_sci_port scif4_platform_data = {
93 .mapbase = 0xffee0000,
94 .flags = UPF_BOOT_AUTOCONF,
95 .type = PORT_SCIF,
96 .irqs = { 52, 52, 52, 52 },
97};
98
99static struct platform_device scif4_device = {
100 .name = "sh-sci",
101 .id = 4,
102 .dev = {
103 .platform_data = &scif4_platform_data,
104 },
105};
106
107static struct plat_sci_port scif5_platform_data = {
108 .mapbase = 0xffef0000,
109 .flags = UPF_BOOT_AUTOCONF,
110 .type = PORT_SCIF,
111 .irqs = { 53, 53, 53, 53 },
112};
113
114static struct platform_device scif5_device = {
115 .name = "sh-sci",
116 .id = 5,
55ba99eb 117 .dev = {
a9571d7b 118 .platform_data = &scif5_platform_data,
55ba99eb
KM		 119 },
120};
121
c3d480de 122static struct sh_timer_config tmu0_platform_data = {
c3d480de
PM		 123 .channel_offset = 0x04,
124 .timer_bit = 0,
c3d480de
PM		 125 .clockevent_rating = 200,
126};
127
128static struct resource tmu0_resources[] = {
129 [0] = {
c3d480de
PM		 130 .start = 0xffd80008,
131 .end = 0xffd80013,
132 .flags = IORESOURCE_MEM,
133 },
134 [1] = {
135 .start = 16,
136 .flags = IORESOURCE_IRQ,
137 },
138};
139
140static struct platform_device tmu0_device = {
141 .name = "sh_tmu",
142 .id = 0,
143 .dev = {
144 .platform_data = &tmu0_platform_data,
145 },
146 .resource = tmu0_resources,
147 .num_resources = ARRAY_SIZE(tmu0_resources),
148};
149
150static struct sh_timer_config tmu1_platform_data = {
c3d480de
PM		 151 .channel_offset = 0x10,
152 .timer_bit = 1,
c3d480de
PM		 153 .clocksource_rating = 200,
154};
155
156static struct resource tmu1_resources[] = {
157 [0] = {
c3d480de
PM		 158 .start = 0xffd80014,
159 .end = 0xffd8001f,
160 .flags = IORESOURCE_MEM,
161 },
162 [1] = {
163 .start = 17,
164 .flags = IORESOURCE_IRQ,
165 },
166};
167
168static struct platform_device tmu1_device = {
169 .name = "sh_tmu",
170 .id = 1,
171 .dev = {
172 .platform_data = &tmu1_platform_data,
173 },
174 .resource = tmu1_resources,
175 .num_resources = ARRAY_SIZE(tmu1_resources),
176};
177
178static struct sh_timer_config tmu2_platform_data = {
c3d480de
PM		 179 .channel_offset = 0x1c,
180 .timer_bit = 2,
c3d480de
PM		 181};
182
183static struct resource tmu2_resources[] = {
184 [0] = {
c3d480de
PM		 185 .start = 0xffd80020,
186 .end = 0xffd8002f,
187 .flags = IORESOURCE_MEM,
188 },
189 [1] = {
190 .start = 18,
191 .flags = IORESOURCE_IRQ,
192 },
193};
194
195static struct platform_device tmu2_device = {
196 .name = "sh_tmu",
197 .id = 2,
198 .dev = {
199 .platform_data = &tmu2_platform_data,
200 },
201 .resource = tmu2_resources,
202 .num_resources = ARRAY_SIZE(tmu2_resources),
203};
204
205static struct sh_timer_config tmu3_platform_data = {
c3d480de
PM		 206 .channel_offset = 0x04,
207 .timer_bit = 0,
c3d480de
PM		 208};
209
210static struct resource tmu3_resources[] = {
211 [0] = {
c3d480de
PM		 212 .start = 0xffda0008,
213 .end = 0xffda0013,
214 .flags = IORESOURCE_MEM,
215 },
216 [1] = {
217 .start = 20,
218 .flags = IORESOURCE_IRQ,
219 },
220};
221
222static struct platform_device tmu3_device = {
223 .name = "sh_tmu",
224 .id = 3,
225 .dev = {
226 .platform_data = &tmu3_platform_data,
227 },
228 .resource = tmu3_resources,
229 .num_resources = ARRAY_SIZE(tmu3_resources),
230};
231
232static struct sh_timer_config tmu4_platform_data = {
c3d480de
PM		 233 .channel_offset = 0x10,
234 .timer_bit = 1,
c3d480de
PM		 235};
236
237static struct resource tmu4_resources[] = {
238 [0] = {
c3d480de
PM		 239 .start = 0xffda0014,
240 .end = 0xffda001f,
241 .flags = IORESOURCE_MEM,
242 },
243 [1] = {
244 .start = 21,
245 .flags = IORESOURCE_IRQ,
246 },
247};
248
249static struct platform_device tmu4_device = {
250 .name = "sh_tmu",
251 .id = 4,
252 .dev = {
253 .platform_data = &tmu4_platform_data,
254 },
255 .resource = tmu4_resources,
256 .num_resources = ARRAY_SIZE(tmu4_resources),
257};
258
259static struct sh_timer_config tmu5_platform_data = {
c3d480de
PM		 260 .channel_offset = 0x1c,
261 .timer_bit = 2,
c3d480de
PM		 262};
263
264static struct resource tmu5_resources[] = {
265 [0] = {
c3d480de
PM		 266 .start = 0xffda0020,
267 .end = 0xffda002b,
268 .flags = IORESOURCE_MEM,
269 },
270 [1] = {
271 .start = 22,
272 .flags = IORESOURCE_IRQ,
273 },
274};
275
276static struct platform_device tmu5_device = {
277 .name = "sh_tmu",
278 .id = 5,
279 .dev = {
280 .platform_data = &tmu5_platform_data,
281 },
282 .resource = tmu5_resources,
283 .num_resources = ARRAY_SIZE(tmu5_resources),
284};
285
286static struct sh_timer_config tmu6_platform_data = {
c3d480de
PM		 287 .channel_offset = 0x04,
288 .timer_bit = 0,
c3d480de
PM		 289};
290
291static struct resource tmu6_resources[] = {
292 [0] = {
c3d480de
PM		 293 .start = 0xffdc0008,
294 .end = 0xffdc0013,
295 .flags = IORESOURCE_MEM,
296 },
297 [1] = {
298 .start = 45,
299 .flags = IORESOURCE_IRQ,
300 },
301};
302
303static struct platform_device tmu6_device = {
304 .name = "sh_tmu",
305 .id = 6,
306 .dev = {
307 .platform_data = &tmu6_platform_data,
308 },
309 .resource = tmu6_resources,
310 .num_resources = ARRAY_SIZE(tmu6_resources),
311};
312
313static struct sh_timer_config tmu7_platform_data = {
c3d480de
PM		 314 .channel_offset = 0x10,
315 .timer_bit = 1,
c3d480de
PM		 316};
317
318static struct resource tmu7_resources[] = {
319 [0] = {
c3d480de
PM		 320 .start = 0xffdc0014,
321 .end = 0xffdc001f,
322 .flags = IORESOURCE_MEM,
323 },
324 [1] = {
325 .start = 45,
326 .flags = IORESOURCE_IRQ,
327 },
328};
329
330static struct platform_device tmu7_device = {
331 .name = "sh_tmu",
332 .id = 7,
333 .dev = {
334 .platform_data = &tmu7_platform_data,
335 },
336 .resource = tmu7_resources,
337 .num_resources = ARRAY_SIZE(tmu7_resources),
338};
339
340static struct sh_timer_config tmu8_platform_data = {
c3d480de
PM		 341 .channel_offset = 0x1c,
342 .timer_bit = 2,
c3d480de
PM		 343};
344
345static struct resource tmu8_resources[] = {
346 [0] = {
c3d480de
PM		 347 .start = 0xffdc0020,
348 .end = 0xffdc002b,
349 .flags = IORESOURCE_MEM,
350 },
351 [1] = {
352 .start = 45,
353 .flags = IORESOURCE_IRQ,
354 },
355};
356
357static struct platform_device tmu8_device = {
358 .name = "sh_tmu",
359 .id = 8,
360 .dev = {
361 .platform_data = &tmu8_platform_data,
362 },
363 .resource = tmu8_resources,
364 .num_resources = ARRAY_SIZE(tmu8_resources),
365};
366
367static struct sh_timer_config tmu9_platform_data = {
c3d480de
PM		 368 .channel_offset = 0x04,
369 .timer_bit = 0,
c3d480de
PM		 370};
371
372static struct resource tmu9_resources[] = {
373 [0] = {
c3d480de
PM		 374 .start = 0xffde0008,
375 .end = 0xffde0013,
376 .flags = IORESOURCE_MEM,
377 },
378 [1] = {
379 .start = 46,
380 .flags = IORESOURCE_IRQ,
381 },
382};
383
384static struct platform_device tmu9_device = {
385 .name = "sh_tmu",
386 .id = 9,
387 .dev = {
388 .platform_data = &tmu9_platform_data,
389 },
390 .resource = tmu9_resources,
391 .num_resources = ARRAY_SIZE(tmu9_resources),
392};
393
394static struct sh_timer_config tmu10_platform_data = {
c3d480de
PM		 395 .channel_offset = 0x10,
396 .timer_bit = 1,
c3d480de
PM		 397};
398
399static struct resource tmu10_resources[] = {
400 [0] = {
c3d480de
PM		 401 .start = 0xffde0014,
402 .end = 0xffde001f,
403 .flags = IORESOURCE_MEM,
404 },
405 [1] = {
406 .start = 46,
407 .flags = IORESOURCE_IRQ,
408 },
409};
410
411static struct platform_device tmu10_device = {
412 .name = "sh_tmu",
413 .id = 10,
414 .dev = {
415 .platform_data = &tmu10_platform_data,
416 },
417 .resource = tmu10_resources,
418 .num_resources = ARRAY_SIZE(tmu10_resources),
419};
420
421static struct sh_timer_config tmu11_platform_data = {
c3d480de
PM		 422 .channel_offset = 0x1c,
423 .timer_bit = 2,
c3d480de
PM		 424};
425
426static struct resource tmu11_resources[] = {
427 [0] = {
c3d480de
PM		 428 .start = 0xffde0020,
429 .end = 0xffde002b,
430 .flags = IORESOURCE_MEM,
431 },
432 [1] = {
433 .start = 46,
434 .flags = IORESOURCE_IRQ,
435 },
436};
437
438static struct platform_device tmu11_device = {
439 .name = "sh_tmu",
440 .id = 11,
441 .dev = {
442 .platform_data = &tmu11_platform_data,
443 },
444 .resource = tmu11_resources,
445 .num_resources = ARRAY_SIZE(tmu11_resources),
446};
447
050d4cc7
PM		 448static struct sh_dmae_channel dmac0_channels[] = {
449 {
450 .offset = 0,
451 .dmars = 0,
452 .dmars_bit = 0,
453 }, {
454 .offset = 0x10,
455 .dmars = 0,
456 .dmars_bit = 8,
457 }, {
458 .offset = 0x20,
459 .dmars = 4,
460 .dmars_bit = 0,
461 }, {
462 .offset = 0x30,
463 .dmars = 4,
464 .dmars_bit = 8,
465 }, {
466 .offset = 0x50,
467 .dmars = 8,
468 .dmars_bit = 0,
469 }, {
470 .offset = 0x60,
471 .dmars = 8,
472 .dmars_bit = 8,
473 }
474};
475
476static unsigned int ts_shift[] = TS_SHIFT;
477
478static struct sh_dmae_pdata dma0_platform_data = {
479 .channel = dmac0_channels,
480 .channel_num = ARRAY_SIZE(dmac0_channels),
481 .ts_low_shift = CHCR_TS_LOW_SHIFT,
482 .ts_low_mask = CHCR_TS_LOW_MASK,
483 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
484 .ts_high_mask = CHCR_TS_HIGH_MASK,
485 .ts_shift = ts_shift,
486 .ts_shift_num = ARRAY_SIZE(ts_shift),
487 .dmaor_init = DMAOR_INIT,
488};
489
490/* Resource order important! */
491static struct resource dmac0_resources[] = {
492 {
493 /* Channel registers and DMAOR */
494 .start = 0xfe008020,
495 .end = 0xfe00808f,
496 .flags = IORESOURCE_MEM,
497 }, {
498 /* DMARSx */
499 .start = 0xfe009000,
500 .end = 0xfe00900b,
501 .flags = IORESOURCE_MEM,
502 }, {
503 /* DMA error IRQ */
504 .start = evt2irq(0x5c0),
505 .end = evt2irq(0x5c0),
506 .flags = IORESOURCE_IRQ,
507 }, {
508 /* IRQ for channels 0-5 */
509 .start = evt2irq(0x500),
510 .end = evt2irq(0x5a0),
511 .flags = IORESOURCE_IRQ,
512 },
513};
514
515static struct platform_device dma0_device = {
516 .name = "sh-dma-engine",
517 .id = 0,
518 .resource = dmac0_resources,
519 .num_resources = ARRAY_SIZE(dmac0_resources),
520 .dev = {
521 .platform_data = &dma0_platform_data,
522 },
523};
524
4c3f450b
KM		 525static struct resource usb_ohci_resources[] = {
526 [0] = {
527 .start = 0xffe70400,
528 .end = 0xffe704ff,
529 .flags = IORESOURCE_MEM,
530 },
531 [1] = {
532 .start = 77,
533 .end = 77,
534 .flags = IORESOURCE_IRQ,
535 },
536};
537
538static u64 usb_ohci_dma_mask = DMA_BIT_MASK(32);
539static struct platform_device usb_ohci_device = {
540 .name = "sh_ohci",
541 .id = -1,
542 .dev = {
543 .dma_mask = &usb_ohci_dma_mask,
544 .coherent_dma_mask = DMA_BIT_MASK(32),
545 },
546 .num_resources = ARRAY_SIZE(usb_ohci_resources),
547 .resource = usb_ohci_resources,
548};
549
c3d480de 550static struct platform_device *sh7786_early_devices[] __initdata = {
a9571d7b
MD		 551 &scif0_device,
552 &scif1_device,
553 &scif2_device,
554 &scif3_device,
555 &scif4_device,
556 &scif5_device,
c3d480de
PM		 557 &tmu0_device,
558 &tmu1_device,
559 &tmu2_device,
560 &tmu3_device,
561 &tmu4_device,
562 &tmu5_device,
563 &tmu6_device,
564 &tmu7_device,
565 &tmu8_device,
566 &tmu9_device,
567 &tmu10_device,
568 &tmu11_device,
569};
570
55ba99eb 571static struct platform_device *sh7786_devices[] __initdata = {
050d4cc7 572 &dma0_device,
4c3f450b 573 &usb_ohci_device,
55ba99eb
KM		 574};
575
4c3f450b
KM		 576/*
577 * Please call this function if your platform board
578 * use external clock for USB
579 * */
580#define USBCTL0 0xffe70858
581#define CLOCK_MODE_MASK 0xffffff7f
582#define EXT_CLOCK_MODE 0x00000080
dc825b17 583
4c3f450b
KM		 584void __init sh7786_usb_use_exclock(void)
585{
586 u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK;
587 __raw_writel(val | EXT_CLOCK_MODE, USBCTL0);
588}
589
590#define USBINITREG1 0xffe70094
591#define USBINITREG2 0xffe7009c
592#define USBINITVAL1 0x00ff0040
593#define USBINITVAL2 0x00000001
594
595#define USBPCTL1 0xffe70804
596#define USBST 0xffe70808
597#define PHY_ENB 0x00000001
598#define PLL_ENB 0x00000002
599#define PHY_RST 0x00000004
600#define ACT_PLL_STATUS 0xc0000000
dc825b17 601
4c3f450b
KM		 602static void __init sh7786_usb_setup(void)
603{
604 int i = 1000000;
605
606 /*
607 * USB initial settings
608 *
609 * The following settings are necessary
610 * for using the USB modules.
611 *
612 * see "USB Inital Settings" for detail
613 */
614 __raw_writel(USBINITVAL1, USBINITREG1);
615 __raw_writel(USBINITVAL2, USBINITREG2);
616
617 /*
618 * Set the PHY and PLL enable bit
619 */
620 __raw_writel(PHY_ENB | PLL_ENB, USBPCTL1);
0ee50254
KM		 621 while (i--) {
622 if (ACT_PLL_STATUS == (__raw_readl(USBST) & ACT_PLL_STATUS)) {
623 /* Set the PHY RST bit */
624 __raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1);
625 printk(KERN_INFO "sh7786 usb setup done\n");
626 break;
627 }
4c3f450b 628 cpu_relax();
4c3f450b
KM		 629 }
630}
631
55ba99eb
KM		 632static int __init sh7786_devices_setup(void)
633{
c3d480de
PM		 634 int ret;
635
4c3f450b 636 sh7786_usb_setup();
c3d480de
PM		 637
638 ret = platform_add_devices(sh7786_early_devices,
639 ARRAY_SIZE(sh7786_early_devices));
640 if (unlikely(ret != 0))
641 return ret;
642
55ba99eb
KM		 643 return platform_add_devices(sh7786_devices,
644 ARRAY_SIZE(sh7786_devices));
645}
ba9a6337 646arch_initcall(sh7786_devices_setup);
55ba99eb 647
c3d480de
PM		 648void __init plat_early_device_setup(void)
649{
650 early_platform_add_devices(sh7786_early_devices,
651 ARRAY_SIZE(sh7786_early_devices));
652}
653
55ba99eb
KM		 654enum {
655 UNUSED = 0,
656
657 /* interrupt sources */
658
659 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
660 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
661 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
662 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
663
664 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
665 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
666 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
667 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
668
669 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
670 WDT,
671 TMU0_0, TMU0_1, TMU0_2, TMU0_3,
672 TMU1_0, TMU1_1, TMU1_2,
673 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
674 HUDI1, HUDI0,
675 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
676 HPB_0, HPB_1, HPB_2,
677 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
678 SCIF1,
679 TMU2, TMU3,
680 SCIF2, SCIF3, SCIF4, SCIF5,
681 Eth_0, Eth_1,
682 PCIeC0_0, PCIeC0_1, PCIeC0_2,
683 PCIeC1_0, PCIeC1_1, PCIeC1_2,
684 USB,
685 I2C0, I2C1,
686 DU,
687 SSI0, SSI1, SSI2, SSI3,
688 PCIeC2_0, PCIeC2_1, PCIeC2_2,
689 HAC0, HAC1,
690 FLCTL,
691 HSPI,
692 GPIO0, GPIO1,
693 Thermal,
2eb2a436
PM		 694 INTICI0, INTICI1, INTICI2, INTICI3,
695 INTICI4, INTICI5, INTICI6, INTICI7,
55ba99eb
KM		 696};
697
698static struct intc_vect vectors[] __initdata = {
699 INTC_VECT(WDT, 0x3e0),
700 INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
701 INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
702 INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
703 INTC_VECT(TMU1_2, 0x4c0),
704 INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
705 INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
706 INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
707 INTC_VECT(DMAC0_6, 0x5c0),
708 INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
709 INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
710 INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
711 INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
712 INTC_VECT(HPB_2, 0x6e0),
713 INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
714 INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
715 INTC_VECT(SCIF1, 0x780),
716 INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
717 INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
718 INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
719 INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
720 INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
721 INTC_VECT(PCIeC0_2, 0xb20),
722 INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
723 INTC_VECT(PCIeC1_2, 0xb80),
724 INTC_VECT(USB, 0xba0),
725 INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
726 INTC_VECT(DU, 0xd00),
727 INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
728 INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
729 INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
730 INTC_VECT(PCIeC2_2, 0xde0),
731 INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
732 INTC_VECT(FLCTL, 0xe40),
733 INTC_VECT(HSPI, 0xe80),
734 INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
735 INTC_VECT(Thermal, 0xee0),
2eb2a436
PM		 736 INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
737 INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
738 INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
739 INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
55ba99eb
KM		 740};
741
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KM		 742#define CnINTMSK0 0xfe410030
743#define CnINTMSK1 0xfe410040
744#define CnINTMSKCLR0 0xfe410050
745#define CnINTMSKCLR1 0xfe410060
746#define CnINT2MSKR0 0xfe410a20
747#define CnINT2MSKR1 0xfe410a24
748#define CnINT2MSKR2 0xfe410a28
749#define CnINT2MSKR3 0xfe410a2c
750#define CnINT2MSKCR0 0xfe410a30
751#define CnINT2MSKCR1 0xfe410a34
752#define CnINT2MSKCR2 0xfe410a38
753#define CnINT2MSKCR3 0xfe410a3c
55ba99eb
KM		 754#define INTMSK2 0xfe410068
755#define INTMSKCLR2 0xfe41006c
756
dc825b17
PM		 757#define INTDISTCR0 0xfe4100b0
758#define INTDISTCR1 0xfe4100b4
759#define INTACK 0xfe4100b8
760#define INTACKCLR 0xfe4100bc
761#define INT2DISTCR0 0xfe410900
762#define INT2DISTCR1 0xfe410904
763#define INT2DISTCR2 0xfe410908
764#define INT2DISTCR3 0xfe41090c
765
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KM		 766static struct intc_mask_reg mask_registers[] __initdata = {
767 { CnINTMSK0, CnINTMSKCLR0, 32,
dc825b17
PM		 768 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 },
769 INTC_SMP_BALANCING(INTDISTCR0) },
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KM		 770 { INTMSK2, INTMSKCLR2, 32,
771 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
772 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
773 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
774 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
775 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
776 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
777 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
778 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
779 { CnINT2MSKR0, CnINT2MSKCR0 , 32,
780 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
dc825b17
PM		 781 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT },
782 INTC_SMP_BALANCING(INT2DISTCR0) },
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KM		 783 { CnINT2MSKR1, CnINT2MSKCR1, 32,
784 { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
785 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
786 HUDI1, HUDI0,
787 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
788 HPB_0, HPB_1, HPB_2,
789 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
790 SCIF1,
dc825b17 791 TMU2, TMU3, 0, }, INTC_SMP_BALANCING(INT2DISTCR1) },
55ba99eb
KM		 792 { CnINT2MSKR2, CnINT2MSKCR2, 32,
793 { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
794 Eth_0, Eth_1,
795 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
796 PCIeC0_0, PCIeC0_1, PCIeC0_2,
797 PCIeC1_0, PCIeC1_1, PCIeC1_2,
dc825b17 798 USB, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR2) },
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KM		 799 { CnINT2MSKR3, CnINT2MSKCR3, 32,
800 { 0, 0, 0, 0, 0, 0,
801 I2C0, I2C1,
802 DU, SSI0, SSI1, SSI2, SSI3,
803 PCIeC2_0, PCIeC2_1, PCIeC2_2,
804 HAC0, HAC1,
805 FLCTL, 0,
806 HSPI, GPIO0, GPIO1, Thermal,
dc825b17 807 0, 0, 0, 0, 0, 0, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR3) },
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KM		 808};
809
810static struct intc_prio_reg prio_registers[] __initdata = {
811 { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
812 IRQ4, IRQ5, IRQ6, IRQ7 } },
813 { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
814 { 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1,
815 TMU0_2, TMU0_3 } },
816 { 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1,
817 TMU1_2, 0 } },
818 { 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1,
819 DMAC0_2, DMAC0_3 } },
820 { 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5,
821 DMAC0_6, HUDI1 } },
822 { 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0,
823 DMAC1_1, DMAC1_2 } },
824 { 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0,
825 HPB_1, HPB_2 } },
826 { 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1,
827 SCIF0_2, SCIF0_3 } },
828 { 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },
829 { 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } },
830 { 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5,
831 Eth_0, Eth_1 } },
832 { 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } },
833 { 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } },
834 { 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } },
835 { 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } },
836 { 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2,
837 PCIeC1_0, PCIeC1_1 } },
838 { 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } },
839 { 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } },
840 { 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } },
841 { 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
842 { 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0,
843 PCIeC2_1, PCIeC2_2 } },
844 { 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } },
845 { 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0,
846 GPIO1, Thermal } },
847 { 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } },
848 { 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } },
2eb2a436
PM		 849 { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */
850 { INTICI7, INTICI6, INTICI5, INTICI4,
851 INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) },
55ba99eb
KM		 852};
853
854static DECLARE_INTC_DESC(intc_desc, "sh7786", vectors, NULL,
855 mask_registers, prio_registers, NULL);
856
857/* Support for external interrupt pins in IRQ mode */
858
859static struct intc_vect vectors_irq0123[] __initdata = {
860 INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
861 INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
862};
863
864static struct intc_vect vectors_irq4567[] __initdata = {
865 INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
866 INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
867};
868
869static struct intc_sense_reg sense_registers[] __initdata = {
870 { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
871 IRQ4, IRQ5, IRQ6, IRQ7 } },
872};
873
874static struct intc_mask_reg ack_registers[] __initdata = {
875 { 0xfe410024, 0, 32, /* INTREQ */
876 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
877};
878
879static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
880 vectors_irq0123, NULL, mask_registers,
881 prio_registers, sense_registers, ack_registers);
882
883static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
884 vectors_irq4567, NULL, mask_registers,
885 prio_registers, sense_registers, ack_registers);
886
887/* External interrupt pins in IRL mode */
888
889static struct intc_vect vectors_irl0123[] __initdata = {
890 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
891 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
892 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
893 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
894 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
895 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
896 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
897 INTC_VECT(IRL0_HHHL, 0x3c0),
898};
899
900static struct intc_vect vectors_irl4567[] __initdata = {
901 INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
902 INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
903 INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
904 INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
905 INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
906 INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
907 INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
908 INTC_VECT(IRL4_HHHL, 0xac0),
909};
910
911static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
912 NULL, mask_registers, NULL, NULL);
913
914static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
915 NULL, mask_registers, NULL, NULL);
916
917#define INTC_ICR0 0xfe410000
918#define INTC_INTMSK0 CnINTMSK0
919#define INTC_INTMSK1 CnINTMSK1
920#define INTC_INTMSK2 INTMSK2
921#define INTC_INTMSKCLR1 CnINTMSKCLR1
922#define INTC_INTMSKCLR2 INTMSKCLR2
43b8774d 923#define INTC_USERIMASK 0xfe411000
55ba99eb 924
dc825b17
PM		 925#ifdef CONFIG_INTC_BALANCING
926unsigned int irq_lookup(unsigned int irq)
927{
928 return __raw_readl(INTACK) & 1 ? irq : NO_IRQ_IGNORE;
929}
930
931void irq_finish(unsigned int irq)
932{
933 __raw_writel(irq2evt(irq), INTACKCLR);
934}
935#endif
936
55ba99eb
KM		 937void __init plat_irq_setup(void)
938{
939 /* disable IRQ3-0 + IRQ7-4 */
9d56dd3b 940 __raw_writel(0xff000000, INTC_INTMSK0);
55ba99eb
KM		 941
942 /* disable IRL3-0 + IRL7-4 */
9d56dd3b
PM		 943 __raw_writel(0xc0000000, INTC_INTMSK1);
944 __raw_writel(0xfffefffe, INTC_INTMSK2);
55ba99eb
KM		 945
946 /* select IRL mode for IRL3-0 + IRL7-4 */
9d56dd3b 947 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
55ba99eb
KM		 948
949 register_intc_controller(&intc_desc);
43b8774d 950 register_intc_userimask(INTC_USERIMASK);
55ba99eb
KM		 951}
952
953void __init plat_irq_setup_pins(int mode)
954{
955 switch (mode) {
956 case IRQ_MODE_IRQ7654:
957 /* select IRQ mode for IRL7-4 */
9d56dd3b 958 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
55ba99eb
KM		 959 register_intc_controller(&intc_desc_irq4567);
960 break;
961 case IRQ_MODE_IRQ3210:
962 /* select IRQ mode for IRL3-0 */
9d56dd3b 963 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
55ba99eb
KM		 964 register_intc_controller(&intc_desc_irq0123);
965 break;
966 case IRQ_MODE_IRL7654:
967 /* enable IRL7-4 but don't provide any masking */
9d56dd3b
PM		 968 __raw_writel(0x40000000, INTC_INTMSKCLR1);
969 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
55ba99eb
KM		 970 break;
971 case IRQ_MODE_IRL3210:
972 /* enable IRL0-3 but don't provide any masking */
9d56dd3b
PM		 973 __raw_writel(0x80000000, INTC_INTMSKCLR1);
974 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
55ba99eb
KM		 975 break;
976 case IRQ_MODE_IRL7654_MASK:
977 /* enable IRL7-4 and mask using cpu intc controller */
9d56dd3b 978 __raw_writel(0x40000000, INTC_INTMSKCLR1);
55ba99eb
KM		 979 register_intc_controller(&intc_desc_irl4567);
980 break;
981 case IRQ_MODE_IRL3210_MASK:
982 /* enable IRL0-3 and mask using cpu intc controller */
9d56dd3b 983 __raw_writel(0x80000000, INTC_INTMSKCLR1);
55ba99eb
KM		 984 register_intc_controller(&intc_desc_irl0123);
985 break;
986 default:
987 BUG();
988 }
989}
990
991void __init plat_mem_setup(void)
992{
993}
Linux 6.x block layer and io_uring tree(s)