[linux-block.git] / arch / sh / kernel / cpu / sh4a / setup-sh7785.c

/*
 * SH7785 Setup
 *
 *  Copyright (C) 2007  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/serial_sci.h>
#include <linux/io.h>
#include <linux/mm.h>
#include <linux/sh_timer.h>
#include <asm/mmzone.h>

static struct sh_timer_config tmu0_platform_data = {
	.name = "TMU0",
	.channel_offset = 0x04,
	.timer_bit = 0,
	.clk = "tmu012_fck",
	.clockevent_rating = 200,
};

static struct resource tmu0_resources[] = {
	[0] = {
		.name	= "TMU0",
		.start	= 0xffd80008,
		.end	= 0xffd80013,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 28,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu0_device = {
	.name		= "sh_tmu",
	.id		= 0,
	.dev = {
		.platform_data	= &tmu0_platform_data,
	},
	.resource	= tmu0_resources,
	.num_resources	= ARRAY_SIZE(tmu0_resources),
};

static struct sh_timer_config tmu1_platform_data = {
	.name = "TMU1",
	.channel_offset = 0x10,
	.timer_bit = 1,
	.clk = "tmu012_fck",
	.clocksource_rating = 200,
};

static struct resource tmu1_resources[] = {
	[0] = {
		.name	= "TMU1",
		.start	= 0xffd80014,
		.end	= 0xffd8001f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 29,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu1_device = {
	.name		= "sh_tmu",
	.id		= 1,
	.dev = {
		.platform_data	= &tmu1_platform_data,
	},
	.resource	= tmu1_resources,
	.num_resources	= ARRAY_SIZE(tmu1_resources),
};

static struct sh_timer_config tmu2_platform_data = {
	.name = "TMU2",
	.channel_offset = 0x1c,
	.timer_bit = 2,
	.clk = "tmu012_fck",
};

static struct resource tmu2_resources[] = {
	[0] = {
		.name	= "TMU2",
		.start	= 0xffd80020,
		.end	= 0xffd8002f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 30,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu2_device = {
	.name		= "sh_tmu",
	.id		= 2,
	.dev = {
		.platform_data	= &tmu2_platform_data,
	},
	.resource	= tmu2_resources,
	.num_resources	= ARRAY_SIZE(tmu2_resources),
};

static struct sh_timer_config tmu3_platform_data = {
	.name = "TMU3",
	.channel_offset = 0x04,
	.timer_bit = 0,
	.clk = "tmu345_fck",
};

static struct resource tmu3_resources[] = {
	[0] = {
		.name	= "TMU3",
		.start	= 0xffdc0008,
		.end	= 0xffdc0013,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 96,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu3_device = {
	.name		= "sh_tmu",
	.id		= 3,
	.dev = {
		.platform_data	= &tmu3_platform_data,
	},
	.resource	= tmu3_resources,
	.num_resources	= ARRAY_SIZE(tmu3_resources),
};

static struct sh_timer_config tmu4_platform_data = {
	.name = "TMU4",
	.channel_offset = 0x10,
	.timer_bit = 1,
	.clk = "tmu345_fck",
};

static struct resource tmu4_resources[] = {
	[0] = {
		.name	= "TMU4",
		.start	= 0xffdc0014,
		.end	= 0xffdc001f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 97,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu4_device = {
	.name		= "sh_tmu",
	.id		= 4,
	.dev = {
		.platform_data	= &tmu4_platform_data,
	},
	.resource	= tmu4_resources,
	.num_resources	= ARRAY_SIZE(tmu4_resources),
};

static struct sh_timer_config tmu5_platform_data = {
	.name = "TMU5",
	.channel_offset = 0x1c,
	.timer_bit = 2,
	.clk = "tmu345_fck",
};

static struct resource tmu5_resources[] = {
	[0] = {
		.name	= "TMU5",
		.start	= 0xffdc0020,
		.end	= 0xffdc002b,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 98,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu5_device = {
	.name		= "sh_tmu",
	.id		= 5,
	.dev = {
		.platform_data	= &tmu5_platform_data,
	},
	.resource	= tmu5_resources,
	.num_resources	= ARRAY_SIZE(tmu5_resources),
};

static struct plat_sci_port sci_platform_data[] = {
	{
		.mapbase	= 0xffea0000,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIF,
		.irqs		= { 40, 40, 40, 40 },
		.clk		= "scif_fck",
	}, {
		.mapbase	= 0xffeb0000,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIF,
		.irqs		= { 44, 44, 44, 44 },
		.clk		= "scif_fck",
	}, {
		.mapbase	= 0xffec0000,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIF,
		.irqs		= { 60, 60, 60, 60 },
		.clk		= "scif_fck",
	}, {
		.mapbase	= 0xffed0000,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIF,
		.irqs		= { 61, 61, 61, 61 },
		.clk		= "scif_fck",
	}, {
		.mapbase	= 0xffee0000,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIF,
		.irqs		= { 62, 62, 62, 62 },
		.clk		= "scif_fck",
	}, {
		.mapbase	= 0xffef0000,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIF,
		.irqs		= { 63, 63, 63, 63 },
		.clk		= "scif_fck",
	}, {
		.flags = 0,
	}
};

static struct platform_device sci_device = {
	.name		= "sh-sci",
	.id		= -1,
	.dev		= {
		.platform_data	= sci_platform_data,
	},
};

static struct platform_device *sh7785_devices[] __initdata = {
	&tmu0_device,
	&tmu1_device,
	&tmu2_device,
	&tmu3_device,
	&tmu4_device,
	&tmu5_device,
	&sci_device,
};

static int __init sh7785_devices_setup(void)
{
	return platform_add_devices(sh7785_devices,
				    ARRAY_SIZE(sh7785_devices));
}
arch_initcall(sh7785_devices_setup);

static struct platform_device *sh7785_early_devices[] __initdata = {
	&tmu0_device,
	&tmu1_device,
	&tmu2_device,
	&tmu3_device,
	&tmu4_device,
	&tmu5_device,
};

void __init plat_early_device_setup(void)
{
	early_platform_add_devices(sh7785_early_devices,
				   ARRAY_SIZE(sh7785_early_devices));
}

enum {
	UNUSED = 0,

	/* interrupt sources */

	IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
	IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
	IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
	IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,

	IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
	IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
	IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
	IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,

	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
	HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI,
	SCIF2, SCIF3, SCIF4, SCIF5,
	PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
	SIOF, MMCIF, DU, GDTA,
	TMU3, TMU4, TMU5,
	SSI0, SSI1,
	HAC0, HAC1,
	FLCTL, GPIO,

	/* interrupt groups */

	TMU012,	TMU345
};

static struct intc_vect vectors[] __initdata = {
	INTC_VECT(WDT, 0x560),
	INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
	INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
	INTC_VECT(HUDI, 0x600),
	INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
	INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
	INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
	INTC_VECT(DMAC0, 0x6e0),
	INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
	INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
	INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
	INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
	INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
	INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
	INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
	INTC_VECT(DMAC1, 0x940),
	INTC_VECT(HSPI, 0x960),
	INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
	INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
	INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
	INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
	INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
	INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
	INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
	INTC_VECT(SIOF, 0xc00),
	INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
	INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
	INTC_VECT(DU, 0xd80),
	INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
	INTC_VECT(GDTA, 0xde0),
	INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
	INTC_VECT(TMU5, 0xe40),
	INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
	INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
	INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
	INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
	INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
	INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
};

static struct intc_group groups[] __initdata = {
	INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
	INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
};

static struct intc_mask_reg mask_registers[] __initdata = {
	{ 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },

	{ 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
	  { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
	    IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
	    IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
	    IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
	    IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
	    IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
	    IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
	    IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },

	{ 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
	  { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
	    FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
	    PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
	    SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
};

static struct intc_prio_reg prio_registers[] __initdata = {
	{ 0xffd00010, 0, 32, 4, /* INTPRI */   { IRQ0, IRQ1, IRQ2, IRQ3,
						 IRQ4, IRQ5, IRQ6, IRQ7 } },
	{ 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
						 TMU2, TMU2_TICPI } },
	{ 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
	{ 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1,
						 SCIF2, SCIF3 } },
	{ 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
	{ 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
	{ 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1,
						 PCISERR, PCIINTA } },
	{ 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
						 PCIINTD, PCIC5 } },
	{ 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
	{ 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
	{ 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
};

static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups,
			 mask_registers, prio_registers, NULL);

/* Support for external interrupt pins in IRQ mode */

static struct intc_vect vectors_irq0123[] __initdata = {
	INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
	INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
};

static struct intc_vect vectors_irq4567[] __initdata = {
	INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
	INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
};

static struct intc_sense_reg sense_registers[] __initdata = {
	{ 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
					    IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_mask_reg ack_registers[] __initdata = {
	{ 0xffd00024, 0, 32, /* INTREQ */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7785-irq0123",
			     vectors_irq0123, NULL, mask_registers,
			     prio_registers, sense_registers, ack_registers);

static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7785-irq4567",
			     vectors_irq4567, NULL, mask_registers,
			     prio_registers, sense_registers, ack_registers);

/* External interrupt pins in IRL mode */

static struct intc_vect vectors_irl0123[] __initdata = {
	INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
	INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
	INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
	INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
	INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
	INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
	INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
	INTC_VECT(IRL0_HHHL, 0x3c0),
};

static struct intc_vect vectors_irl4567[] __initdata = {
	INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
	INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
	INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
	INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
	INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
	INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
	INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
	INTC_VECT(IRL4_HHHL, 0xcc0),
};

static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
			 NULL, mask_registers, NULL, NULL);

static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
			 NULL, mask_registers, NULL, NULL);

#define INTC_ICR0	0xffd00000
#define INTC_INTMSK0	0xffd00044
#define INTC_INTMSK1	0xffd00048
#define INTC_INTMSK2	0xffd40080
#define INTC_INTMSKCLR1	0xffd00068
#define INTC_INTMSKCLR2	0xffd40084

void __init plat_irq_setup(void)
{
	/* disable IRQ3-0 + IRQ7-4 */
	ctrl_outl(0xff000000, INTC_INTMSK0);

	/* disable IRL3-0 + IRL7-4 */
	ctrl_outl(0xc0000000, INTC_INTMSK1);
	ctrl_outl(0xfffefffe, INTC_INTMSK2);

	/* select IRL mode for IRL3-0 + IRL7-4 */
	ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);

	/* disable holding function, ie enable "SH-4 Mode" */
	ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);

	register_intc_controller(&intc_desc);
}

void __init plat_irq_setup_pins(int mode)
{
	switch (mode) {
	case IRQ_MODE_IRQ7654:
		/* select IRQ mode for IRL7-4 */
		ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
		register_intc_controller(&intc_desc_irq4567);
		break;
	case IRQ_MODE_IRQ3210:
		/* select IRQ mode for IRL3-0 */
		ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
		register_intc_controller(&intc_desc_irq0123);
		break;
	case IRQ_MODE_IRL7654:
		/* enable IRL7-4 but don't provide any masking */
		ctrl_outl(0x40000000, INTC_INTMSKCLR1);
		ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
		break;
	case IRQ_MODE_IRL3210:
		/* enable IRL0-3 but don't provide any masking */
		ctrl_outl(0x80000000, INTC_INTMSKCLR1);
		ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
		break;
	case IRQ_MODE_IRL7654_MASK:
		/* enable IRL7-4 and mask using cpu intc controller */
		ctrl_outl(0x40000000, INTC_INTMSKCLR1);
		register_intc_controller(&intc_desc_irl4567);
		break;
	case IRQ_MODE_IRL3210_MASK:
		/* enable IRL0-3 and mask using cpu intc controller */
		ctrl_outl(0x80000000, INTC_INTMSKCLR1);
		register_intc_controller(&intc_desc_irl0123);
		break;
	default:
		BUG();
	}
}

void __init plat_mem_setup(void)
{
	/* Register the URAM space as Node 1 */
	setup_bootmem_node(1, 0xe55f0000, 0xe5610000);
}
Commit	Line	Data
32351a28 PM	1	/*
	2	* SH7785 Setup
	3	*
	4	* Copyright (C) 2007 Paul Mundt
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10	#include <linux/platform_device.h>
	11	#include <linux/init.h>
	12	#include <linux/serial.h>
96de1a8f	13	#include <linux/serial_sci.h>
953c8ef2	14	#include <linux/io.h>
db250496	15	#include <linux/mm.h>
e367592c	16	#include <linux/sh_timer.h>
db250496	17	#include <asm/mmzone.h>
32351a28	18
e367592c MD	19	static struct sh_timer_config tmu0_platform_data = {
	20	.name = "TMU0",
	21	.channel_offset = 0x04,
	22	.timer_bit = 0,
549b5e35	23	.clk = "tmu012_fck",
e367592c MD	24	.clockevent_rating = 200,
	25	};
	26
	27	static struct resource tmu0_resources[] = {
	28	[0] = {
	29	.name = "TMU0",
	30	.start = 0xffd80008,
	31	.end = 0xffd80013,
	32	.flags = IORESOURCE_MEM,
	33	},
	34	[1] = {
	35	.start = 28,
	36	.flags = IORESOURCE_IRQ,
	37	},
	38	};
	39
	40	static struct platform_device tmu0_device = {
	41	.name = "sh_tmu",
	42	.id = 0,
	43	.dev = {
	44	.platform_data = &tmu0_platform_data,
	45	},
	46	.resource = tmu0_resources,
	47	.num_resources = ARRAY_SIZE(tmu0_resources),
	48	};
	49
	50	static struct sh_timer_config tmu1_platform_data = {
	51	.name = "TMU1",
	52	.channel_offset = 0x10,
	53	.timer_bit = 1,
549b5e35	54	.clk = "tmu012_fck",
e367592c MD	55	.clocksource_rating = 200,
	56	};
	57
	58	static struct resource tmu1_resources[] = {
	59	[0] = {
	60	.name = "TMU1",
	61	.start = 0xffd80014,
	62	.end = 0xffd8001f,
	63	.flags = IORESOURCE_MEM,
	64	},
	65	[1] = {
	66	.start = 29,
	67	.flags = IORESOURCE_IRQ,
	68	},
	69	};
	70
	71	static struct platform_device tmu1_device = {
	72	.name = "sh_tmu",
	73	.id = 1,
	74	.dev = {
	75	.platform_data = &tmu1_platform_data,
	76	},
	77	.resource = tmu1_resources,
	78	.num_resources = ARRAY_SIZE(tmu1_resources),
	79	};
	80
	81	static struct sh_timer_config tmu2_platform_data = {
	82	.name = "TMU2",
	83	.channel_offset = 0x1c,
	84	.timer_bit = 2,
549b5e35	85	.clk = "tmu012_fck",
e367592c MD	86	};
	87
	88	static struct resource tmu2_resources[] = {
	89	[0] = {
	90	.name = "TMU2",
	91	.start = 0xffd80020,
	92	.end = 0xffd8002f,
	93	.flags = IORESOURCE_MEM,
	94	},
	95	[1] = {
	96	.start = 30,
	97	.flags = IORESOURCE_IRQ,
	98	},
	99	};
	100
	101	static struct platform_device tmu2_device = {
	102	.name = "sh_tmu",
	103	.id = 2,
	104	.dev = {
	105	.platform_data = &tmu2_platform_data,
	106	},
	107	.resource = tmu2_resources,
	108	.num_resources = ARRAY_SIZE(tmu2_resources),
	109	};
	110
	111	static struct sh_timer_config tmu3_platform_data = {
	112	.name = "TMU3",
	113	.channel_offset = 0x04,
	114	.timer_bit = 0,
549b5e35	115	.clk = "tmu345_fck",
e367592c MD	116	};
	117
	118	static struct resource tmu3_resources[] = {
	119	[0] = {
	120	.name = "TMU3",
	121	.start = 0xffdc0008,
	122	.end = 0xffdc0013,
	123	.flags = IORESOURCE_MEM,
	124	},
	125	[1] = {
	126	.start = 96,
	127	.flags = IORESOURCE_IRQ,
	128	},
	129	};
	130
	131	static struct platform_device tmu3_device = {
	132	.name = "sh_tmu",
	133	.id = 3,
	134	.dev = {
	135	.platform_data = &tmu3_platform_data,
	136	},
	137	.resource = tmu3_resources,
	138	.num_resources = ARRAY_SIZE(tmu3_resources),
	139	};
	140
	141	static struct sh_timer_config tmu4_platform_data = {
	142	.name = "TMU4",
	143	.channel_offset = 0x10,
	144	.timer_bit = 1,
549b5e35	145	.clk = "tmu345_fck",
e367592c MD	146	};
	147
	148	static struct resource tmu4_resources[] = {
	149	[0] = {
	150	.name = "TMU4",
	151	.start = 0xffdc0014,
	152	.end = 0xffdc001f,
	153	.flags = IORESOURCE_MEM,
	154	},
	155	[1] = {
	156	.start = 97,
	157	.flags = IORESOURCE_IRQ,
	158	},
	159	};
	160
	161	static struct platform_device tmu4_device = {
	162	.name = "sh_tmu",
	163	.id = 4,
	164	.dev = {
	165	.platform_data = &tmu4_platform_data,
	166	},
	167	.resource = tmu4_resources,
	168	.num_resources = ARRAY_SIZE(tmu4_resources),
	169	};
	170
	171	static struct sh_timer_config tmu5_platform_data = {
	172	.name = "TMU5",
	173	.channel_offset = 0x1c,
	174	.timer_bit = 2,
549b5e35	175	.clk = "tmu345_fck",
e367592c MD	176	};
	177
	178	static struct resource tmu5_resources[] = {
	179	[0] = {
	180	.name = "TMU5",
	181	.start = 0xffdc0020,
	182	.end = 0xffdc002b,
	183	.flags = IORESOURCE_MEM,
	184	},
	185	[1] = {
	186	.start = 98,
	187	.flags = IORESOURCE_IRQ,
	188	},
	189	};
	190
	191	static struct platform_device tmu5_device = {
	192	.name = "sh_tmu",
	193	.id = 5,
	194	.dev = {
	195	.platform_data = &tmu5_platform_data,
	196	},
	197	.resource = tmu5_resources,
	198	.num_resources = ARRAY_SIZE(tmu5_resources),
	199	};
	200
32351a28 PM	201	static struct plat_sci_port sci_platform_data[] = {
	202	{
	203	.mapbase = 0xffea0000,
	204	.flags = UPF_BOOT_AUTOCONF,
	205	.type = PORT_SCIF,
57e41c86	206	.irqs = { 40, 40, 40, 40 },
549b5e35	207	.clk = "scif_fck",
32351a28 PM	208	}, {
	209	.mapbase = 0xffeb0000,
	210	.flags = UPF_BOOT_AUTOCONF,
	211	.type = PORT_SCIF,
57e41c86	212	.irqs = { 44, 44, 44, 44 },
549b5e35	213	.clk = "scif_fck",
57e41c86	214	}, {
32351a28 PM	215	.mapbase = 0xffec0000,
	216	.flags = UPF_BOOT_AUTOCONF,
	217	.type = PORT_SCIF,
	218	.irqs = { 60, 60, 60, 60 },
549b5e35	219	.clk = "scif_fck",
32351a28 PM	220	}, {
	221	.mapbase = 0xffed0000,
	222	.flags = UPF_BOOT_AUTOCONF,
	223	.type = PORT_SCIF,
	224	.irqs = { 61, 61, 61, 61 },
549b5e35	225	.clk = "scif_fck",
32351a28 PM	226	}, {
	227	.mapbase = 0xffee0000,
	228	.flags = UPF_BOOT_AUTOCONF,
	229	.type = PORT_SCIF,
	230	.irqs = { 62, 62, 62, 62 },
549b5e35	231	.clk = "scif_fck",
32351a28 PM	232	}, {
	233	.mapbase = 0xffef0000,
	234	.flags = UPF_BOOT_AUTOCONF,
	235	.type = PORT_SCIF,
	236	.irqs = { 63, 63, 63, 63 },
549b5e35	237	.clk = "scif_fck",
32351a28 PM	238	}, {
	239	.flags = 0,
	240	}
	241	};
	242
	243	static struct platform_device sci_device = {
	244	.name = "sh-sci",
	245	.id = -1,
	246	.dev = {
	247	.platform_data = sci_platform_data,
	248	},
	249	};
	250
	251	static struct platform_device *sh7785_devices[] __initdata = {
e367592c MD	252	&tmu0_device,
	253	&tmu1_device,
	254	&tmu2_device,
	255	&tmu3_device,
	256	&tmu4_device,
	257	&tmu5_device,
32351a28 PM	258	&sci_device,
	259	};
	260
	261	static int __init sh7785_devices_setup(void)
	262	{
	263	return platform_add_devices(sh7785_devices,
	264	ARRAY_SIZE(sh7785_devices));
	265	}
ba9a6337	266	arch_initcall(sh7785_devices_setup);
32351a28	267
e367592c MD	268	static struct platform_device *sh7785_early_devices[] __initdata = {
	269	&tmu0_device,
	270	&tmu1_device,
	271	&tmu2_device,
	272	&tmu3_device,
	273	&tmu4_device,
	274	&tmu5_device,
	275	};
	276
	277	void __init plat_early_device_setup(void)
	278	{
	279	early_platform_add_devices(sh7785_early_devices,
	280	ARRAY_SIZE(sh7785_early_devices));
	281	}
	282
a0e23267 MD	283	enum {
	284	UNUSED = 0,
	285
	286	/* interrupt sources */
	287
	288	IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
	289	IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
	290	IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
	291	IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
	292
	293	IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
	294	IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
	295	IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
	296	IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
	297
	298	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
57e41c86 MD	299	WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
57e41c86 MD	300	HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI,
a0e23267	301	SCIF2, SCIF3, SCIF4, SCIF5,
57e41c86 MD	302	PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
57e41c86 MD	303	SIOF, MMCIF, DU, GDTA,
a0e23267 MD	304	TMU3, TMU4, TMU5,
	305	SSI0, SSI1,
	306	HAC0, HAC1,
57e41c86	307	FLCTL, GPIO,
a0e23267 MD	308
	309	/* interrupt groups */
	310
57e41c86	311	TMU012, TMU345
32351a28 PM	312	};
32351a28 PM	313
5c37e025	314	static struct intc_vect vectors[] __initdata = {
a0e23267 MD	315	INTC_VECT(WDT, 0x560),
	316	INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
	317	INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
	318	INTC_VECT(HUDI, 0x600),
57e41c86 MD	319	INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
	320	INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
	321	INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
	322	INTC_VECT(DMAC0, 0x6e0),
	323	INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
	324	INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
	325	INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
	326	INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
	327	INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
	328	INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
	329	INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
	330	INTC_VECT(DMAC1, 0x940),
a0e23267 MD	331	INTC_VECT(HSPI, 0x960),
	332	INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
	333	INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
	334	INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
	335	INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
57e41c86 MD	336	INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
	337	INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
	338	INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
a0e23267	339	INTC_VECT(SIOF, 0xc00),
57e41c86 MD	340	INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
57e41c86 MD	341	INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
a0e23267	342	INTC_VECT(DU, 0xd80),
57e41c86 MD	343	INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
57e41c86 MD	344	INTC_VECT(GDTA, 0xde0),
a0e23267 MD	345	INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
	346	INTC_VECT(TMU5, 0xe40),
	347	INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
	348	INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
57e41c86 MD	349	INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
	350	INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
	351	INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
	352	INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
a0e23267	353	};
d619500a	354
5c37e025	355	static struct intc_group groups[] __initdata = {
a0e23267	356	INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
a0e23267	357	INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
a0e23267	358	};
d619500a	359
5c37e025	360	static struct intc_mask_reg mask_registers[] __initdata = {
a0e23267 MD	361	{ 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
	362	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	363
	364	{ 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
	365	{ IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
	366	IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
	367	IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
	368	IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
	369	IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
	370	IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
	371	IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
	372	IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
	373
	374	{ 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
	375	{ 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
	376	FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
	377	PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
	378	SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
	379	};
	380
5c37e025	381	static struct intc_prio_reg prio_registers[] __initdata = {
6ef5fb2c MD	382	{ 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
	383	IRQ4, IRQ5, IRQ6, IRQ7 } },
	384	{ 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
	385	TMU2, TMU2_TICPI } },
	386	{ 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
	387	{ 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1,
	388	SCIF2, SCIF3 } },
	389	{ 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
	390	{ 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
	391	{ 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1,
	392	PCISERR, PCIINTA } },
	393	{ 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
	394	PCIINTD, PCIC5 } },
	395	{ 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
	396	{ 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
	397	{ 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
a0e23267 MD	398	};
a0e23267 MD	399
7f3edee8	400	static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups,
a0e23267 MD	401	mask_registers, prio_registers, NULL);
a0e23267 MD	402
a0e23267 MD	403	/* Support for external interrupt pins in IRQ mode */
a0e23267 MD	404
5c37e025	405	static struct intc_vect vectors_irq0123[] __initdata = {
a0e23267 MD	406	INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
	407	INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
	408	};
	409
5c37e025	410	static struct intc_vect vectors_irq4567[] __initdata = {
a0e23267 MD	411	INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
	412	INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
	413	};
	414
5c37e025	415	static struct intc_sense_reg sense_registers[] __initdata = {
a0e23267 MD	416	{ 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
	417	IRQ4, IRQ5, IRQ6, IRQ7 } },
	418	};
	419
6bdfb22a YS	420	static struct intc_mask_reg ack_registers[] __initdata = {
	421	{ 0xffd00024, 0, 32, /* INTREQ */
	422	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	423	};
	424
	425	static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7785-irq0123",
	426	vectors_irq0123, NULL, mask_registers,
	427	prio_registers, sense_registers, ack_registers);
a0e23267	428
6bdfb22a YS	429	static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7785-irq4567",
	430	vectors_irq4567, NULL, mask_registers,
	431	prio_registers, sense_registers, ack_registers);
a0e23267 MD	432
	433	/* External interrupt pins in IRL mode */
	434
5c37e025	435	static struct intc_vect vectors_irl0123[] __initdata = {
a0e23267 MD	436	INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
	437	INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
	438	INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
	439	INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
	440	INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
	441	INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
	442	INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
	443	INTC_VECT(IRL0_HHHL, 0x3c0),
d619500a MD	444	};
d619500a MD	445
5c37e025	446	static struct intc_vect vectors_irl4567[] __initdata = {
a0e23267 MD	447	INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
	448	INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
	449	INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
	450	INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
	451	INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
	452	INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
	453	INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
	454	INTC_VECT(IRL4_HHHL, 0xcc0),
	455	};
	456
	457	static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
7f3edee8	458	NULL, mask_registers, NULL, NULL);
a0e23267 MD	459
a0e23267 MD	460	static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
7f3edee8	461	NULL, mask_registers, NULL, NULL);
a0e23267	462
953c8ef2 MD	463	#define INTC_ICR0 0xffd00000
	464	#define INTC_INTMSK0 0xffd00044
	465	#define INTC_INTMSK1 0xffd00048
	466	#define INTC_INTMSK2 0xffd40080
	467	#define INTC_INTMSKCLR1 0xffd00068
	468	#define INTC_INTMSKCLR2 0xffd40084
	469
90015c89	470	void __init plat_irq_setup(void)
32351a28	471	{
953c8ef2 MD	472	/* disable IRQ3-0 + IRQ7-4 */
	473	ctrl_outl(0xff000000, INTC_INTMSK0);
	474
	475	/* disable IRL3-0 + IRL7-4 */
	476	ctrl_outl(0xc0000000, INTC_INTMSK1);
	477	ctrl_outl(0xfffefffe, INTC_INTMSK2);
	478
	479	/* select IRL mode for IRL3-0 + IRL7-4 */
	480	ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
	481
	482	/* disable holding function, ie enable "SH-4 Mode" */
	483	ctrl_outl(ctrl_inl(INTC_ICR0) \| 0x00200000, INTC_ICR0);
	484
a0e23267	485	register_intc_controller(&intc_desc);
32351a28	486	}
d619500a	487
a0e23267 MD	488	void __init plat_irq_setup_pins(int mode)
	489	{
	490	switch (mode) {
	491	case IRQ_MODE_IRQ7654:
953c8ef2 MD	492	/* select IRQ mode for IRL7-4 */
953c8ef2 MD	493	ctrl_outl(ctrl_inl(INTC_ICR0) \| 0x00400000, INTC_ICR0);
a0e23267 MD	494	register_intc_controller(&intc_desc_irq4567);
	495	break;
	496	case IRQ_MODE_IRQ3210:
953c8ef2 MD	497	/* select IRQ mode for IRL3-0 */
953c8ef2 MD	498	ctrl_outl(ctrl_inl(INTC_ICR0) \| 0x00800000, INTC_ICR0);
a0e23267 MD	499	register_intc_controller(&intc_desc_irq0123);
	500	break;
	501	case IRQ_MODE_IRL7654:
953c8ef2 MD	502	/* enable IRL7-4 but don't provide any masking */
	503	ctrl_outl(0x40000000, INTC_INTMSKCLR1);
	504	ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
a0e23267 MD	505	break;
a0e23267 MD	506	case IRQ_MODE_IRL3210:
953c8ef2 MD	507	/* enable IRL0-3 but don't provide any masking */
	508	ctrl_outl(0x80000000, INTC_INTMSKCLR1);
	509	ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
	510	break;
	511	case IRQ_MODE_IRL7654_MASK:
	512	/* enable IRL7-4 and mask using cpu intc controller */
	513	ctrl_outl(0x40000000, INTC_INTMSKCLR1);
	514	register_intc_controller(&intc_desc_irl4567);
	515	break;
	516	case IRQ_MODE_IRL3210_MASK:
	517	/* enable IRL0-3 and mask using cpu intc controller */
	518	ctrl_outl(0x80000000, INTC_INTMSKCLR1);
a0e23267 MD	519	register_intc_controller(&intc_desc_irl0123);
	520	break;
	521	default:
	522	BUG();
	523	}
	524	}
db250496 PM	525
	526	void __init plat_mem_setup(void)
	527	{
	528	/* Register the URAM space as Node 1 */
675bd780	529	setup_bootmem_node(1, 0xe55f0000, 0xe5610000);
db250496	530	}