[linux-block.git] / arch / sh / kernel / cpu / sh4a / setup-sh7722.c

/*
 * SH7722 Setup
 *
 *  Copyright (C) 2006 - 2008  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/serial_sci.h>
#include <linux/mm.h>
#include <linux/uio_driver.h>
#include <asm/clock.h>
#include <asm/mmzone.h>

static struct resource rtc_resources[] = {
	[0] = {
		.start	= 0xa465fec0,
		.end	= 0xa465fec0 + 0x58 - 1,
		.flags	= IORESOURCE_IO,
	},
	[1] = {
		/* Period IRQ */
		.start	= 45,
		.flags	= IORESOURCE_IRQ,
	},
	[2] = {
		/* Carry IRQ */
		.start	= 46,
		.flags	= IORESOURCE_IRQ,
	},
	[3] = {
		/* Alarm IRQ */
		.start	= 44,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device rtc_device = {
	.name		= "sh-rtc",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(rtc_resources),
	.resource	= rtc_resources,
};

static struct resource usbf_resources[] = {
	[0] = {
		.name	= "m66592_udc",
		.start	= 0x04480000,
		.end	= 0x044800FF,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 65,
		.end	= 65,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device usbf_device = {
	.name		= "m66592_udc",
	.id             = 0, /* "usbf0" clock */
	.dev = {
		.dma_mask		= NULL,
		.coherent_dma_mask	= 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(usbf_resources),
	.resource	= usbf_resources,
};

static struct resource iic_resources[] = {
	[0] = {
		.name	= "IIC",
		.start  = 0x04470000,
		.end    = 0x04470017,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = 96,
		.end    = 99,
		.flags  = IORESOURCE_IRQ,
       },
};

static struct platform_device iic_device = {
	.name           = "i2c-sh_mobile",
	.id             = 0, /* "i2c0" clock */
	.num_resources  = ARRAY_SIZE(iic_resources),
	.resource       = iic_resources,
};

static struct uio_info vpu_platform_data = {
	.name = "VPU4",
	.version = "0",
	.irq = 60,
};

static struct resource vpu_resources[] = {
	[0] = {
		.name	= "VPU",
		.start	= 0xfe900000,
		.end	= 0xfe9022eb,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device vpu_device = {
	.name		= "uio_pdrv_genirq",
	.id		= 0,
	.dev = {
		.platform_data	= &vpu_platform_data,
	},
	.resource	= vpu_resources,
	.num_resources	= ARRAY_SIZE(vpu_resources),
};

static struct uio_info veu_platform_data = {
	.name = "VEU",
	.version = "0",
	.irq = 54,
};

static struct resource veu_resources[] = {
	[0] = {
		.name	= "VEU",
		.start	= 0xfe920000,
		.end	= 0xfe9200b7,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device veu_device = {
	.name		= "uio_pdrv_genirq",
	.id		= 1,
	.dev = {
		.platform_data	= &veu_platform_data,
	},
	.resource	= veu_resources,
	.num_resources	= ARRAY_SIZE(veu_resources),
};

static struct plat_sci_port sci_platform_data[] = {
	{
		.mapbase	= 0xffe00000,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIF,
		.irqs		= { 80, 80, 80, 80 },
	},
	{
		.mapbase	= 0xffe10000,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIF,
		.irqs		= { 81, 81, 81, 81 },
	},
	{
		.mapbase	= 0xffe20000,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIF,
		.irqs		= { 82, 82, 82, 82 },
	},
	{
		.flags = 0,
	}
};

static struct platform_device sci_device = {
	.name		= "sh-sci",
	.id		= -1,
	.dev		= {
		.platform_data	= sci_platform_data,
	},
};

static struct platform_device *sh7722_devices[] __initdata = {
	&rtc_device,
	&usbf_device,
	&iic_device,
	&sci_device,
	&vpu_device,
	&veu_device,
};

static int __init sh7722_devices_setup(void)
{
	clk_always_enable("uram0"); /* URAM */
	clk_always_enable("xymem0"); /* XYMEM */
	clk_always_enable("rtc0"); /* RTC */
	clk_always_enable("veu0"); /* VEU */
	clk_always_enable("vpu0"); /* VPU */

	platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
	platform_resource_setup_memory(&veu_device, "veu", 2 << 20);

	return platform_add_devices(sh7722_devices,
				    ARRAY_SIZE(sh7722_devices));
}
__initcall(sh7722_devices_setup);

enum {
	UNUSED=0,

	/* interrupt sources */
	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	HUDI,
	SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
	RTC_ATI, RTC_PRI, RTC_CUI,
	DMAC0, DMAC1, DMAC2, DMAC3,
	VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
	VPU, TPU,
	USB_USBI0, USB_USBI1,
	DMAC4, DMAC5, DMAC_DADERR,
	KEYSC,
	SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
	FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
	I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
	SDHI0, SDHI1, SDHI2, SDHI3,
	CMT, TSIF, SIU, TWODG,
	TMU0, TMU1, TMU2,
	IRDA, JPU, LCDC,

	/* interrupt groups */
	SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
};

static struct intc_vect vectors[] __initdata = {
	INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
	INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
	INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
	INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
	INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
	INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
	INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
	INTC_VECT(RTC_CUI, 0x7c0),
	INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
	INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
	INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
	INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
	INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
	INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
	INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
	INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
	INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
	INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
	INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
	INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
	INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
	INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
	INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
	INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
	INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
	INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
	INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
	INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
	INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
};

static struct intc_group groups[] __initdata = {
	INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
	INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
	INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
	INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
	INTC_GROUP(USB, USB_USBI0, USB_USBI1),
	INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
	INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
		   FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
	INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
	INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
};

static struct intc_mask_reg mask_registers[] __initdata = {
	{ 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
	  { } },
	{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
	  { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
	{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
	  { 0, 0, 0, VPU, } },
	{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
	  { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
	{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
	  { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
	{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
	  { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
	{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
	  { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
	{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
	  { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
	    FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
	{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
	  { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, TWODG, SIU } },
	{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
	  { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
	{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
	  { } },
	{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
	  { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
	{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_prio_reg prio_registers[] __initdata = {
	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
	{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
	{ 0xa4080008, 0, 16, 4, /* IPRC */ { } },
	{ 0xa408000c, 0, 16, 4, /* IPRD */ { } },
	{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
	{ 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
	{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
	{ 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
	{ 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
	{ 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
	{ 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
	{ 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
	{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_sense_reg sense_registers[] __initdata = {
	{ 0xa414001c, 16, 2, /* ICR1 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_mask_reg ack_registers[] __initdata = {
	{ 0xa4140024, 0, 8, /* INTREQ00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static DECLARE_INTC_DESC_ACK(intc_desc, "sh7722", vectors, groups,
			     mask_registers, prio_registers, sense_registers,
			     ack_registers);

void __init plat_irq_setup(void)
{
	register_intc_controller(&intc_desc);
}

void __init plat_mem_setup(void)
{
	/* Register the URAM space as Node 1 */
	setup_bootmem_node(1, 0x055f0000, 0x05610000);
}
Commit	Line	Data
41504c39 PM	1	/*
	2	* SH7722 Setup
	3	*
b4d36a25	4	* Copyright (C) 2006 - 2008 Paul Mundt
41504c39 PM	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10	#include <linux/platform_device.h>
	11	#include <linux/init.h>
	12	#include <linux/serial.h>
96de1a8f	13	#include <linux/serial_sci.h>
520588f4	14	#include <linux/mm.h>
a55f6d25	15	#include <linux/uio_driver.h>
6c7d826c	16	#include <asm/clock.h>
5bbeafca	17	#include <asm/mmzone.h>
41504c39	18
b4d36a25 PM	19	static struct resource rtc_resources[] = {
	20	[0] = {
	21	.start = 0xa465fec0,
	22	.end = 0xa465fec0 + 0x58 - 1,
	23	.flags = IORESOURCE_IO,
	24	},
	25	[1] = {
	26	/* Period IRQ */
	27	.start = 45,
	28	.flags = IORESOURCE_IRQ,
	29	},
	30	[2] = {
	31	/* Carry IRQ */
	32	.start = 46,
	33	.flags = IORESOURCE_IRQ,
	34	},
	35	[3] = {
	36	/* Alarm IRQ */
	37	.start = 44,
	38	.flags = IORESOURCE_IRQ,
	39	},
	40	};
	41
	42	static struct platform_device rtc_device = {
	43	.name = "sh-rtc",
	44	.id = -1,
	45	.num_resources = ARRAY_SIZE(rtc_resources),
	46	.resource = rtc_resources,
	47	};
	48
262feaa0 YS	49	static struct resource usbf_resources[] = {
262feaa0 YS	50	[0] = {
526c1c23	51	.name = "m66592_udc",
a0d29798 MD	52	.start = 0x04480000,
a0d29798 MD	53	.end = 0x044800FF,
262feaa0 YS	54	.flags = IORESOURCE_MEM,
	55	},
	56	[1] = {
262feaa0 YS	57	.start = 65,
	58	.end = 65,
	59	.flags = IORESOURCE_IRQ,
	60	},
	61	};
	62
	63	static struct platform_device usbf_device = {
	64	.name = "m66592_udc",
af5be79a	65	.id = 0, /* "usbf0" clock */
262feaa0 YS	66	.dev = {
	67	.dma_mask = NULL,
	68	.coherent_dma_mask = 0xffffffff,
	69	},
	70	.num_resources = ARRAY_SIZE(usbf_resources),
	71	.resource = usbf_resources,
	72	};
	73
ef1b2327 MD	74	static struct resource iic_resources[] = {
	75	[0] = {
	76	.name = "IIC",
	77	.start = 0x04470000,
	78	.end = 0x04470017,
	79	.flags = IORESOURCE_MEM,
	80	},
	81	[1] = {
	82	.start = 96,
	83	.end = 99,
	84	.flags = IORESOURCE_IRQ,
	85	},
	86	};
	87
	88	static struct platform_device iic_device = {
	89	.name = "i2c-sh_mobile",
a5616bd0	90	.id = 0, /* "i2c0" clock */
ef1b2327 MD	91	.num_resources = ARRAY_SIZE(iic_resources),
	92	.resource = iic_resources,
	93	};
	94
a55f6d25 MD	95	static struct uio_info vpu_platform_data = {
	96	.name = "VPU4",
	97	.version = "0",
	98	.irq = 60,
	99	};
	100
	101	static struct resource vpu_resources[] = {
	102	[0] = {
	103	.name = "VPU",
	104	.start = 0xfe900000,
	105	.end = 0xfe9022eb,
	106	.flags = IORESOURCE_MEM,
	107	},
1eca5c92 MD	108	[1] = {
	109	/* place holder for contiguous memory */
	110	},
a55f6d25 MD	111	};
	112
	113	static struct platform_device vpu_device = {
	114	.name = "uio_pdrv_genirq",
	115	.id = 0,
	116	.dev = {
	117	.platform_data = &vpu_platform_data,
	118	},
	119	.resource = vpu_resources,
	120	.num_resources = ARRAY_SIZE(vpu_resources),
	121	};
	122
	123	static struct uio_info veu_platform_data = {
	124	.name = "VEU",
	125	.version = "0",
	126	.irq = 54,
	127	};
	128
	129	static struct resource veu_resources[] = {
	130	[0] = {
	131	.name = "VEU",
	132	.start = 0xfe920000,
	133	.end = 0xfe9200b7,
	134	.flags = IORESOURCE_MEM,
	135	},
1eca5c92 MD	136	[1] = {
	137	/* place holder for contiguous memory */
	138	},
a55f6d25 MD	139	};
	140
	141	static struct platform_device veu_device = {
	142	.name = "uio_pdrv_genirq",
	143	.id = 1,
	144	.dev = {
	145	.platform_data = &veu_platform_data,
	146	},
	147	.resource = veu_resources,
	148	.num_resources = ARRAY_SIZE(veu_resources),
	149	};
	150
41504c39 PM	151	static struct plat_sci_port sci_platform_data[] = {
	152	{
	153	.mapbase = 0xffe00000,
	154	.flags = UPF_BOOT_AUTOCONF,
	155	.type = PORT_SCIF,
53aba19f MD	156	.irqs = { 80, 80, 80, 80 },
	157	},
	158	{
	159	.mapbase = 0xffe10000,
	160	.flags = UPF_BOOT_AUTOCONF,
	161	.type = PORT_SCIF,
	162	.irqs = { 81, 81, 81, 81 },
	163	},
	164	{
	165	.mapbase = 0xffe20000,
	166	.flags = UPF_BOOT_AUTOCONF,
	167	.type = PORT_SCIF,
	168	.irqs = { 82, 82, 82, 82 },
	169	},
	170	{
41504c39 PM	171	.flags = 0,
	172	}
	173	};
	174
	175	static struct platform_device sci_device = {
	176	.name = "sh-sci",
	177	.id = -1,
	178	.dev = {
	179	.platform_data = sci_platform_data,
	180	},
	181	};
	182
	183	static struct platform_device *sh7722_devices[] __initdata = {
b4d36a25	184	&rtc_device,
262feaa0	185	&usbf_device,
ef1b2327	186	&iic_device,
41504c39	187	&sci_device,
a55f6d25 MD	188	&vpu_device,
a55f6d25 MD	189	&veu_device,
41504c39 PM	190	};
	191
	192	static int __init sh7722_devices_setup(void)
	193	{
ef6aff68 MD	194	clk_always_enable("uram0"); /* URAM */
	195	clk_always_enable("xymem0"); /* XYMEM */
	196	clk_always_enable("rtc0"); /* RTC */
	197	clk_always_enable("veu0"); /* VEU */
	198	clk_always_enable("vpu0"); /* VPU */
6c7d826c	199
1eca5c92 MD	200	platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
1eca5c92 MD	201	platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
6c7d826c	202
41504c39 PM	203	return platform_add_devices(sh7722_devices,
	204	ARRAY_SIZE(sh7722_devices));
	205	}
	206	__initcall(sh7722_devices_setup);
	207
1b06428e MD	208	enum {
	209	UNUSED=0,
	210
	211	/* interrupt sources */
	212	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	213	HUDI,
	214	SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
	215	RTC_ATI, RTC_PRI, RTC_CUI,
	216	DMAC0, DMAC1, DMAC2, DMAC3,
	217	VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
	218	VPU, TPU,
	219	USB_USBI0, USB_USBI1,
	220	DMAC4, DMAC5, DMAC_DADERR,
	221	KEYSC,
	222	SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
	223	FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
	224	I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
	225	SDHI0, SDHI1, SDHI2, SDHI3,
	226	CMT, TSIF, SIU, TWODG,
	227	TMU0, TMU1, TMU2,
	228	IRDA, JPU, LCDC,
	229
	230	/* interrupt groups */
1b06428e	231	SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
41504c39 PM	232	};
41504c39 PM	233
5c37e025	234	static struct intc_vect vectors[] __initdata = {
1b06428e MD	235	INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
	236	INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
	237	INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
	238	INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
	239	INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
	240	INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
	241	INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
	242	INTC_VECT(RTC_CUI, 0x7c0),
	243	INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
	244	INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
	245	INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
	246	INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
	247	INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
	248	INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
	249	INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
	250	INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
	251	INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
	252	INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
	253	INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
	254	INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
	255	INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
	256	INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
	257	INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
	258	INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
	259	INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
	260	INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
	261	INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
	262	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
	263	INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
	264	INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
41504c39 PM	265	};
41504c39 PM	266
5c37e025	267	static struct intc_group groups[] __initdata = {
1b06428e MD	268	INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
	269	INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
	270	INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
	271	INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
	272	INTC_GROUP(USB, USB_USBI0, USB_USBI1),
	273	INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
	274	INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
	275	FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
	276	INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
	277	INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
	278	};
68abdbbb	279
5c37e025	280	static struct intc_mask_reg mask_registers[] __initdata = {
1b06428e MD	281	{ 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
	282	{ } },
	283	{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
	284	{ VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
	285	{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
	286	{ 0, 0, 0, VPU, } },
	287	{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
	288	{ SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
	289	{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
	290	{ 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
	291	{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
	292	{ KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
	293	{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
	294	{ 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
	295	{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
	296	{ I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
	297	FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
	298	{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
	299	{ SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, TWODG, SIU } },
	300	{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
	301	{ 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
	302	{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
	303	{ } },
	304	{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
	305	{ 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
	306	{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
	307	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
68abdbbb	308	};
41504c39	309
5c37e025	310	static struct intc_prio_reg prio_registers[] __initdata = {
6ef5fb2c MD	311	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
	312	{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
	313	{ 0xa4080008, 0, 16, 4, /* IPRC */ { } },
	314	{ 0xa408000c, 0, 16, 4, /* IPRD */ { } },
	315	{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
	316	{ 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
	317	{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
	318	{ 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
	319	{ 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
	320	{ 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
	321	{ 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
	322	{ 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
	323	{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
1b06428e MD	324	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	325	};
	326
5c37e025	327	static struct intc_sense_reg sense_registers[] __initdata = {
1b06428e MD	328	{ 0xa414001c, 16, 2, /* ICR1 */
	329	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	330	};
	331
6bdfb22a YS	332	static struct intc_mask_reg ack_registers[] __initdata = {
	333	{ 0xa4140024, 0, 8, /* INTREQ00 */
	334	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	335	};
	336
	337	static DECLARE_INTC_DESC_ACK(intc_desc, "sh7722", vectors, groups,
	338	mask_registers, prio_registers, sense_registers,
	339	ack_registers);
1b06428e	340
90015c89	341	void __init plat_irq_setup(void)
41504c39	342	{
1b06428e	343	register_intc_controller(&intc_desc);
41504c39	344	}
520588f4 PM	345
	346	void __init plat_mem_setup(void)
	347	{
	348	/* Register the URAM space as Node 1 */
	349	setup_bootmem_node(1, 0x055f0000, 0x05610000);
	350	}