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add5ca2c | 1 | // SPDX-License-Identifier: GPL-2.0 |
41504c39 PM |
2 | /* |
3 | * SH7722 Setup | |
4 | * | |
b4d36a25 | 5 | * Copyright (C) 2006 - 2008 Paul Mundt |
41504c39 | 6 | */ |
41504c39 | 7 | #include <linux/init.h> |
8b1935e6 GL |
8 | #include <linux/mm.h> |
9 | #include <linux/platform_device.h> | |
41504c39 | 10 | #include <linux/serial.h> |
96de1a8f | 11 | #include <linux/serial_sci.h> |
08298f06 | 12 | #include <linux/sh_dma.h> |
8b1935e6 | 13 | #include <linux/sh_timer.h> |
29b53e37 | 14 | #include <linux/sh_intc.h> |
a55f6d25 | 15 | #include <linux/uio_driver.h> |
2c59b0b7 | 16 | #include <linux/usb/m66592.h> |
8b1935e6 | 17 | |
6c7d826c | 18 | #include <asm/clock.h> |
5bbeafca | 19 | #include <asm/mmzone.h> |
331af0c1 | 20 | #include <asm/siu.h> |
507fd01d | 21 | #include <asm/platform_early.h> |
8b1935e6 GL |
22 | |
23 | #include <cpu/dma-register.h> | |
f69d5782 | 24 | #include <cpu/sh7722.h> |
08ef2e42 | 25 | #include <cpu/serial.h> |
41504c39 | 26 | |
5bac942d | 27 | static const struct sh_dmae_slave_config sh7722_dmae_slaves[] = { |
331af0c1 GL |
28 | { |
29 | .slave_id = SHDMA_SLAVE_SCIF0_TX, | |
30 | .addr = 0xffe0000c, | |
28564f08 | 31 | .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), |
331af0c1 GL |
32 | .mid_rid = 0x21, |
33 | }, { | |
34 | .slave_id = SHDMA_SLAVE_SCIF0_RX, | |
35 | .addr = 0xffe00014, | |
28564f08 | 36 | .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), |
331af0c1 GL |
37 | .mid_rid = 0x22, |
38 | }, { | |
39 | .slave_id = SHDMA_SLAVE_SCIF1_TX, | |
40 | .addr = 0xffe1000c, | |
28564f08 | 41 | .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), |
331af0c1 GL |
42 | .mid_rid = 0x25, |
43 | }, { | |
44 | .slave_id = SHDMA_SLAVE_SCIF1_RX, | |
45 | .addr = 0xffe10014, | |
28564f08 | 46 | .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), |
331af0c1 GL |
47 | .mid_rid = 0x26, |
48 | }, { | |
49 | .slave_id = SHDMA_SLAVE_SCIF2_TX, | |
50 | .addr = 0xffe2000c, | |
28564f08 | 51 | .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), |
331af0c1 GL |
52 | .mid_rid = 0x29, |
53 | }, { | |
54 | .slave_id = SHDMA_SLAVE_SCIF2_RX, | |
55 | .addr = 0xffe20014, | |
28564f08 | 56 | .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), |
331af0c1 GL |
57 | .mid_rid = 0x2a, |
58 | }, { | |
59 | .slave_id = SHDMA_SLAVE_SIUA_TX, | |
60 | .addr = 0xa454c098, | |
28564f08 | 61 | .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), |
331af0c1 GL |
62 | .mid_rid = 0xb1, |
63 | }, { | |
64 | .slave_id = SHDMA_SLAVE_SIUA_RX, | |
65 | .addr = 0xa454c090, | |
28564f08 | 66 | .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), |
331af0c1 GL |
67 | .mid_rid = 0xb2, |
68 | }, { | |
69 | .slave_id = SHDMA_SLAVE_SIUB_TX, | |
70 | .addr = 0xa454c09c, | |
28564f08 | 71 | .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), |
331af0c1 GL |
72 | .mid_rid = 0xb5, |
73 | }, { | |
74 | .slave_id = SHDMA_SLAVE_SIUB_RX, | |
75 | .addr = 0xa454c094, | |
28564f08 | 76 | .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), |
331af0c1 | 77 | .mid_rid = 0xb6, |
afd46501 GL |
78 | }, { |
79 | .slave_id = SHDMA_SLAVE_SDHI0_TX, | |
80 | .addr = 0x04ce0030, | |
28564f08 | 81 | .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT), |
afd46501 GL |
82 | .mid_rid = 0xc1, |
83 | }, { | |
84 | .slave_id = SHDMA_SLAVE_SDHI0_RX, | |
85 | .addr = 0x04ce0030, | |
28564f08 | 86 | .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT), |
afd46501 | 87 | .mid_rid = 0xc2, |
331af0c1 GL |
88 | }, |
89 | }; | |
90 | ||
5bac942d | 91 | static const struct sh_dmae_channel sh7722_dmae_channels[] = { |
027811b9 GL |
92 | { |
93 | .offset = 0, | |
94 | .dmars = 0, | |
95 | .dmars_bit = 0, | |
96 | }, { | |
97 | .offset = 0x10, | |
98 | .dmars = 0, | |
99 | .dmars_bit = 8, | |
100 | }, { | |
101 | .offset = 0x20, | |
102 | .dmars = 4, | |
103 | .dmars_bit = 0, | |
104 | }, { | |
105 | .offset = 0x30, | |
106 | .dmars = 4, | |
107 | .dmars_bit = 8, | |
108 | }, { | |
109 | .offset = 0x50, | |
110 | .dmars = 8, | |
111 | .dmars_bit = 0, | |
112 | }, { | |
113 | .offset = 0x60, | |
114 | .dmars = 8, | |
115 | .dmars_bit = 8, | |
116 | } | |
117 | }; | |
118 | ||
5bac942d | 119 | static const unsigned int ts_shift[] = TS_SHIFT; |
8b1935e6 | 120 | |
331af0c1 | 121 | static struct sh_dmae_pdata dma_platform_data = { |
027811b9 GL |
122 | .slave = sh7722_dmae_slaves, |
123 | .slave_num = ARRAY_SIZE(sh7722_dmae_slaves), | |
124 | .channel = sh7722_dmae_channels, | |
125 | .channel_num = ARRAY_SIZE(sh7722_dmae_channels), | |
8b1935e6 GL |
126 | .ts_low_shift = CHCR_TS_LOW_SHIFT, |
127 | .ts_low_mask = CHCR_TS_LOW_MASK, | |
128 | .ts_high_shift = CHCR_TS_HIGH_SHIFT, | |
129 | .ts_high_mask = CHCR_TS_HIGH_MASK, | |
130 | .ts_shift = ts_shift, | |
131 | .ts_shift_num = ARRAY_SIZE(ts_shift), | |
132 | .dmaor_init = DMAOR_INIT, | |
027811b9 GL |
133 | }; |
134 | ||
135 | static struct resource sh7722_dmae_resources[] = { | |
136 | [0] = { | |
137 | /* Channel registers and DMAOR */ | |
138 | .start = 0xfe008020, | |
139 | .end = 0xfe00808f, | |
140 | .flags = IORESOURCE_MEM, | |
141 | }, | |
142 | [1] = { | |
143 | /* DMARSx */ | |
144 | .start = 0xfe009000, | |
145 | .end = 0xfe00900b, | |
146 | .flags = IORESOURCE_MEM, | |
147 | }, | |
148 | { | |
a4d52473 | 149 | .name = "error_irq", |
29b53e37 PM |
150 | .start = evt2irq(0xbc0), |
151 | .end = evt2irq(0xbc0), | |
027811b9 GL |
152 | .flags = IORESOURCE_IRQ, |
153 | }, | |
154 | { | |
155 | /* IRQ for channels 0-3 */ | |
29b53e37 PM |
156 | .start = evt2irq(0x800), |
157 | .end = evt2irq(0x860), | |
027811b9 GL |
158 | .flags = IORESOURCE_IRQ, |
159 | }, | |
160 | { | |
161 | /* IRQ for channels 4-5 */ | |
29b53e37 PM |
162 | .start = evt2irq(0xb80), |
163 | .end = evt2irq(0xba0), | |
027811b9 GL |
164 | .flags = IORESOURCE_IRQ, |
165 | }, | |
331af0c1 GL |
166 | }; |
167 | ||
168 | struct platform_device dma_device = { | |
169 | .name = "sh-dma-engine", | |
170 | .id = -1, | |
027811b9 GL |
171 | .resource = sh7722_dmae_resources, |
172 | .num_resources = ARRAY_SIZE(sh7722_dmae_resources), | |
331af0c1 GL |
173 | .dev = { |
174 | .platform_data = &dma_platform_data, | |
175 | }, | |
176 | }; | |
177 | ||
bcac24d0 MD |
178 | /* Serial */ |
179 | static struct plat_sci_port scif0_platform_data = { | |
c3fa400b | 180 | .scscr = SCSCR_REIE, |
bcac24d0 | 181 | .type = PORT_SCIF, |
61a6976b PM |
182 | .ops = &sh7722_sci_port_ops, |
183 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | |
bcac24d0 MD |
184 | }; |
185 | ||
d850acf9 LP |
186 | static struct resource scif0_resources[] = { |
187 | DEFINE_RES_MEM(0xffe00000, 0x100), | |
188 | DEFINE_RES_IRQ(evt2irq(0xc00)), | |
189 | }; | |
190 | ||
bcac24d0 MD |
191 | static struct platform_device scif0_device = { |
192 | .name = "sh-sci", | |
193 | .id = 0, | |
d850acf9 LP |
194 | .resource = scif0_resources, |
195 | .num_resources = ARRAY_SIZE(scif0_resources), | |
bcac24d0 MD |
196 | .dev = { |
197 | .platform_data = &scif0_platform_data, | |
198 | }, | |
199 | }; | |
200 | ||
201 | static struct plat_sci_port scif1_platform_data = { | |
c3fa400b | 202 | .scscr = SCSCR_REIE, |
bcac24d0 | 203 | .type = PORT_SCIF, |
61a6976b PM |
204 | .ops = &sh7722_sci_port_ops, |
205 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | |
bcac24d0 MD |
206 | }; |
207 | ||
d850acf9 LP |
208 | static struct resource scif1_resources[] = { |
209 | DEFINE_RES_MEM(0xffe10000, 0x100), | |
210 | DEFINE_RES_IRQ(evt2irq(0xc20)), | |
211 | }; | |
212 | ||
bcac24d0 MD |
213 | static struct platform_device scif1_device = { |
214 | .name = "sh-sci", | |
215 | .id = 1, | |
d850acf9 LP |
216 | .resource = scif1_resources, |
217 | .num_resources = ARRAY_SIZE(scif1_resources), | |
bcac24d0 MD |
218 | .dev = { |
219 | .platform_data = &scif1_platform_data, | |
220 | }, | |
221 | }; | |
222 | ||
223 | static struct plat_sci_port scif2_platform_data = { | |
c3fa400b | 224 | .scscr = SCSCR_REIE, |
bcac24d0 | 225 | .type = PORT_SCIF, |
61a6976b PM |
226 | .ops = &sh7722_sci_port_ops, |
227 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | |
bcac24d0 MD |
228 | }; |
229 | ||
d850acf9 LP |
230 | static struct resource scif2_resources[] = { |
231 | DEFINE_RES_MEM(0xffe20000, 0x100), | |
232 | DEFINE_RES_IRQ(evt2irq(0xc40)), | |
233 | }; | |
234 | ||
bcac24d0 MD |
235 | static struct platform_device scif2_device = { |
236 | .name = "sh-sci", | |
237 | .id = 2, | |
d850acf9 LP |
238 | .resource = scif2_resources, |
239 | .num_resources = ARRAY_SIZE(scif2_resources), | |
bcac24d0 MD |
240 | .dev = { |
241 | .platform_data = &scif2_platform_data, | |
242 | }, | |
243 | }; | |
244 | ||
b4d36a25 PM |
245 | static struct resource rtc_resources[] = { |
246 | [0] = { | |
247 | .start = 0xa465fec0, | |
248 | .end = 0xa465fec0 + 0x58 - 1, | |
249 | .flags = IORESOURCE_IO, | |
250 | }, | |
251 | [1] = { | |
252 | /* Period IRQ */ | |
29b53e37 | 253 | .start = evt2irq(0x7a0), |
b4d36a25 PM |
254 | .flags = IORESOURCE_IRQ, |
255 | }, | |
256 | [2] = { | |
257 | /* Carry IRQ */ | |
29b53e37 | 258 | .start = evt2irq(0x7c0), |
b4d36a25 PM |
259 | .flags = IORESOURCE_IRQ, |
260 | }, | |
261 | [3] = { | |
262 | /* Alarm IRQ */ | |
29b53e37 | 263 | .start = evt2irq(0x780), |
b4d36a25 PM |
264 | .flags = IORESOURCE_IRQ, |
265 | }, | |
266 | }; | |
267 | ||
268 | static struct platform_device rtc_device = { | |
269 | .name = "sh-rtc", | |
270 | .id = -1, | |
271 | .num_resources = ARRAY_SIZE(rtc_resources), | |
272 | .resource = rtc_resources, | |
273 | }; | |
274 | ||
2c59b0b7 MD |
275 | static struct m66592_platdata usbf_platdata = { |
276 | .on_chip = 1, | |
277 | }; | |
278 | ||
262feaa0 YS |
279 | static struct resource usbf_resources[] = { |
280 | [0] = { | |
2c59b0b7 | 281 | .name = "USBF", |
a0d29798 MD |
282 | .start = 0x04480000, |
283 | .end = 0x044800FF, | |
262feaa0 YS |
284 | .flags = IORESOURCE_MEM, |
285 | }, | |
286 | [1] = { | |
29b53e37 PM |
287 | .start = evt2irq(0xa20), |
288 | .end = evt2irq(0xa20), | |
262feaa0 YS |
289 | .flags = IORESOURCE_IRQ, |
290 | }, | |
291 | }; | |
292 | ||
293 | static struct platform_device usbf_device = { | |
294 | .name = "m66592_udc", | |
af5be79a | 295 | .id = 0, /* "usbf0" clock */ |
262feaa0 YS |
296 | .dev = { |
297 | .dma_mask = NULL, | |
298 | .coherent_dma_mask = 0xffffffff, | |
2c59b0b7 | 299 | .platform_data = &usbf_platdata, |
262feaa0 YS |
300 | }, |
301 | .num_resources = ARRAY_SIZE(usbf_resources), | |
302 | .resource = usbf_resources, | |
303 | }; | |
304 | ||
ef1b2327 MD |
305 | static struct resource iic_resources[] = { |
306 | [0] = { | |
307 | .name = "IIC", | |
308 | .start = 0x04470000, | |
309 | .end = 0x04470017, | |
310 | .flags = IORESOURCE_MEM, | |
311 | }, | |
312 | [1] = { | |
29b53e37 PM |
313 | .start = evt2irq(0xe00), |
314 | .end = evt2irq(0xe60), | |
ef1b2327 MD |
315 | .flags = IORESOURCE_IRQ, |
316 | }, | |
317 | }; | |
318 | ||
319 | static struct platform_device iic_device = { | |
320 | .name = "i2c-sh_mobile", | |
a5616bd0 | 321 | .id = 0, /* "i2c0" clock */ |
ef1b2327 MD |
322 | .num_resources = ARRAY_SIZE(iic_resources), |
323 | .resource = iic_resources, | |
324 | }; | |
325 | ||
a55f6d25 MD |
326 | static struct uio_info vpu_platform_data = { |
327 | .name = "VPU4", | |
328 | .version = "0", | |
29b53e37 | 329 | .irq = evt2irq(0x980), |
a55f6d25 MD |
330 | }; |
331 | ||
332 | static struct resource vpu_resources[] = { | |
333 | [0] = { | |
334 | .name = "VPU", | |
335 | .start = 0xfe900000, | |
336 | .end = 0xfe9022eb, | |
337 | .flags = IORESOURCE_MEM, | |
338 | }, | |
1eca5c92 MD |
339 | [1] = { |
340 | /* place holder for contiguous memory */ | |
341 | }, | |
a55f6d25 MD |
342 | }; |
343 | ||
344 | static struct platform_device vpu_device = { | |
345 | .name = "uio_pdrv_genirq", | |
346 | .id = 0, | |
347 | .dev = { | |
348 | .platform_data = &vpu_platform_data, | |
349 | }, | |
350 | .resource = vpu_resources, | |
351 | .num_resources = ARRAY_SIZE(vpu_resources), | |
352 | }; | |
353 | ||
354 | static struct uio_info veu_platform_data = { | |
355 | .name = "VEU", | |
356 | .version = "0", | |
29b53e37 | 357 | .irq = evt2irq(0x8c0), |
a55f6d25 MD |
358 | }; |
359 | ||
360 | static struct resource veu_resources[] = { | |
361 | [0] = { | |
362 | .name = "VEU", | |
363 | .start = 0xfe920000, | |
364 | .end = 0xfe9200b7, | |
365 | .flags = IORESOURCE_MEM, | |
366 | }, | |
1eca5c92 MD |
367 | [1] = { |
368 | /* place holder for contiguous memory */ | |
369 | }, | |
a55f6d25 MD |
370 | }; |
371 | ||
372 | static struct platform_device veu_device = { | |
373 | .name = "uio_pdrv_genirq", | |
374 | .id = 1, | |
375 | .dev = { | |
376 | .platform_data = &veu_platform_data, | |
377 | }, | |
378 | .resource = veu_resources, | |
379 | .num_resources = ARRAY_SIZE(veu_resources), | |
380 | }; | |
381 | ||
7d91fcfc TH |
382 | static struct uio_info jpu_platform_data = { |
383 | .name = "JPU", | |
384 | .version = "0", | |
29b53e37 | 385 | .irq = evt2irq(0x560), |
7d91fcfc TH |
386 | }; |
387 | ||
388 | static struct resource jpu_resources[] = { | |
389 | [0] = { | |
390 | .name = "JPU", | |
391 | .start = 0xfea00000, | |
3442c0d6 | 392 | .end = 0xfea102d3, |
7d91fcfc TH |
393 | .flags = IORESOURCE_MEM, |
394 | }, | |
395 | [1] = { | |
396 | /* place holder for contiguous memory */ | |
397 | }, | |
398 | }; | |
399 | ||
400 | static struct platform_device jpu_device = { | |
401 | .name = "uio_pdrv_genirq", | |
402 | .id = 2, | |
403 | .dev = { | |
404 | .platform_data = &jpu_platform_data, | |
405 | }, | |
406 | .resource = jpu_resources, | |
407 | .num_resources = ARRAY_SIZE(jpu_resources), | |
408 | }; | |
409 | ||
46a12f74 | 410 | static struct sh_timer_config cmt_platform_data = { |
9b17e48c | 411 | .channels_mask = 0x20, |
424f59d0 MD |
412 | }; |
413 | ||
414 | static struct resource cmt_resources[] = { | |
9b17e48c LP |
415 | DEFINE_RES_MEM(0x044a0000, 0x70), |
416 | DEFINE_RES_IRQ(evt2irq(0xf00)), | |
424f59d0 MD |
417 | }; |
418 | ||
419 | static struct platform_device cmt_device = { | |
9b17e48c | 420 | .name = "sh-cmt-32", |
424f59d0 MD |
421 | .id = 0, |
422 | .dev = { | |
423 | .platform_data = &cmt_platform_data, | |
424 | }, | |
425 | .resource = cmt_resources, | |
426 | .num_resources = ARRAY_SIZE(cmt_resources), | |
427 | }; | |
428 | ||
46a12f74 | 429 | static struct sh_timer_config tmu0_platform_data = { |
1399c195 | 430 | .channels_mask = 7, |
d43a41bf MD |
431 | }; |
432 | ||
433 | static struct resource tmu0_resources[] = { | |
1399c195 LP |
434 | DEFINE_RES_MEM(0xffd80000, 0x2c), |
435 | DEFINE_RES_IRQ(evt2irq(0x400)), | |
436 | DEFINE_RES_IRQ(evt2irq(0x420)), | |
437 | DEFINE_RES_IRQ(evt2irq(0x440)), | |
d43a41bf MD |
438 | }; |
439 | ||
440 | static struct platform_device tmu0_device = { | |
1399c195 | 441 | .name = "sh-tmu", |
d43a41bf MD |
442 | .id = 0, |
443 | .dev = { | |
444 | .platform_data = &tmu0_platform_data, | |
445 | }, | |
446 | .resource = tmu0_resources, | |
447 | .num_resources = ARRAY_SIZE(tmu0_resources), | |
448 | }; | |
449 | ||
331af0c1 | 450 | static struct siu_platform siu_platform_data = { |
331af0c1 GL |
451 | .dma_slave_tx_a = SHDMA_SLAVE_SIUA_TX, |
452 | .dma_slave_rx_a = SHDMA_SLAVE_SIUA_RX, | |
453 | .dma_slave_tx_b = SHDMA_SLAVE_SIUB_TX, | |
454 | .dma_slave_rx_b = SHDMA_SLAVE_SIUB_RX, | |
8255fff4 NI |
455 | }; |
456 | ||
331af0c1 GL |
457 | static struct resource siu_resources[] = { |
458 | [0] = { | |
459 | .start = 0xa4540000, | |
460 | .end = 0xa454c10f, | |
461 | .flags = IORESOURCE_MEM, | |
462 | }, | |
463 | [1] = { | |
29b53e37 | 464 | .start = evt2irq(0xf80), |
331af0c1 GL |
465 | .flags = IORESOURCE_IRQ, |
466 | }, | |
467 | }; | |
468 | ||
469 | static struct platform_device siu_device = { | |
7d25d644 | 470 | .name = "siu-pcm-audio", |
8255fff4 | 471 | .id = -1, |
331af0c1 GL |
472 | .dev = { |
473 | .platform_data = &siu_platform_data, | |
474 | }, | |
475 | .resource = siu_resources, | |
476 | .num_resources = ARRAY_SIZE(siu_resources), | |
8255fff4 NI |
477 | }; |
478 | ||
41504c39 | 479 | static struct platform_device *sh7722_devices[] __initdata = { |
bcac24d0 MD |
480 | &scif0_device, |
481 | &scif1_device, | |
482 | &scif2_device, | |
424f59d0 | 483 | &cmt_device, |
d43a41bf | 484 | &tmu0_device, |
b4d36a25 | 485 | &rtc_device, |
262feaa0 | 486 | &usbf_device, |
ef1b2327 | 487 | &iic_device, |
a55f6d25 MD |
488 | &vpu_device, |
489 | &veu_device, | |
7d91fcfc | 490 | &jpu_device, |
331af0c1 | 491 | &siu_device, |
8255fff4 | 492 | &dma_device, |
41504c39 PM |
493 | }; |
494 | ||
495 | static int __init sh7722_devices_setup(void) | |
496 | { | |
1eca5c92 MD |
497 | platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20); |
498 | platform_resource_setup_memory(&veu_device, "veu", 2 << 20); | |
7d91fcfc | 499 | platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); |
6c7d826c | 500 | |
41504c39 PM |
501 | return platform_add_devices(sh7722_devices, |
502 | ARRAY_SIZE(sh7722_devices)); | |
503 | } | |
955c9863 | 504 | arch_initcall(sh7722_devices_setup); |
41504c39 | 505 | |
28fde686 | 506 | static struct platform_device *sh7722_early_devices[] __initdata = { |
bcac24d0 MD |
507 | &scif0_device, |
508 | &scif1_device, | |
509 | &scif2_device, | |
28fde686 | 510 | &cmt_device, |
d43a41bf | 511 | &tmu0_device, |
28fde686 MD |
512 | }; |
513 | ||
514 | void __init plat_early_device_setup(void) | |
515 | { | |
201e9109 | 516 | sh_early_platform_add_devices(sh7722_early_devices, |
28fde686 MD |
517 | ARRAY_SIZE(sh7722_early_devices)); |
518 | } | |
519 | ||
1b06428e MD |
520 | enum { |
521 | UNUSED=0, | |
8d9adaba | 522 | ENABLED, |
e9125ac0 | 523 | DISABLED, |
1b06428e MD |
524 | |
525 | /* interrupt sources */ | |
526 | IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, | |
527 | HUDI, | |
528 | SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI, | |
529 | RTC_ATI, RTC_PRI, RTC_CUI, | |
530 | DMAC0, DMAC1, DMAC2, DMAC3, | |
531 | VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU, | |
532 | VPU, TPU, | |
533 | USB_USBI0, USB_USBI1, | |
534 | DMAC4, DMAC5, DMAC_DADERR, | |
535 | KEYSC, | |
536 | SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO, | |
537 | FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, | |
538 | I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI, | |
1b06428e MD |
539 | CMT, TSIF, SIU, TWODG, |
540 | TMU0, TMU1, TMU2, | |
541 | IRDA, JPU, LCDC, | |
542 | ||
543 | /* interrupt groups */ | |
1b06428e | 544 | SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI, |
41504c39 PM |
545 | }; |
546 | ||
5c37e025 | 547 | static struct intc_vect vectors[] __initdata = { |
1b06428e MD |
548 | INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), |
549 | INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), | |
550 | INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), | |
551 | INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), | |
552 | INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720), | |
553 | INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760), | |
554 | INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0), | |
555 | INTC_VECT(RTC_CUI, 0x7c0), | |
556 | INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820), | |
557 | INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860), | |
558 | INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0), | |
559 | INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0), | |
560 | INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0), | |
561 | INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40), | |
562 | INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0), | |
563 | INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0), | |
564 | INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20), | |
565 | INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80), | |
566 | INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00), | |
567 | INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0), | |
568 | INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), | |
569 | INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20), | |
570 | INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60), | |
8d9adaba MD |
571 | INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0), |
572 | INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0), | |
1b06428e MD |
573 | INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), |
574 | INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0), | |
575 | INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), | |
576 | INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480), | |
577 | INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580), | |
41504c39 PM |
578 | }; |
579 | ||
5c37e025 | 580 | static struct intc_group groups[] __initdata = { |
1b06428e MD |
581 | INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI), |
582 | INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), | |
583 | INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3), | |
584 | INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU), | |
585 | INTC_GROUP(USB, USB_USBI0, USB_USBI1), | |
586 | INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR), | |
587 | INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI, | |
588 | FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), | |
589 | INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI), | |
1b06428e | 590 | }; |
68abdbbb | 591 | |
5c37e025 | 592 | static struct intc_mask_reg mask_registers[] __initdata = { |
1b06428e MD |
593 | { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ |
594 | { } }, | |
595 | { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ | |
596 | { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } }, | |
597 | { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ | |
598 | { 0, 0, 0, VPU, } }, | |
599 | { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ | |
600 | { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } }, | |
601 | { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ | |
602 | { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } }, | |
603 | { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ | |
604 | { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } }, | |
605 | { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ | |
606 | { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } }, | |
607 | { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ | |
608 | { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, | |
609 | FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, | |
610 | { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ | |
464495e5 | 611 | { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } }, |
1b06428e MD |
612 | { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ |
613 | { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } }, | |
614 | { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ | |
615 | { } }, | |
616 | { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ | |
617 | { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } }, | |
618 | { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ | |
619 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, | |
68abdbbb | 620 | }; |
41504c39 | 621 | |
5c37e025 | 622 | static struct intc_prio_reg prio_registers[] __initdata = { |
6ef5fb2c MD |
623 | { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } }, |
624 | { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } }, | |
625 | { 0xa4080008, 0, 16, 4, /* IPRC */ { } }, | |
626 | { 0xa408000c, 0, 16, 4, /* IPRD */ { } }, | |
627 | { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } }, | |
628 | { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } }, | |
629 | { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } }, | |
630 | { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } }, | |
631 | { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } }, | |
632 | { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } }, | |
633 | { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } }, | |
634 | { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } }, | |
635 | { 0xa4140010, 0, 32, 4, /* INTPRI00 */ | |
1b06428e MD |
636 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, |
637 | }; | |
638 | ||
5c37e025 | 639 | static struct intc_sense_reg sense_registers[] __initdata = { |
1b06428e MD |
640 | { 0xa414001c, 16, 2, /* ICR1 */ |
641 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, | |
642 | }; | |
643 | ||
6bdfb22a YS |
644 | static struct intc_mask_reg ack_registers[] __initdata = { |
645 | { 0xa4140024, 0, 8, /* INTREQ00 */ | |
646 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, | |
647 | }; | |
648 | ||
8d9adaba MD |
649 | static struct intc_desc intc_desc __initdata = { |
650 | .name = "sh7722", | |
651 | .force_enable = ENABLED, | |
e9125ac0 | 652 | .force_disable = DISABLED, |
8d9adaba MD |
653 | .hw = INTC_HW_DESC(vectors, groups, mask_registers, |
654 | prio_registers, sense_registers, ack_registers), | |
655 | }; | |
1b06428e | 656 | |
90015c89 | 657 | void __init plat_irq_setup(void) |
41504c39 | 658 | { |
1b06428e | 659 | register_intc_controller(&intc_desc); |
41504c39 | 660 | } |
520588f4 PM |
661 | |
662 | void __init plat_mem_setup(void) | |
663 | { | |
664 | /* Register the URAM space as Node 1 */ | |
665 | setup_bootmem_node(1, 0x055f0000, 0x05610000); | |
666 | } |