[linux-block.git] / arch / sh / kernel / cpu / sh4a / setup-sh7722.c

/*
 * SH7722 Setup
 *
 *  Copyright (C) 2006 - 2008  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/serial_sci.h>
#include <linux/mm.h>
#include <linux/uio_driver.h>
#include <linux/sh_cmt.h>
#include <asm/clock.h>
#include <asm/mmzone.h>

static struct resource rtc_resources[] = {
	[0] = {
		.start	= 0xa465fec0,
		.end	= 0xa465fec0 + 0x58 - 1,
		.flags	= IORESOURCE_IO,
	},
	[1] = {
		/* Period IRQ */
		.start	= 45,
		.flags	= IORESOURCE_IRQ,
	},
	[2] = {
		/* Carry IRQ */
		.start	= 46,
		.flags	= IORESOURCE_IRQ,
	},
	[3] = {
		/* Alarm IRQ */
		.start	= 44,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device rtc_device = {
	.name		= "sh-rtc",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(rtc_resources),
	.resource	= rtc_resources,
};

static struct resource usbf_resources[] = {
	[0] = {
		.name	= "m66592_udc",
		.start	= 0x04480000,
		.end	= 0x044800FF,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 65,
		.end	= 65,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device usbf_device = {
	.name		= "m66592_udc",
	.id             = 0, /* "usbf0" clock */
	.dev = {
		.dma_mask		= NULL,
		.coherent_dma_mask	= 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(usbf_resources),
	.resource	= usbf_resources,
};

static struct resource iic_resources[] = {
	[0] = {
		.name	= "IIC",
		.start  = 0x04470000,
		.end    = 0x04470017,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = 96,
		.end    = 99,
		.flags  = IORESOURCE_IRQ,
       },
};

static struct platform_device iic_device = {
	.name           = "i2c-sh_mobile",
	.id             = 0, /* "i2c0" clock */
	.num_resources  = ARRAY_SIZE(iic_resources),
	.resource       = iic_resources,
};

static struct uio_info vpu_platform_data = {
	.name = "VPU4",
	.version = "0",
	.irq = 60,
};

static struct resource vpu_resources[] = {
	[0] = {
		.name	= "VPU",
		.start	= 0xfe900000,
		.end	= 0xfe9022eb,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device vpu_device = {
	.name		= "uio_pdrv_genirq",
	.id		= 0,
	.dev = {
		.platform_data	= &vpu_platform_data,
	},
	.resource	= vpu_resources,
	.num_resources	= ARRAY_SIZE(vpu_resources),
};

static struct uio_info veu_platform_data = {
	.name = "VEU",
	.version = "0",
	.irq = 54,
};

static struct resource veu_resources[] = {
	[0] = {
		.name	= "VEU",
		.start	= 0xfe920000,
		.end	= 0xfe9200b7,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device veu_device = {
	.name		= "uio_pdrv_genirq",
	.id		= 1,
	.dev = {
		.platform_data	= &veu_platform_data,
	},
	.resource	= veu_resources,
	.num_resources	= ARRAY_SIZE(veu_resources),
};

static struct uio_info jpu_platform_data = {
	.name = "JPU",
	.version = "0",
	.irq = 27,
};

static struct resource jpu_resources[] = {
	[0] = {
		.name	= "JPU",
		.start	= 0xfea00000,
		.end	= 0xfea102d3,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device jpu_device = {
	.name		= "uio_pdrv_genirq",
	.id		= 2,
	.dev = {
		.platform_data	= &jpu_platform_data,
	},
	.resource	= jpu_resources,
	.num_resources	= ARRAY_SIZE(jpu_resources),
};

static struct sh_cmt_config cmt_platform_data = {
	.name = "CMT",
	.channel_offset = 0x60,
	.timer_bit = 5,
	.clk = "cmt0",
	.clockevent_rating = 125,
	.clocksource_rating = 200,
};

static struct resource cmt_resources[] = {
	[0] = {
		.name	= "CMT",
		.start	= 0x044a0060,
		.end	= 0x044a006b,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 104,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device cmt_device = {
	.name		= "sh_cmt",
	.id		= 0,
	.dev = {
		.platform_data	= &cmt_platform_data,
	},
	.resource	= cmt_resources,
	.num_resources	= ARRAY_SIZE(cmt_resources),
};

static struct plat_sci_port sci_platform_data[] = {
	{
		.mapbase	= 0xffe00000,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIF,
		.irqs		= { 80, 80, 80, 80 },
	},
	{
		.mapbase	= 0xffe10000,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIF,
		.irqs		= { 81, 81, 81, 81 },
	},
	{
		.mapbase	= 0xffe20000,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIF,
		.irqs		= { 82, 82, 82, 82 },
	},
	{
		.flags = 0,
	}
};

static struct platform_device sci_device = {
	.name		= "sh-sci",
	.id		= -1,
	.dev		= {
		.platform_data	= sci_platform_data,
	},
};

static struct platform_device *sh7722_devices[] __initdata = {
	&cmt_device,
	&rtc_device,
	&usbf_device,
	&iic_device,
	&sci_device,
	&vpu_device,
	&veu_device,
	&jpu_device,
};

static int __init sh7722_devices_setup(void)
{
	clk_always_enable("uram0"); /* URAM */
	clk_always_enable("xymem0"); /* XYMEM */
	clk_always_enable("rtc0"); /* RTC */
	clk_always_enable("veu0"); /* VEU */
	clk_always_enable("vpu0"); /* VPU */
	clk_always_enable("jpu0"); /* JPU */

	platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
	platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
	platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);

	return platform_add_devices(sh7722_devices,
				    ARRAY_SIZE(sh7722_devices));
}
__initcall(sh7722_devices_setup);

enum {
	UNUSED=0,

	/* interrupt sources */
	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	HUDI,
	SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
	RTC_ATI, RTC_PRI, RTC_CUI,
	DMAC0, DMAC1, DMAC2, DMAC3,
	VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
	VPU, TPU,
	USB_USBI0, USB_USBI1,
	DMAC4, DMAC5, DMAC_DADERR,
	KEYSC,
	SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
	FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
	I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
	SDHI0, SDHI1, SDHI2, SDHI3,
	CMT, TSIF, SIU, TWODG,
	TMU0, TMU1, TMU2,
	IRDA, JPU, LCDC,

	/* interrupt groups */
	SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
};

static struct intc_vect vectors[] __initdata = {
	INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
	INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
	INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
	INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
	INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
	INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
	INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
	INTC_VECT(RTC_CUI, 0x7c0),
	INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
	INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
	INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
	INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
	INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
	INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
	INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
	INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
	INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
	INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
	INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
	INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
	INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
	INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
	INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
	INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
	INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
	INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
	INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
	INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
	INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
};

static struct intc_group groups[] __initdata = {
	INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
	INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
	INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
	INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
	INTC_GROUP(USB, USB_USBI0, USB_USBI1),
	INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
	INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
		   FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
	INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
	INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
};

static struct intc_mask_reg mask_registers[] __initdata = {
	{ 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
	  { } },
	{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
	  { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
	{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
	  { 0, 0, 0, VPU, } },
	{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
	  { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
	{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
	  { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
	{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
	  { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
	{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
	  { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
	{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
	  { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
	    FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
	{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
	  { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, TWODG, SIU } },
	{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
	  { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
	{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
	  { } },
	{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
	  { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
	{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_prio_reg prio_registers[] __initdata = {
	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
	{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
	{ 0xa4080008, 0, 16, 4, /* IPRC */ { } },
	{ 0xa408000c, 0, 16, 4, /* IPRD */ { } },
	{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
	{ 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
	{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
	{ 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
	{ 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
	{ 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
	{ 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
	{ 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
	{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_sense_reg sense_registers[] __initdata = {
	{ 0xa414001c, 16, 2, /* ICR1 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_mask_reg ack_registers[] __initdata = {
	{ 0xa4140024, 0, 8, /* INTREQ00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static DECLARE_INTC_DESC_ACK(intc_desc, "sh7722", vectors, groups,
			     mask_registers, prio_registers, sense_registers,
			     ack_registers);

void __init plat_irq_setup(void)
{
	register_intc_controller(&intc_desc);
}

void __init plat_mem_setup(void)
{
	/* Register the URAM space as Node 1 */
	setup_bootmem_node(1, 0x055f0000, 0x05610000);
}
Commit	Line	Data
41504c39 PM	1	/*
	2	* SH7722 Setup
	3	*
b4d36a25	4	* Copyright (C) 2006 - 2008 Paul Mundt
41504c39 PM	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10	#include <linux/platform_device.h>
	11	#include <linux/init.h>
	12	#include <linux/serial.h>
96de1a8f	13	#include <linux/serial_sci.h>
520588f4	14	#include <linux/mm.h>
a55f6d25	15	#include <linux/uio_driver.h>
424f59d0	16	#include <linux/sh_cmt.h>
6c7d826c	17	#include <asm/clock.h>
5bbeafca	18	#include <asm/mmzone.h>
41504c39	19
b4d36a25 PM	20	static struct resource rtc_resources[] = {
	21	[0] = {
	22	.start = 0xa465fec0,
	23	.end = 0xa465fec0 + 0x58 - 1,
	24	.flags = IORESOURCE_IO,
	25	},
	26	[1] = {
	27	/* Period IRQ */
	28	.start = 45,
	29	.flags = IORESOURCE_IRQ,
	30	},
	31	[2] = {
	32	/* Carry IRQ */
	33	.start = 46,
	34	.flags = IORESOURCE_IRQ,
	35	},
	36	[3] = {
	37	/* Alarm IRQ */
	38	.start = 44,
	39	.flags = IORESOURCE_IRQ,
	40	},
	41	};
	42
	43	static struct platform_device rtc_device = {
	44	.name = "sh-rtc",
	45	.id = -1,
	46	.num_resources = ARRAY_SIZE(rtc_resources),
	47	.resource = rtc_resources,
	48	};
	49
262feaa0 YS	50	static struct resource usbf_resources[] = {
262feaa0 YS	51	[0] = {
526c1c23	52	.name = "m66592_udc",
a0d29798 MD	53	.start = 0x04480000,
a0d29798 MD	54	.end = 0x044800FF,
262feaa0 YS	55	.flags = IORESOURCE_MEM,
	56	},
	57	[1] = {
262feaa0 YS	58	.start = 65,
	59	.end = 65,
	60	.flags = IORESOURCE_IRQ,
	61	},
	62	};
	63
	64	static struct platform_device usbf_device = {
	65	.name = "m66592_udc",
af5be79a	66	.id = 0, /* "usbf0" clock */
262feaa0 YS	67	.dev = {
	68	.dma_mask = NULL,
	69	.coherent_dma_mask = 0xffffffff,
	70	},
	71	.num_resources = ARRAY_SIZE(usbf_resources),
	72	.resource = usbf_resources,
	73	};
	74
ef1b2327 MD	75	static struct resource iic_resources[] = {
	76	[0] = {
	77	.name = "IIC",
	78	.start = 0x04470000,
	79	.end = 0x04470017,
	80	.flags = IORESOURCE_MEM,
	81	},
	82	[1] = {
	83	.start = 96,
	84	.end = 99,
	85	.flags = IORESOURCE_IRQ,
	86	},
	87	};
	88
	89	static struct platform_device iic_device = {
	90	.name = "i2c-sh_mobile",
a5616bd0	91	.id = 0, /* "i2c0" clock */
ef1b2327 MD	92	.num_resources = ARRAY_SIZE(iic_resources),
	93	.resource = iic_resources,
	94	};
	95
a55f6d25 MD	96	static struct uio_info vpu_platform_data = {
	97	.name = "VPU4",
	98	.version = "0",
	99	.irq = 60,
	100	};
	101
	102	static struct resource vpu_resources[] = {
	103	[0] = {
	104	.name = "VPU",
	105	.start = 0xfe900000,
	106	.end = 0xfe9022eb,
	107	.flags = IORESOURCE_MEM,
	108	},
1eca5c92 MD	109	[1] = {
	110	/* place holder for contiguous memory */
	111	},
a55f6d25 MD	112	};
	113
	114	static struct platform_device vpu_device = {
	115	.name = "uio_pdrv_genirq",
	116	.id = 0,
	117	.dev = {
	118	.platform_data = &vpu_platform_data,
	119	},
	120	.resource = vpu_resources,
	121	.num_resources = ARRAY_SIZE(vpu_resources),
	122	};
	123
	124	static struct uio_info veu_platform_data = {
	125	.name = "VEU",
	126	.version = "0",
	127	.irq = 54,
	128	};
	129
	130	static struct resource veu_resources[] = {
	131	[0] = {
	132	.name = "VEU",
	133	.start = 0xfe920000,
	134	.end = 0xfe9200b7,
	135	.flags = IORESOURCE_MEM,
	136	},
1eca5c92 MD	137	[1] = {
	138	/* place holder for contiguous memory */
	139	},
a55f6d25 MD	140	};
	141
	142	static struct platform_device veu_device = {
	143	.name = "uio_pdrv_genirq",
	144	.id = 1,
	145	.dev = {
	146	.platform_data = &veu_platform_data,
	147	},
	148	.resource = veu_resources,
	149	.num_resources = ARRAY_SIZE(veu_resources),
	150	};
	151
7d91fcfc TH	152	static struct uio_info jpu_platform_data = {
	153	.name = "JPU",
	154	.version = "0",
	155	.irq = 27,
	156	};
	157
	158	static struct resource jpu_resources[] = {
	159	[0] = {
	160	.name = "JPU",
	161	.start = 0xfea00000,
3442c0d6	162	.end = 0xfea102d3,
7d91fcfc TH	163	.flags = IORESOURCE_MEM,
	164	},
	165	[1] = {
	166	/* place holder for contiguous memory */
	167	},
	168	};
	169
	170	static struct platform_device jpu_device = {
	171	.name = "uio_pdrv_genirq",
	172	.id = 2,
	173	.dev = {
	174	.platform_data = &jpu_platform_data,
	175	},
	176	.resource = jpu_resources,
	177	.num_resources = ARRAY_SIZE(jpu_resources),
	178	};
	179
424f59d0 MD	180	static struct sh_cmt_config cmt_platform_data = {
	181	.name = "CMT",
	182	.channel_offset = 0x60,
	183	.timer_bit = 5,
	184	.clk = "cmt0",
	185	.clockevent_rating = 125,
	186	.clocksource_rating = 200,
	187	};
	188
	189	static struct resource cmt_resources[] = {
	190	[0] = {
	191	.name = "CMT",
	192	.start = 0x044a0060,
	193	.end = 0x044a006b,
	194	.flags = IORESOURCE_MEM,
	195	},
	196	[1] = {
	197	.start = 104,
	198	.flags = IORESOURCE_IRQ,
	199	},
	200	};
	201
	202	static struct platform_device cmt_device = {
	203	.name = "sh_cmt",
	204	.id = 0,
	205	.dev = {
	206	.platform_data = &cmt_platform_data,
	207	},
	208	.resource = cmt_resources,
	209	.num_resources = ARRAY_SIZE(cmt_resources),
	210	};
	211
41504c39 PM	212	static struct plat_sci_port sci_platform_data[] = {
	213	{
	214	.mapbase = 0xffe00000,
	215	.flags = UPF_BOOT_AUTOCONF,
	216	.type = PORT_SCIF,
53aba19f MD	217	.irqs = { 80, 80, 80, 80 },
	218	},
	219	{
	220	.mapbase = 0xffe10000,
	221	.flags = UPF_BOOT_AUTOCONF,
	222	.type = PORT_SCIF,
	223	.irqs = { 81, 81, 81, 81 },
	224	},
	225	{
	226	.mapbase = 0xffe20000,
	227	.flags = UPF_BOOT_AUTOCONF,
	228	.type = PORT_SCIF,
	229	.irqs = { 82, 82, 82, 82 },
	230	},
	231	{
41504c39 PM	232	.flags = 0,
	233	}
	234	};
	235
	236	static struct platform_device sci_device = {
	237	.name = "sh-sci",
	238	.id = -1,
	239	.dev = {
	240	.platform_data = sci_platform_data,
	241	},
	242	};
	243
	244	static struct platform_device *sh7722_devices[] __initdata = {
424f59d0	245	&cmt_device,
b4d36a25	246	&rtc_device,
262feaa0	247	&usbf_device,
ef1b2327	248	&iic_device,
41504c39	249	&sci_device,
a55f6d25 MD	250	&vpu_device,
a55f6d25 MD	251	&veu_device,
7d91fcfc	252	&jpu_device,
41504c39 PM	253	};
	254
	255	static int __init sh7722_devices_setup(void)
	256	{
ef6aff68 MD	257	clk_always_enable("uram0"); /* URAM */
	258	clk_always_enable("xymem0"); /* XYMEM */
	259	clk_always_enable("rtc0"); /* RTC */
	260	clk_always_enable("veu0"); /* VEU */
	261	clk_always_enable("vpu0"); /* VPU */
7d91fcfc	262	clk_always_enable("jpu0"); /* JPU */
6c7d826c	263
1eca5c92 MD	264	platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
1eca5c92 MD	265	platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
7d91fcfc	266	platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
6c7d826c	267
41504c39 PM	268	return platform_add_devices(sh7722_devices,
	269	ARRAY_SIZE(sh7722_devices));
	270	}
	271	__initcall(sh7722_devices_setup);
	272
1b06428e MD	273	enum {
	274	UNUSED=0,
	275
	276	/* interrupt sources */
	277	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	278	HUDI,
	279	SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
	280	RTC_ATI, RTC_PRI, RTC_CUI,
	281	DMAC0, DMAC1, DMAC2, DMAC3,
	282	VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
	283	VPU, TPU,
	284	USB_USBI0, USB_USBI1,
	285	DMAC4, DMAC5, DMAC_DADERR,
	286	KEYSC,
	287	SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
	288	FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
	289	I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
	290	SDHI0, SDHI1, SDHI2, SDHI3,
	291	CMT, TSIF, SIU, TWODG,
	292	TMU0, TMU1, TMU2,
	293	IRDA, JPU, LCDC,
	294
	295	/* interrupt groups */
1b06428e	296	SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
41504c39 PM	297	};
41504c39 PM	298
5c37e025	299	static struct intc_vect vectors[] __initdata = {
1b06428e MD	300	INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
	301	INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
	302	INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
	303	INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
	304	INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
	305	INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
	306	INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
	307	INTC_VECT(RTC_CUI, 0x7c0),
	308	INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
	309	INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
	310	INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
	311	INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
	312	INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
	313	INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
	314	INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
	315	INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
	316	INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
	317	INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
	318	INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
	319	INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
	320	INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
	321	INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
	322	INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
	323	INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
	324	INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
	325	INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
	326	INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
	327	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
	328	INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
	329	INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
41504c39 PM	330	};
41504c39 PM	331
5c37e025	332	static struct intc_group groups[] __initdata = {
1b06428e MD	333	INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
	334	INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
	335	INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
	336	INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
	337	INTC_GROUP(USB, USB_USBI0, USB_USBI1),
	338	INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
	339	INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
	340	FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
	341	INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
	342	INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
	343	};
68abdbbb	344
5c37e025	345	static struct intc_mask_reg mask_registers[] __initdata = {
1b06428e MD	346	{ 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
	347	{ } },
	348	{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
	349	{ VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
	350	{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
	351	{ 0, 0, 0, VPU, } },
	352	{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
	353	{ SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
	354	{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
	355	{ 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
	356	{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
	357	{ KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
	358	{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
	359	{ 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
	360	{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
	361	{ I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
	362	FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
	363	{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
	364	{ SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, TWODG, SIU } },
	365	{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
	366	{ 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
	367	{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
	368	{ } },
	369	{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
	370	{ 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
	371	{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
	372	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
68abdbbb	373	};
41504c39	374
5c37e025	375	static struct intc_prio_reg prio_registers[] __initdata = {
6ef5fb2c MD	376	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
	377	{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
	378	{ 0xa4080008, 0, 16, 4, /* IPRC */ { } },
	379	{ 0xa408000c, 0, 16, 4, /* IPRD */ { } },
	380	{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
	381	{ 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
	382	{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
	383	{ 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
	384	{ 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
	385	{ 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
	386	{ 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
	387	{ 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
	388	{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
1b06428e MD	389	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	390	};
	391
5c37e025	392	static struct intc_sense_reg sense_registers[] __initdata = {
1b06428e MD	393	{ 0xa414001c, 16, 2, /* ICR1 */
	394	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	395	};
	396
6bdfb22a YS	397	static struct intc_mask_reg ack_registers[] __initdata = {
	398	{ 0xa4140024, 0, 8, /* INTREQ00 */
	399	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	400	};
	401
	402	static DECLARE_INTC_DESC_ACK(intc_desc, "sh7722", vectors, groups,
	403	mask_registers, prio_registers, sense_registers,
	404	ack_registers);
1b06428e	405
90015c89	406	void __init plat_irq_setup(void)
41504c39	407	{
1b06428e	408	register_intc_controller(&intc_desc);
41504c39	409	}
520588f4 PM	410
	411	void __init plat_mem_setup(void)
	412	{
	413	/* Register the URAM space as Node 1 */
	414	setup_bootmem_node(1, 0x055f0000, 0x05610000);
	415	}