[linux-2.6-block.git] / arch / sh / kernel / cpu / sh4a / setup-sh7343.c

/*
 * SH7343 Setup
 *
 *  Copyright (C) 2006  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/serial_sci.h>
#include <linux/uio_driver.h>
#include <linux/sh_timer.h>
#include <linux/sh_intc.h>
#include <asm/clock.h>

/* Serial */
static struct plat_sci_port scif0_platform_data = {
	.flags          = UPF_BOOT_AUTOCONF,
	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
	.type           = PORT_SCIF,
};

static struct resource scif0_resources[] = {
	DEFINE_RES_MEM(0xffe00000, 0x100),
	DEFINE_RES_IRQ(evt2irq(0xc00)),
};

static struct platform_device scif0_device = {
	.name		= "sh-sci",
	.id		= 0,
	.resource	= scif0_resources,
	.num_resources	= ARRAY_SIZE(scif0_resources),
	.dev		= {
		.platform_data	= &scif0_platform_data,
	},
};

static struct plat_sci_port scif1_platform_data = {
	.flags          = UPF_BOOT_AUTOCONF,
	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
	.type           = PORT_SCIF,
};

static struct resource scif1_resources[] = {
	DEFINE_RES_MEM(0xffe10000, 0x100),
	DEFINE_RES_IRQ(evt2irq(0xc20)),
};

static struct platform_device scif1_device = {
	.name		= "sh-sci",
	.id		= 1,
	.resource	= scif1_resources,
	.num_resources	= ARRAY_SIZE(scif1_resources),
	.dev		= {
		.platform_data	= &scif1_platform_data,
	},
};

static struct plat_sci_port scif2_platform_data = {
	.flags          = UPF_BOOT_AUTOCONF,
	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
	.type           = PORT_SCIF,
};

static struct resource scif2_resources[] = {
	DEFINE_RES_MEM(0xffe20000, 0x100),
	DEFINE_RES_IRQ(evt2irq(0xc40)),
};

static struct platform_device scif2_device = {
	.name		= "sh-sci",
	.id		= 2,
	.resource	= scif2_resources,
	.num_resources	= ARRAY_SIZE(scif2_resources),
	.dev		= {
		.platform_data	= &scif2_platform_data,
	},
};

static struct plat_sci_port scif3_platform_data = {
	.flags          = UPF_BOOT_AUTOCONF,
	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
	.type           = PORT_SCIF,
};

static struct resource scif3_resources[] = {
	DEFINE_RES_MEM(0xffe30000, 0x100),
	DEFINE_RES_IRQ(evt2irq(0xc60)),
};

static struct platform_device scif3_device = {
	.name		= "sh-sci",
	.id		= 3,
	.resource	= scif3_resources,
	.num_resources	= ARRAY_SIZE(scif3_resources),
	.dev		= {
		.platform_data	= &scif3_platform_data,
	},
};

static struct resource iic0_resources[] = {
	[0] = {
		.name	= "IIC0",
		.start  = 0x04470000,
		.end    = 0x04470017,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = evt2irq(0xe00),
		.end    = evt2irq(0xe60),
		.flags  = IORESOURCE_IRQ,
       },
};

static struct platform_device iic0_device = {
	.name           = "i2c-sh_mobile",
	.id             = 0, /* "i2c0" clock */
	.num_resources  = ARRAY_SIZE(iic0_resources),
	.resource       = iic0_resources,
};

static struct resource iic1_resources[] = {
	[0] = {
		.name	= "IIC1",
		.start  = 0x04750000,
		.end    = 0x04750017,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = evt2irq(0x780),
		.end    = evt2irq(0x7e0),
		.flags  = IORESOURCE_IRQ,
       },
};

static struct platform_device iic1_device = {
	.name           = "i2c-sh_mobile",
	.id             = 1, /* "i2c1" clock */
	.num_resources  = ARRAY_SIZE(iic1_resources),
	.resource       = iic1_resources,
};

static struct uio_info vpu_platform_data = {
	.name = "VPU4",
	.version = "0",
	.irq = evt2irq(0x980),
};

static struct resource vpu_resources[] = {
	[0] = {
		.name	= "VPU",
		.start	= 0xfe900000,
		.end	= 0xfe9022eb,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device vpu_device = {
	.name		= "uio_pdrv_genirq",
	.id		= 0,
	.dev = {
		.platform_data	= &vpu_platform_data,
	},
	.resource	= vpu_resources,
	.num_resources	= ARRAY_SIZE(vpu_resources),
};

static struct uio_info veu_platform_data = {
	.name = "VEU",
	.version = "0",
	.irq = evt2irq(0x8c0),
};

static struct resource veu_resources[] = {
	[0] = {
		.name	= "VEU",
		.start	= 0xfe920000,
		.end	= 0xfe9200b7,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device veu_device = {
	.name		= "uio_pdrv_genirq",
	.id		= 1,
	.dev = {
		.platform_data	= &veu_platform_data,
	},
	.resource	= veu_resources,
	.num_resources	= ARRAY_SIZE(veu_resources),
};

static struct uio_info jpu_platform_data = {
	.name = "JPU",
	.version = "0",
	.irq = evt2irq(0x560),
};

static struct resource jpu_resources[] = {
	[0] = {
		.name	= "JPU",
		.start	= 0xfea00000,
		.end	= 0xfea102d3,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device jpu_device = {
	.name		= "uio_pdrv_genirq",
	.id		= 2,
	.dev = {
		.platform_data	= &jpu_platform_data,
	},
	.resource	= jpu_resources,
	.num_resources	= ARRAY_SIZE(jpu_resources),
};

static struct sh_timer_config cmt_platform_data = {
	.channels_mask = 0x20,
};

static struct resource cmt_resources[] = {
	DEFINE_RES_MEM(0x044a0000, 0x70),
	DEFINE_RES_IRQ(evt2irq(0xf00)),
};

static struct platform_device cmt_device = {
	.name		= "sh-cmt-32",
	.id		= 0,
	.dev = {
		.platform_data	= &cmt_platform_data,
	},
	.resource	= cmt_resources,
	.num_resources	= ARRAY_SIZE(cmt_resources),
};

static struct sh_timer_config tmu0_platform_data = {
	.channel_offset = 0x04,
	.timer_bit = 0,
	.clockevent_rating = 200,
};

static struct resource tmu0_resources[] = {
	[0] = {
		.start	= 0xffd80008,
		.end	= 0xffd80013,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= evt2irq(0x400),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu0_device = {
	.name		= "sh_tmu",
	.id		= 0,
	.dev = {
		.platform_data	= &tmu0_platform_data,
	},
	.resource	= tmu0_resources,
	.num_resources	= ARRAY_SIZE(tmu0_resources),
};

static struct sh_timer_config tmu1_platform_data = {
	.channel_offset = 0x10,
	.timer_bit = 1,
	.clocksource_rating = 200,
};

static struct resource tmu1_resources[] = {
	[0] = {
		.start	= 0xffd80014,
		.end	= 0xffd8001f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= evt2irq(0x420),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu1_device = {
	.name		= "sh_tmu",
	.id		= 1,
	.dev = {
		.platform_data	= &tmu1_platform_data,
	},
	.resource	= tmu1_resources,
	.num_resources	= ARRAY_SIZE(tmu1_resources),
};

static struct sh_timer_config tmu2_platform_data = {
	.channel_offset = 0x1c,
	.timer_bit = 2,
};

static struct resource tmu2_resources[] = {
	[0] = {
		.start	= 0xffd80020,
		.end	= 0xffd8002b,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= evt2irq(0x440),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu2_device = {
	.name		= "sh_tmu",
	.id		= 2,
	.dev = {
		.platform_data	= &tmu2_platform_data,
	},
	.resource	= tmu2_resources,
	.num_resources	= ARRAY_SIZE(tmu2_resources),
};

static struct platform_device *sh7343_devices[] __initdata = {
	&scif0_device,
	&scif1_device,
	&scif2_device,
	&scif3_device,
	&cmt_device,
	&tmu0_device,
	&tmu1_device,
	&tmu2_device,
	&iic0_device,
	&iic1_device,
	&vpu_device,
	&veu_device,
	&jpu_device,
};

static int __init sh7343_devices_setup(void)
{
	platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
	platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
	platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);

	return platform_add_devices(sh7343_devices,
				    ARRAY_SIZE(sh7343_devices));
}
arch_initcall(sh7343_devices_setup);

static struct platform_device *sh7343_early_devices[] __initdata = {
	&scif0_device,
	&scif1_device,
	&scif2_device,
	&scif3_device,
	&cmt_device,
	&tmu0_device,
	&tmu1_device,
	&tmu2_device,
};

void __init plat_early_device_setup(void)
{
	early_platform_add_devices(sh7343_early_devices,
				   ARRAY_SIZE(sh7343_early_devices));
}

enum {
	UNUSED = 0,
	ENABLED,
	DISABLED,

	/* interrupt sources */
	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	DMAC0, DMAC1, DMAC2, DMAC3,
	VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
	MFI, VPU, TPU, Z3D4, USBI0, USBI1,
	MMC_ERR, MMC_TRAN, MMC_FSTAT, MMC_FRDY,
	DMAC4, DMAC5, DMAC_DADERR,
	KEYSC,
	SCIF, SCIF1, SCIF2, SCIF3,
	SIOF0, SIOF1, SIO,
	FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
	I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
	I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
	SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI,
	IRDA, SDHI, CMT, TSIF, SIU,
	TMU0, TMU1, TMU2,
	JPU, LCDC,

	/* interrupt groups */

	DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, USB,
};

static struct intc_vect vectors[] __initdata = {
	INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
	INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
	INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
	INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
	INTC_VECT(I2C1_ALI, 0x780), INTC_VECT(I2C1_TACKI, 0x7a0),
	INTC_VECT(I2C1_WAITI, 0x7c0), INTC_VECT(I2C1_DTEI, 0x7e0),
	INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
	INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
	INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
	INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
	INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980),
	INTC_VECT(TPU, 0x9a0), INTC_VECT(Z3D4, 0x9e0),
	INTC_VECT(USBI0, 0xa20), INTC_VECT(USBI1, 0xa40),
	INTC_VECT(MMC_ERR, 0xb00), INTC_VECT(MMC_TRAN, 0xb20),
	INTC_VECT(MMC_FSTAT, 0xb40), INTC_VECT(MMC_FRDY, 0xb60),
	INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
	INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
	INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIF1, 0xc20),
	INTC_VECT(SCIF2, 0xc40), INTC_VECT(SCIF3, 0xc60),
	INTC_VECT(SIOF0, 0xc80), INTC_VECT(SIOF1, 0xca0),
	INTC_VECT(SIO, 0xd00),
	INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
	INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
	INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20),
	INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60),
	INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
	INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
	INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
	INTC_VECT(SIU, 0xf80),
	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
	INTC_VECT(TMU2, 0x440),
	INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
};

static struct intc_group groups[] __initdata = {
	INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
	INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
	INTC_GROUP(MMC, MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR),
	INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
	INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
		   FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
	INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
	INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
	INTC_GROUP(SIM, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI),
	INTC_GROUP(USB, USBI0, USBI1),
};

static struct intc_mask_reg mask_registers[] __initdata = {
	{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
	  { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
	{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
	  { 0, 0, 0, VPU, 0, 0, 0, MFI } },
	{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
	  { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
	{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
	  { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
	{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
	  { KEYSC, DMAC_DADERR, DMAC5, DMAC4, SCIF3, SCIF2, SCIF1, SCIF } },
	{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
	  { 0, 0, 0, SIO, Z3D4, 0, SIOF1, SIOF0 } },
	{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
	  { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
	    FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
	{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
	  { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, 0, SIU } },
	{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
	  { 0, 0, 0, CMT, 0, USBI1, USBI0 } },
	{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
	  { MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR } },
	{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
	  { I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI, TPU, 0, 0, TSIF } },
	{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_prio_reg prio_registers[] __initdata = {
	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
	{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
	{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
	{ 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
	{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIF1, SCIF2, SCIF3 } },
	{ 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C0 } },
	{ 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, I2C1 } },
	{ 0xa4080024, 0, 16, 4, /* IPRJ */ { Z3D4, 0, SIU } },
	{ 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
	{ 0xa408002c, 0, 16, 4, /* IPRL */ { 0, 0, TPU } },
	{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_sense_reg sense_registers[] __initdata = {
	{ 0xa414001c, 16, 2, /* ICR1 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_mask_reg ack_registers[] __initdata = {
	{ 0xa4140024, 0, 8, /* INTREQ00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_desc intc_desc __initdata = {
	.name = "sh7343",
	.force_enable = ENABLED,
	.force_disable = DISABLED,
	.hw = INTC_HW_DESC(vectors, groups, mask_registers,
			   prio_registers, sense_registers, ack_registers),
};

void __init plat_irq_setup(void)
{
	register_intc_controller(&intc_desc);
}
Commit	Line	Data
e5723e0e PM	1	/*
	2	* SH7343 Setup
	3	*
	4	* Copyright (C) 2006 Paul Mundt
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10	#include <linux/platform_device.h>
	11	#include <linux/init.h>
	12	#include <linux/serial.h>
96de1a8f	13	#include <linux/serial_sci.h>
c901c96c	14	#include <linux/uio_driver.h>
46a12f74	15	#include <linux/sh_timer.h>
de410b53	16	#include <linux/sh_intc.h>
8fa509ab	17	#include <asm/clock.h>
e5723e0e	18
bcac24d0 MD	19	/* Serial */
bcac24d0 MD	20	static struct plat_sci_port scif0_platform_data = {
bcac24d0	21	.flags = UPF_BOOT_AUTOCONF,
f43dc23d	22	.scscr = SCSCR_RE \| SCSCR_TE \| SCSCR_CKE1,
bcac24d0	23	.type = PORT_SCIF,
d850acf9 LP	24	};
	25
	26	static struct resource scif0_resources[] = {
	27	DEFINE_RES_MEM(0xffe00000, 0x100),
	28	DEFINE_RES_IRQ(evt2irq(0xc00)),
bcac24d0 MD	29	};
	30
	31	static struct platform_device scif0_device = {
	32	.name = "sh-sci",
	33	.id = 0,
d850acf9 LP	34	.resource = scif0_resources,
d850acf9 LP	35	.num_resources = ARRAY_SIZE(scif0_resources),
bcac24d0 MD	36	.dev = {
	37	.platform_data = &scif0_platform_data,
	38	},
	39	};
	40
	41	static struct plat_sci_port scif1_platform_data = {
bcac24d0	42	.flags = UPF_BOOT_AUTOCONF,
f43dc23d	43	.scscr = SCSCR_RE \| SCSCR_TE \| SCSCR_CKE1,
bcac24d0	44	.type = PORT_SCIF,
d850acf9 LP	45	};
	46
	47	static struct resource scif1_resources[] = {
	48	DEFINE_RES_MEM(0xffe10000, 0x100),
	49	DEFINE_RES_IRQ(evt2irq(0xc20)),
bcac24d0 MD	50	};
	51
	52	static struct platform_device scif1_device = {
	53	.name = "sh-sci",
	54	.id = 1,
d850acf9 LP	55	.resource = scif1_resources,
d850acf9 LP	56	.num_resources = ARRAY_SIZE(scif1_resources),
bcac24d0 MD	57	.dev = {
	58	.platform_data = &scif1_platform_data,
	59	},
	60	};
	61
	62	static struct plat_sci_port scif2_platform_data = {
bcac24d0	63	.flags = UPF_BOOT_AUTOCONF,
f43dc23d	64	.scscr = SCSCR_RE \| SCSCR_TE \| SCSCR_CKE1,
bcac24d0	65	.type = PORT_SCIF,
d850acf9 LP	66	};
	67
	68	static struct resource scif2_resources[] = {
	69	DEFINE_RES_MEM(0xffe20000, 0x100),
	70	DEFINE_RES_IRQ(evt2irq(0xc40)),
bcac24d0 MD	71	};
	72
	73	static struct platform_device scif2_device = {
	74	.name = "sh-sci",
	75	.id = 2,
d850acf9 LP	76	.resource = scif2_resources,
d850acf9 LP	77	.num_resources = ARRAY_SIZE(scif2_resources),
bcac24d0 MD	78	.dev = {
	79	.platform_data = &scif2_platform_data,
	80	},
	81	};
	82
	83	static struct plat_sci_port scif3_platform_data = {
bcac24d0	84	.flags = UPF_BOOT_AUTOCONF,
f43dc23d	85	.scscr = SCSCR_RE \| SCSCR_TE \| SCSCR_CKE1,
bcac24d0	86	.type = PORT_SCIF,
d850acf9 LP	87	};
	88
	89	static struct resource scif3_resources[] = {
	90	DEFINE_RES_MEM(0xffe30000, 0x100),
	91	DEFINE_RES_IRQ(evt2irq(0xc60)),
bcac24d0 MD	92	};
	93
	94	static struct platform_device scif3_device = {
	95	.name = "sh-sci",
	96	.id = 3,
d850acf9 LP	97	.resource = scif3_resources,
d850acf9 LP	98	.num_resources = ARRAY_SIZE(scif3_resources),
bcac24d0 MD	99	.dev = {
	100	.platform_data = &scif3_platform_data,
	101	},
	102	};
	103
7549079d MD	104	static struct resource iic0_resources[] = {
	105	[0] = {
	106	.name = "IIC0",
	107	.start = 0x04470000,
	108	.end = 0x04470017,
	109	.flags = IORESOURCE_MEM,
	110	},
	111	[1] = {
de410b53 PM	112	.start = evt2irq(0xe00),
de410b53 PM	113	.end = evt2irq(0xe60),
7549079d MD	114	.flags = IORESOURCE_IRQ,
	115	},
	116	};
	117
	118	static struct platform_device iic0_device = {
	119	.name = "i2c-sh_mobile",
a5616bd0	120	.id = 0, /* "i2c0" clock */
7549079d MD	121	.num_resources = ARRAY_SIZE(iic0_resources),
	122	.resource = iic0_resources,
	123	};
	124
	125	static struct resource iic1_resources[] = {
	126	[0] = {
	127	.name = "IIC1",
	128	.start = 0x04750000,
	129	.end = 0x04750017,
	130	.flags = IORESOURCE_MEM,
	131	},
	132	[1] = {
de410b53 PM	133	.start = evt2irq(0x780),
de410b53 PM	134	.end = evt2irq(0x7e0),
7549079d MD	135	.flags = IORESOURCE_IRQ,
	136	},
	137	};
	138
	139	static struct platform_device iic1_device = {
	140	.name = "i2c-sh_mobile",
a5616bd0	141	.id = 1, /* "i2c1" clock */
7549079d MD	142	.num_resources = ARRAY_SIZE(iic1_resources),
	143	.resource = iic1_resources,
	144	};
	145
c901c96c MD	146	static struct uio_info vpu_platform_data = {
	147	.name = "VPU4",
	148	.version = "0",
de410b53	149	.irq = evt2irq(0x980),
c901c96c MD	150	};
	151
	152	static struct resource vpu_resources[] = {
	153	[0] = {
	154	.name = "VPU",
	155	.start = 0xfe900000,
	156	.end = 0xfe9022eb,
	157	.flags = IORESOURCE_MEM,
	158	},
1eca5c92 MD	159	[1] = {
	160	/* place holder for contiguous memory */
	161	},
c901c96c MD	162	};
	163
	164	static struct platform_device vpu_device = {
	165	.name = "uio_pdrv_genirq",
	166	.id = 0,
	167	.dev = {
	168	.platform_data = &vpu_platform_data,
	169	},
	170	.resource = vpu_resources,
	171	.num_resources = ARRAY_SIZE(vpu_resources),
	172	};
	173
	174	static struct uio_info veu_platform_data = {
	175	.name = "VEU",
	176	.version = "0",
de410b53	177	.irq = evt2irq(0x8c0),
c901c96c MD	178	};
	179
	180	static struct resource veu_resources[] = {
	181	[0] = {
	182	.name = "VEU",
	183	.start = 0xfe920000,
	184	.end = 0xfe9200b7,
	185	.flags = IORESOURCE_MEM,
	186	},
1eca5c92 MD	187	[1] = {
	188	/* place holder for contiguous memory */
	189	},
c901c96c MD	190	};
	191
	192	static struct platform_device veu_device = {
	193	.name = "uio_pdrv_genirq",
	194	.id = 1,
	195	.dev = {
	196	.platform_data = &veu_platform_data,
	197	},
	198	.resource = veu_resources,
	199	.num_resources = ARRAY_SIZE(veu_resources),
	200	};
	201
3442c0d6 MD	202	static struct uio_info jpu_platform_data = {
	203	.name = "JPU",
	204	.version = "0",
de410b53	205	.irq = evt2irq(0x560),
3442c0d6 MD	206	};
	207
	208	static struct resource jpu_resources[] = {
	209	[0] = {
	210	.name = "JPU",
	211	.start = 0xfea00000,
	212	.end = 0xfea102d3,
	213	.flags = IORESOURCE_MEM,
	214	},
	215	[1] = {
	216	/* place holder for contiguous memory */
	217	},
	218	};
	219
	220	static struct platform_device jpu_device = {
	221	.name = "uio_pdrv_genirq",
	222	.id = 2,
	223	.dev = {
	224	.platform_data = &jpu_platform_data,
	225	},
	226	.resource = jpu_resources,
	227	.num_resources = ARRAY_SIZE(jpu_resources),
	228	};
	229
46a12f74	230	static struct sh_timer_config cmt_platform_data = {
9b17e48c	231	.channels_mask = 0x20,
424f59d0 MD	232	};
	233
	234	static struct resource cmt_resources[] = {
9b17e48c LP	235	DEFINE_RES_MEM(0x044a0000, 0x70),
9b17e48c LP	236	DEFINE_RES_IRQ(evt2irq(0xf00)),
424f59d0 MD	237	};
	238
	239	static struct platform_device cmt_device = {
9b17e48c	240	.name = "sh-cmt-32",
424f59d0 MD	241	.id = 0,
	242	.dev = {
	243	.platform_data = &cmt_platform_data,
	244	},
	245	.resource = cmt_resources,
	246	.num_resources = ARRAY_SIZE(cmt_resources),
	247	};
	248
e37677a4	249	static struct sh_timer_config tmu0_platform_data = {
e37677a4 MD	250	.channel_offset = 0x04,
e37677a4 MD	251	.timer_bit = 0,
e37677a4 MD	252	.clockevent_rating = 200,
	253	};
	254
	255	static struct resource tmu0_resources[] = {
	256	[0] = {
e37677a4 MD	257	.start = 0xffd80008,
	258	.end = 0xffd80013,
	259	.flags = IORESOURCE_MEM,
	260	},
	261	[1] = {
de410b53	262	.start = evt2irq(0x400),
e37677a4 MD	263	.flags = IORESOURCE_IRQ,
	264	},
	265	};
	266
	267	static struct platform_device tmu0_device = {
	268	.name = "sh_tmu",
	269	.id = 0,
	270	.dev = {
	271	.platform_data = &tmu0_platform_data,
	272	},
	273	.resource = tmu0_resources,
	274	.num_resources = ARRAY_SIZE(tmu0_resources),
	275	};
	276
	277	static struct sh_timer_config tmu1_platform_data = {
e37677a4 MD	278	.channel_offset = 0x10,
e37677a4 MD	279	.timer_bit = 1,
e37677a4 MD	280	.clocksource_rating = 200,
	281	};
	282
	283	static struct resource tmu1_resources[] = {
	284	[0] = {
e37677a4 MD	285	.start = 0xffd80014,
	286	.end = 0xffd8001f,
	287	.flags = IORESOURCE_MEM,
	288	},
	289	[1] = {
de410b53	290	.start = evt2irq(0x420),
e37677a4 MD	291	.flags = IORESOURCE_IRQ,
	292	},
	293	};
	294
	295	static struct platform_device tmu1_device = {
	296	.name = "sh_tmu",
	297	.id = 1,
	298	.dev = {
	299	.platform_data = &tmu1_platform_data,
	300	},
	301	.resource = tmu1_resources,
	302	.num_resources = ARRAY_SIZE(tmu1_resources),
	303	};
	304
	305	static struct sh_timer_config tmu2_platform_data = {
e37677a4 MD	306	.channel_offset = 0x1c,
e37677a4 MD	307	.timer_bit = 2,
e37677a4 MD	308	};
	309
	310	static struct resource tmu2_resources[] = {
	311	[0] = {
e37677a4 MD	312	.start = 0xffd80020,
	313	.end = 0xffd8002b,
	314	.flags = IORESOURCE_MEM,
	315	},
	316	[1] = {
de410b53	317	.start = evt2irq(0x440),
e37677a4 MD	318	.flags = IORESOURCE_IRQ,
	319	},
	320	};
	321
	322	static struct platform_device tmu2_device = {
	323	.name = "sh_tmu",
	324	.id = 2,
	325	.dev = {
	326	.platform_data = &tmu2_platform_data,
	327	},
	328	.resource = tmu2_resources,
	329	.num_resources = ARRAY_SIZE(tmu2_resources),
	330	};
	331
e5723e0e	332	static struct platform_device *sh7343_devices[] __initdata = {
bcac24d0 MD	333	&scif0_device,
	334	&scif1_device,
	335	&scif2_device,
	336	&scif3_device,
424f59d0	337	&cmt_device,
e37677a4 MD	338	&tmu0_device,
	339	&tmu1_device,
	340	&tmu2_device,
7549079d MD	341	&iic0_device,
7549079d MD	342	&iic1_device,
c901c96c MD	343	&vpu_device,
c901c96c MD	344	&veu_device,
3442c0d6	345	&jpu_device,
e5723e0e PM	346	};
	347
	348	static int __init sh7343_devices_setup(void)
	349	{
1eca5c92 MD	350	platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
1eca5c92 MD	351	platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
3442c0d6	352	platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
8fa509ab	353
e5723e0e PM	354	return platform_add_devices(sh7343_devices,
	355	ARRAY_SIZE(sh7343_devices));
	356	}
ba9a6337	357	arch_initcall(sh7343_devices_setup);
35f3abe9	358
28fde686	359	static struct platform_device *sh7343_early_devices[] __initdata = {
bcac24d0 MD	360	&scif0_device,
	361	&scif1_device,
	362	&scif2_device,
	363	&scif3_device,
28fde686	364	&cmt_device,
e37677a4 MD	365	&tmu0_device,
	366	&tmu1_device,
	367	&tmu2_device,
28fde686 MD	368	};
	369
	370	void __init plat_early_device_setup(void)
	371	{
	372	early_platform_add_devices(sh7343_early_devices,
	373	ARRAY_SIZE(sh7343_early_devices));
	374	}
	375
a4e1d084 YS	376	enum {
a4e1d084 YS	377	UNUSED = 0,
3a0f4c78 MD	378	ENABLED,
3a0f4c78 MD	379	DISABLED,
a4e1d084 YS	380
	381	/* interrupt sources */
	382	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	383	DMAC0, DMAC1, DMAC2, DMAC3,
	384	VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
	385	MFI, VPU, TPU, Z3D4, USBI0, USBI1,
	386	MMC_ERR, MMC_TRAN, MMC_FSTAT, MMC_FRDY,
	387	DMAC4, DMAC5, DMAC_DADERR,
	388	KEYSC,
551ea2b4	389	SCIF, SCIF1, SCIF2, SCIF3,
a4e1d084 YS	390	SIOF0, SIOF1, SIO,
	391	FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
	392	I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
	393	I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
	394	SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI,
3a0f4c78	395	IRDA, SDHI, CMT, TSIF, SIU,
a4e1d084 YS	396	TMU0, TMU1, TMU2,
	397	JPU, LCDC,
	398
	399	/* interrupt groups */
	400
3a0f4c78	401	DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, USB,
a4e1d084 YS	402	};
	403
	404	static struct intc_vect vectors[] __initdata = {
	405	INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
	406	INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
	407	INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
	408	INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
	409	INTC_VECT(I2C1_ALI, 0x780), INTC_VECT(I2C1_TACKI, 0x7a0),
	410	INTC_VECT(I2C1_WAITI, 0x7c0), INTC_VECT(I2C1_DTEI, 0x7e0),
	411	INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
	412	INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
	413	INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
	414	INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
	415	INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980),
	416	INTC_VECT(TPU, 0x9a0), INTC_VECT(Z3D4, 0x9e0),
	417	INTC_VECT(USBI0, 0xa20), INTC_VECT(USBI1, 0xa40),
	418	INTC_VECT(MMC_ERR, 0xb00), INTC_VECT(MMC_TRAN, 0xb20),
	419	INTC_VECT(MMC_FSTAT, 0xb40), INTC_VECT(MMC_FRDY, 0xb60),
	420	INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
	421	INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
	422	INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIF1, 0xc20),
	423	INTC_VECT(SCIF2, 0xc40), INTC_VECT(SCIF3, 0xc60),
	424	INTC_VECT(SIOF0, 0xc80), INTC_VECT(SIOF1, 0xca0),
	425	INTC_VECT(SIO, 0xd00),
	426	INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
	427	INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
	428	INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20),
	429	INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60),
3a0f4c78 MD	430	INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
3a0f4c78 MD	431	INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
a4e1d084 YS	432	INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
	433	INTC_VECT(SIU, 0xf80),
	434	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
	435	INTC_VECT(TMU2, 0x440),
	436	INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
	437	};
	438
	439	static struct intc_group groups[] __initdata = {
	440	INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
	441	INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
	442	INTC_GROUP(MMC, MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR),
	443	INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
	444	INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
	445	FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
	446	INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
	447	INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
	448	INTC_GROUP(SIM, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI),
a4e1d084 YS	449	INTC_GROUP(USB, USBI0, USBI1),
	450	};
	451
	452	static struct intc_mask_reg mask_registers[] __initdata = {
	453	{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
	454	{ VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
	455	{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
	456	{ 0, 0, 0, VPU, 0, 0, 0, MFI } },
	457	{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
	458	{ SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
	459	{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
	460	{ 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
	461	{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
	462	{ KEYSC, DMAC_DADERR, DMAC5, DMAC4, SCIF3, SCIF2, SCIF1, SCIF } },
	463	{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
	464	{ 0, 0, 0, SIO, Z3D4, 0, SIOF1, SIOF0 } },
	465	{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
	466	{ I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
	467	FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
	468	{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
3a0f4c78	469	{ DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, 0, SIU } },
a4e1d084 YS	470	{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
	471	{ 0, 0, 0, CMT, 0, USBI1, USBI0 } },
	472	{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
	473	{ MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR } },
	474	{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
	475	{ I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI, TPU, 0, 0, TSIF } },
	476	{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
	477	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	478	};
	479
	480	static struct intc_prio_reg prio_registers[] __initdata = {
	481	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
	482	{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
	483	{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
	484	{ 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
	485	{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIF1, SCIF2, SCIF3 } },
	486	{ 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C0 } },
	487	{ 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, I2C1 } },
	488	{ 0xa4080024, 0, 16, 4, /* IPRJ */ { Z3D4, 0, SIU } },
	489	{ 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
	490	{ 0xa408002c, 0, 16, 4, /* IPRL */ { 0, 0, TPU } },
	491	{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
	492	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	493	};
	494
	495	static struct intc_sense_reg sense_registers[] __initdata = {
	496	{ 0xa414001c, 16, 2, /* ICR1 */
	497	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	498	};
	499
	500	static struct intc_mask_reg ack_registers[] __initdata = {
	501	{ 0xa4140024, 0, 8, /* INTREQ00 */
	502	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	503	};
	504
3a0f4c78 MD	505	static struct intc_desc intc_desc __initdata = {
	506	.name = "sh7343",
	507	.force_enable = ENABLED,
	508	.force_disable = DISABLED,
	509	.hw = INTC_HW_DESC(vectors, groups, mask_registers,
	510	prio_registers, sense_registers, ack_registers),
	511	};
a4e1d084	512
35f3abe9 PM	513	void __init plat_irq_setup(void)
35f3abe9 PM	514	{
a4e1d084	515	register_intc_controller(&intc_desc);
35f3abe9	516	}