[linux-block.git] / arch / sh / kernel / cpu / sh4a / setup-sh7343.c

/*
 * SH7343 Setup
 *
 *  Copyright (C) 2006  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/serial_sci.h>
#include <linux/uio_driver.h>
#include <linux/sh_timer.h>
#include <asm/clock.h>

static struct resource iic0_resources[] = {
	[0] = {
		.name	= "IIC0",
		.start  = 0x04470000,
		.end    = 0x04470017,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = 96,
		.end    = 99,
		.flags  = IORESOURCE_IRQ,
       },
};

static struct platform_device iic0_device = {
	.name           = "i2c-sh_mobile",
	.id             = 0, /* "i2c0" clock */
	.num_resources  = ARRAY_SIZE(iic0_resources),
	.resource       = iic0_resources,
};

static struct resource iic1_resources[] = {
	[0] = {
		.name	= "IIC1",
		.start  = 0x04750000,
		.end    = 0x04750017,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = 44,
		.end    = 47,
		.flags  = IORESOURCE_IRQ,
       },
};

static struct platform_device iic1_device = {
	.name           = "i2c-sh_mobile",
	.id             = 1, /* "i2c1" clock */
	.num_resources  = ARRAY_SIZE(iic1_resources),
	.resource       = iic1_resources,
};

static struct uio_info vpu_platform_data = {
	.name = "VPU4",
	.version = "0",
	.irq = 60,
};

static struct resource vpu_resources[] = {
	[0] = {
		.name	= "VPU",
		.start	= 0xfe900000,
		.end	= 0xfe9022eb,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device vpu_device = {
	.name		= "uio_pdrv_genirq",
	.id		= 0,
	.dev = {
		.platform_data	= &vpu_platform_data,
	},
	.resource	= vpu_resources,
	.num_resources	= ARRAY_SIZE(vpu_resources),
};

static struct uio_info veu_platform_data = {
	.name = "VEU",
	.version = "0",
	.irq = 54,
};

static struct resource veu_resources[] = {
	[0] = {
		.name	= "VEU",
		.start	= 0xfe920000,
		.end	= 0xfe9200b7,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device veu_device = {
	.name		= "uio_pdrv_genirq",
	.id		= 1,
	.dev = {
		.platform_data	= &veu_platform_data,
	},
	.resource	= veu_resources,
	.num_resources	= ARRAY_SIZE(veu_resources),
};

static struct uio_info jpu_platform_data = {
	.name = "JPU",
	.version = "0",
	.irq = 27,
};

static struct resource jpu_resources[] = {
	[0] = {
		.name	= "JPU",
		.start	= 0xfea00000,
		.end	= 0xfea102d3,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device jpu_device = {
	.name		= "uio_pdrv_genirq",
	.id		= 2,
	.dev = {
		.platform_data	= &jpu_platform_data,
	},
	.resource	= jpu_resources,
	.num_resources	= ARRAY_SIZE(jpu_resources),
};

static struct sh_timer_config cmt_platform_data = {
	.name = "CMT",
	.channel_offset = 0x60,
	.timer_bit = 5,
	.clk = "cmt0",
	.clockevent_rating = 125,
	.clocksource_rating = 200,
};

static struct resource cmt_resources[] = {
	[0] = {
		.name	= "CMT",
		.start	= 0x044a0060,
		.end	= 0x044a006b,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 104,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device cmt_device = {
	.name		= "sh_cmt",
	.id		= 0,
	.dev = {
		.platform_data	= &cmt_platform_data,
	},
	.resource	= cmt_resources,
	.num_resources	= ARRAY_SIZE(cmt_resources),
};

static struct plat_sci_port sci_platform_data[] = {
	{
		.mapbase	= 0xffe00000,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIF,
		.irqs		= { 80, 80, 80, 80 },
	}, {
		.mapbase	= 0xffe10000,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIF,
		.irqs		= { 81, 81, 81, 81 },
	}, {
		.mapbase	= 0xffe20000,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIF,
		.irqs		= { 82, 82, 82, 82 },
	}, {
		.mapbase	= 0xffe30000,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIF,
		.irqs		= { 83, 83, 83, 83 },
	}, {
		.flags = 0,
	}
};

static struct platform_device sci_device = {
	.name		= "sh-sci",
	.id		= -1,
	.dev		= {
		.platform_data	= sci_platform_data,
	},
};

static struct platform_device *sh7343_devices[] __initdata = {
	&cmt_device,
	&iic0_device,
	&iic1_device,
	&sci_device,
	&vpu_device,
	&veu_device,
	&jpu_device,
};

static int __init sh7343_devices_setup(void)
{
	clk_always_enable("uram0"); /* URAM */
	clk_always_enable("xymem0"); /* XYMEM */
	clk_always_enable("veu0"); /* VEU */
	clk_always_enable("vpu0"); /* VPU */
	clk_always_enable("jpu0"); /* JPU */

	platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
	platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
	platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);

	return platform_add_devices(sh7343_devices,
				    ARRAY_SIZE(sh7343_devices));
}
__initcall(sh7343_devices_setup);

static struct platform_device *sh7343_early_devices[] __initdata = {
	&cmt_device,
};

void __init plat_early_device_setup(void)
{
	early_platform_add_devices(sh7343_early_devices,
				   ARRAY_SIZE(sh7343_early_devices));
}

enum {
	UNUSED = 0,

	/* interrupt sources */
	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	DMAC0, DMAC1, DMAC2, DMAC3,
	VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
	MFI, VPU, TPU, Z3D4, USBI0, USBI1,
	MMC_ERR, MMC_TRAN, MMC_FSTAT, MMC_FRDY,
	DMAC4, DMAC5, DMAC_DADERR,
	KEYSC,
	SCIF, SCIF1, SCIF2, SCIF3,
	SIOF0, SIOF1, SIO,
	FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
	I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
	I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
	SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI,
	IRDA,
	SDHI0, SDHI1, SDHI2, SDHI3,
	CMT, TSIF, SIU,
	TMU0, TMU1, TMU2,
	JPU, LCDC,

	/* interrupt groups */

	DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, SDHI, USB,
};

static struct intc_vect vectors[] __initdata = {
	INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
	INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
	INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
	INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
	INTC_VECT(I2C1_ALI, 0x780), INTC_VECT(I2C1_TACKI, 0x7a0),
	INTC_VECT(I2C1_WAITI, 0x7c0), INTC_VECT(I2C1_DTEI, 0x7e0),
	INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
	INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
	INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
	INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
	INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980),
	INTC_VECT(TPU, 0x9a0), INTC_VECT(Z3D4, 0x9e0),
	INTC_VECT(USBI0, 0xa20), INTC_VECT(USBI1, 0xa40),
	INTC_VECT(MMC_ERR, 0xb00), INTC_VECT(MMC_TRAN, 0xb20),
	INTC_VECT(MMC_FSTAT, 0xb40), INTC_VECT(MMC_FRDY, 0xb60),
	INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
	INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
	INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIF1, 0xc20),
	INTC_VECT(SCIF2, 0xc40), INTC_VECT(SCIF3, 0xc60),
	INTC_VECT(SIOF0, 0xc80), INTC_VECT(SIOF1, 0xca0),
	INTC_VECT(SIO, 0xd00),
	INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
	INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
	INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20),
	INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60),
	INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
	INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
	INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
	INTC_VECT(SIU, 0xf80),
	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
	INTC_VECT(TMU2, 0x440),
	INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
};

static struct intc_group groups[] __initdata = {
	INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
	INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
	INTC_GROUP(MMC, MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR),
	INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
	INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
		   FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
	INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
	INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
	INTC_GROUP(SIM, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI),
	INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
	INTC_GROUP(USB, USBI0, USBI1),
};

static struct intc_mask_reg mask_registers[] __initdata = {
	{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
	  { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
	{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
	  { 0, 0, 0, VPU, 0, 0, 0, MFI } },
	{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
	  { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
	{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
	  { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
	{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
	  { KEYSC, DMAC_DADERR, DMAC5, DMAC4, SCIF3, SCIF2, SCIF1, SCIF } },
	{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
	  { 0, 0, 0, SIO, Z3D4, 0, SIOF1, SIOF0 } },
	{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
	  { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
	    FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
	{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
	  { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } },
	{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
	  { 0, 0, 0, CMT, 0, USBI1, USBI0 } },
	{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
	  { MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR } },
	{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
	  { I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI, TPU, 0, 0, TSIF } },
	{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_prio_reg prio_registers[] __initdata = {
	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
	{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
	{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
	{ 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
	{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIF1, SCIF2, SCIF3 } },
	{ 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C0 } },
	{ 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, I2C1 } },
	{ 0xa4080024, 0, 16, 4, /* IPRJ */ { Z3D4, 0, SIU } },
	{ 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
	{ 0xa408002c, 0, 16, 4, /* IPRL */ { 0, 0, TPU } },
	{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_sense_reg sense_registers[] __initdata = {
	{ 0xa414001c, 16, 2, /* ICR1 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_mask_reg ack_registers[] __initdata = {
	{ 0xa4140024, 0, 8, /* INTREQ00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static DECLARE_INTC_DESC_ACK(intc_desc, "sh7343", vectors, groups,
			     mask_registers, prio_registers, sense_registers,
			     ack_registers);

void __init plat_irq_setup(void)
{
	register_intc_controller(&intc_desc);
}
Commit	Line	Data
e5723e0e PM	1	/*
	2	* SH7343 Setup
	3	*
	4	* Copyright (C) 2006 Paul Mundt
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10	#include <linux/platform_device.h>
	11	#include <linux/init.h>
	12	#include <linux/serial.h>
96de1a8f	13	#include <linux/serial_sci.h>
c901c96c	14	#include <linux/uio_driver.h>
46a12f74	15	#include <linux/sh_timer.h>
8fa509ab	16	#include <asm/clock.h>
e5723e0e	17
7549079d MD	18	static struct resource iic0_resources[] = {
	19	[0] = {
	20	.name = "IIC0",
	21	.start = 0x04470000,
	22	.end = 0x04470017,
	23	.flags = IORESOURCE_MEM,
	24	},
	25	[1] = {
	26	.start = 96,
	27	.end = 99,
	28	.flags = IORESOURCE_IRQ,
	29	},
	30	};
	31
	32	static struct platform_device iic0_device = {
	33	.name = "i2c-sh_mobile",
a5616bd0	34	.id = 0, /* "i2c0" clock */
7549079d MD	35	.num_resources = ARRAY_SIZE(iic0_resources),
	36	.resource = iic0_resources,
	37	};
	38
	39	static struct resource iic1_resources[] = {
	40	[0] = {
	41	.name = "IIC1",
	42	.start = 0x04750000,
	43	.end = 0x04750017,
	44	.flags = IORESOURCE_MEM,
	45	},
	46	[1] = {
	47	.start = 44,
	48	.end = 47,
	49	.flags = IORESOURCE_IRQ,
	50	},
	51	};
	52
	53	static struct platform_device iic1_device = {
	54	.name = "i2c-sh_mobile",
a5616bd0	55	.id = 1, /* "i2c1" clock */
7549079d MD	56	.num_resources = ARRAY_SIZE(iic1_resources),
	57	.resource = iic1_resources,
	58	};
	59
c901c96c MD	60	static struct uio_info vpu_platform_data = {
	61	.name = "VPU4",
	62	.version = "0",
	63	.irq = 60,
	64	};
	65
	66	static struct resource vpu_resources[] = {
	67	[0] = {
	68	.name = "VPU",
	69	.start = 0xfe900000,
	70	.end = 0xfe9022eb,
	71	.flags = IORESOURCE_MEM,
	72	},
1eca5c92 MD	73	[1] = {
	74	/* place holder for contiguous memory */
	75	},
c901c96c MD	76	};
	77
	78	static struct platform_device vpu_device = {
	79	.name = "uio_pdrv_genirq",
	80	.id = 0,
	81	.dev = {
	82	.platform_data = &vpu_platform_data,
	83	},
	84	.resource = vpu_resources,
	85	.num_resources = ARRAY_SIZE(vpu_resources),
	86	};
	87
	88	static struct uio_info veu_platform_data = {
	89	.name = "VEU",
	90	.version = "0",
	91	.irq = 54,
	92	};
	93
	94	static struct resource veu_resources[] = {
	95	[0] = {
	96	.name = "VEU",
	97	.start = 0xfe920000,
	98	.end = 0xfe9200b7,
	99	.flags = IORESOURCE_MEM,
	100	},
1eca5c92 MD	101	[1] = {
	102	/* place holder for contiguous memory */
	103	},
c901c96c MD	104	};
	105
	106	static struct platform_device veu_device = {
	107	.name = "uio_pdrv_genirq",
	108	.id = 1,
	109	.dev = {
	110	.platform_data = &veu_platform_data,
	111	},
	112	.resource = veu_resources,
	113	.num_resources = ARRAY_SIZE(veu_resources),
	114	};
	115
3442c0d6 MD	116	static struct uio_info jpu_platform_data = {
	117	.name = "JPU",
	118	.version = "0",
	119	.irq = 27,
	120	};
	121
	122	static struct resource jpu_resources[] = {
	123	[0] = {
	124	.name = "JPU",
	125	.start = 0xfea00000,
	126	.end = 0xfea102d3,
	127	.flags = IORESOURCE_MEM,
	128	},
	129	[1] = {
	130	/* place holder for contiguous memory */
	131	},
	132	};
	133
	134	static struct platform_device jpu_device = {
	135	.name = "uio_pdrv_genirq",
	136	.id = 2,
	137	.dev = {
	138	.platform_data = &jpu_platform_data,
	139	},
	140	.resource = jpu_resources,
	141	.num_resources = ARRAY_SIZE(jpu_resources),
	142	};
	143
46a12f74	144	static struct sh_timer_config cmt_platform_data = {
424f59d0 MD	145	.name = "CMT",
	146	.channel_offset = 0x60,
	147	.timer_bit = 5,
	148	.clk = "cmt0",
	149	.clockevent_rating = 125,
	150	.clocksource_rating = 200,
	151	};
	152
	153	static struct resource cmt_resources[] = {
	154	[0] = {
	155	.name = "CMT",
	156	.start = 0x044a0060,
	157	.end = 0x044a006b,
	158	.flags = IORESOURCE_MEM,
	159	},
	160	[1] = {
	161	.start = 104,
	162	.flags = IORESOURCE_IRQ,
	163	},
	164	};
	165
	166	static struct platform_device cmt_device = {
	167	.name = "sh_cmt",
	168	.id = 0,
	169	.dev = {
	170	.platform_data = &cmt_platform_data,
	171	},
	172	.resource = cmt_resources,
	173	.num_resources = ARRAY_SIZE(cmt_resources),
	174	};
	175
e5723e0e PM	176	static struct plat_sci_port sci_platform_data[] = {
	177	{
	178	.mapbase = 0xffe00000,
	179	.flags = UPF_BOOT_AUTOCONF,
	180	.type = PORT_SCIF,
551ea2b4 MD	181	.irqs = { 80, 80, 80, 80 },
	182	}, {
	183	.mapbase = 0xffe10000,
	184	.flags = UPF_BOOT_AUTOCONF,
	185	.type = PORT_SCIF,
	186	.irqs = { 81, 81, 81, 81 },
	187	}, {
	188	.mapbase = 0xffe20000,
	189	.flags = UPF_BOOT_AUTOCONF,
	190	.type = PORT_SCIF,
	191	.irqs = { 82, 82, 82, 82 },
	192	}, {
	193	.mapbase = 0xffe30000,
	194	.flags = UPF_BOOT_AUTOCONF,
	195	.type = PORT_SCIF,
	196	.irqs = { 83, 83, 83, 83 },
e5723e0e PM	197	}, {
	198	.flags = 0,
	199	}
	200	};
	201
	202	static struct platform_device sci_device = {
	203	.name = "sh-sci",
	204	.id = -1,
	205	.dev = {
	206	.platform_data = sci_platform_data,
	207	},
	208	};
	209
	210	static struct platform_device *sh7343_devices[] __initdata = {
424f59d0	211	&cmt_device,
7549079d MD	212	&iic0_device,
7549079d MD	213	&iic1_device,
e5723e0e	214	&sci_device,
c901c96c MD	215	&vpu_device,
c901c96c MD	216	&veu_device,
3442c0d6	217	&jpu_device,
e5723e0e PM	218	};
	219
	220	static int __init sh7343_devices_setup(void)
	221	{
ef6aff68 MD	222	clk_always_enable("uram0"); /* URAM */
	223	clk_always_enable("xymem0"); /* XYMEM */
	224	clk_always_enable("veu0"); /* VEU */
	225	clk_always_enable("vpu0"); /* VPU */
3442c0d6	226	clk_always_enable("jpu0"); /* JPU */
8fa509ab	227
1eca5c92 MD	228	platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
1eca5c92 MD	229	platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
3442c0d6	230	platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
8fa509ab	231
e5723e0e PM	232	return platform_add_devices(sh7343_devices,
	233	ARRAY_SIZE(sh7343_devices));
	234	}
	235	__initcall(sh7343_devices_setup);
35f3abe9	236
28fde686 MD	237	static struct platform_device *sh7343_early_devices[] __initdata = {
	238	&cmt_device,
	239	};
	240
	241	void __init plat_early_device_setup(void)
	242	{
	243	early_platform_add_devices(sh7343_early_devices,
	244	ARRAY_SIZE(sh7343_early_devices));
	245	}
	246
a4e1d084 YS	247	enum {
	248	UNUSED = 0,
	249
	250	/* interrupt sources */
	251	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	252	DMAC0, DMAC1, DMAC2, DMAC3,
	253	VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
	254	MFI, VPU, TPU, Z3D4, USBI0, USBI1,
	255	MMC_ERR, MMC_TRAN, MMC_FSTAT, MMC_FRDY,
	256	DMAC4, DMAC5, DMAC_DADERR,
	257	KEYSC,
551ea2b4	258	SCIF, SCIF1, SCIF2, SCIF3,
a4e1d084 YS	259	SIOF0, SIOF1, SIO,
	260	FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
	261	I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
	262	I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
	263	SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI,
	264	IRDA,
	265	SDHI0, SDHI1, SDHI2, SDHI3,
	266	CMT, TSIF, SIU,
	267	TMU0, TMU1, TMU2,
	268	JPU, LCDC,
	269
	270	/* interrupt groups */
	271
	272	DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, SDHI, USB,
	273	};
	274
	275	static struct intc_vect vectors[] __initdata = {
	276	INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
	277	INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
	278	INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
	279	INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
	280	INTC_VECT(I2C1_ALI, 0x780), INTC_VECT(I2C1_TACKI, 0x7a0),
	281	INTC_VECT(I2C1_WAITI, 0x7c0), INTC_VECT(I2C1_DTEI, 0x7e0),
	282	INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
	283	INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
	284	INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
	285	INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
	286	INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980),
	287	INTC_VECT(TPU, 0x9a0), INTC_VECT(Z3D4, 0x9e0),
	288	INTC_VECT(USBI0, 0xa20), INTC_VECT(USBI1, 0xa40),
	289	INTC_VECT(MMC_ERR, 0xb00), INTC_VECT(MMC_TRAN, 0xb20),
	290	INTC_VECT(MMC_FSTAT, 0xb40), INTC_VECT(MMC_FRDY, 0xb60),
	291	INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
	292	INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
	293	INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIF1, 0xc20),
	294	INTC_VECT(SCIF2, 0xc40), INTC_VECT(SCIF3, 0xc60),
	295	INTC_VECT(SIOF0, 0xc80), INTC_VECT(SIOF1, 0xca0),
	296	INTC_VECT(SIO, 0xd00),
	297	INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
	298	INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
	299	INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20),
	300	INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60),
	301	INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
	302	INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
	303	INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
	304	INTC_VECT(SIU, 0xf80),
	305	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
	306	INTC_VECT(TMU2, 0x440),
	307	INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
	308	};
	309
	310	static struct intc_group groups[] __initdata = {
	311	INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
	312	INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
	313	INTC_GROUP(MMC, MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR),
	314	INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
	315	INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
	316	FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
	317	INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
	318	INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
	319	INTC_GROUP(SIM, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI),
	320	INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
	321	INTC_GROUP(USB, USBI0, USBI1),
	322	};
323
324	static struct intc_mask_reg mask_registers[] __initdata = {
325	{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
326	{ VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
327	{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
328	{ 0, 0, 0, VPU, 0, 0, 0, MFI } },
329	{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
330	{ SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
331	{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
332	{ 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
333	{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
334	{ KEYSC, DMAC_DADERR, DMAC5, DMAC4, SCIF3, SCIF2, SCIF1, SCIF } },
335	{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
336	{ 0, 0, 0, SIO, Z3D4, 0, SIOF1, SIOF0 } },
337	{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
338	{ I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
339	FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
340	{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
341	{ SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } },
342	{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
343	{ 0, 0, 0, CMT, 0, USBI1, USBI0 } },
344	{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
345	{ MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR } },
346	{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
347	{ I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI, TPU, 0, 0, TSIF } },
348	{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
349	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
350	};
351
352	static struct intc_prio_reg prio_registers[] __initdata = {
353	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
354	{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
355	{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
356	{ 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
357	{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIF1, SCIF2, SCIF3 } },
358	{ 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C0 } },
359	{ 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, I2C1 } },
360	{ 0xa4080024, 0, 16, 4, /* IPRJ */ { Z3D4, 0, SIU } },
361	{ 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
362	{ 0xa408002c, 0, 16, 4, /* IPRL */ { 0, 0, TPU } },
363	{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
364	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
365	};
366
367	static struct intc_sense_reg sense_registers[] __initdata = {
368	{ 0xa414001c, 16, 2, /* ICR1 */
369	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
370	};
371
372	static struct intc_mask_reg ack_registers[] __initdata = {
373	{ 0xa4140024, 0, 8, /* INTREQ00 */
374	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
375	};
376
377	static DECLARE_INTC_DESC_ACK(intc_desc, "sh7343", vectors, groups,
378	mask_registers, prio_registers, sense_registers,
379	ack_registers);
380
35f3abe9 PM	381	void __init plat_irq_setup(void)
35f3abe9 PM	382	{
a4e1d084	383	register_intc_controller(&intc_desc);
35f3abe9	384	}