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32351a28 PM |
1 | /* |
2 | * arch/sh/kernel/cpu/sh4a/clock-sh7785.c | |
3 | * | |
4 | * SH7785 support for the clock framework | |
5 | * | |
c55fbdd3 | 6 | * Copyright (C) 2007 - 2010 Paul Mundt |
32351a28 PM |
7 | * |
8 | * This file is subject to the terms and conditions of the GNU General Public | |
9 | * License. See the file "COPYING" in the main directory of this archive | |
10 | * for more details. | |
11 | */ | |
12 | #include <linux/init.h> | |
13 | #include <linux/kernel.h> | |
a77b5ac0 PM |
14 | #include <linux/clk.h> |
15 | #include <linux/io.h> | |
cc96eace | 16 | #include <linux/cpufreq.h> |
6d803ba7 | 17 | #include <linux/clkdev.h> |
32351a28 PM |
18 | #include <asm/clock.h> |
19 | #include <asm/freq.h> | |
1823f6d5 | 20 | #include <cpu/sh7785.h> |
32351a28 | 21 | |
43909a93 MD |
22 | /* |
23 | * Default rate for the root input clock, reset this with clk_set_rate() | |
24 | * from the platform code. | |
25 | */ | |
26 | static struct clk extal_clk = { | |
43909a93 | 27 | .rate = 33333333, |
32351a28 PM |
28 | }; |
29 | ||
c9904dd1 MD |
30 | static unsigned long pll_recalc(struct clk *clk) |
31 | { | |
1823f6d5 MD |
32 | int multiplier; |
33 | ||
0d4fdbb6 | 34 | multiplier = test_mode_pin(MODE_PIN4) ? 36 : 72; |
1823f6d5 MD |
35 | |
36 | return clk->parent->rate * multiplier; | |
c9904dd1 MD |
37 | } |
38 | ||
39 | static struct clk_ops pll_clk_ops = { | |
40 | .recalc = pll_recalc, | |
41 | }; | |
42 | ||
c9904dd1 | 43 | static struct clk pll_clk = { |
c9904dd1 MD |
44 | .ops = &pll_clk_ops, |
45 | .parent = &extal_clk, | |
46 | .flags = CLK_ENABLE_ON_INIT, | |
47 | }; | |
48 | ||
43909a93 MD |
49 | static struct clk *clks[] = { |
50 | &extal_clk, | |
51 | &pll_clk, | |
32351a28 PM |
52 | }; |
53 | ||
43909a93 MD |
54 | static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, |
55 | 24, 32, 36, 48 }; | |
32351a28 | 56 | |
0a5f337e | 57 | static struct clk_div_mult_table div4_div_mult_table = { |
43909a93 MD |
58 | .divisors = div2, |
59 | .nr_divisors = ARRAY_SIZE(div2), | |
a77b5ac0 | 60 | }; |
32351a28 | 61 | |
0a5f337e MD |
62 | static struct clk_div4_table div4_table = { |
63 | .div_mult_table = &div4_div_mult_table, | |
64 | }; | |
65 | ||
43909a93 MD |
66 | enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA, |
67 | DIV4_DU, DIV4_P, DIV4_NR }; | |
32351a28 | 68 | |
914ebf0b MD |
69 | #define DIV4(_bit, _mask, _flags) \ |
70 | SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags) | |
32351a28 | 71 | |
43909a93 | 72 | struct clk div4_clks[DIV4_NR] = { |
914ebf0b MD |
73 | [DIV4_P] = DIV4(0, 0x0f80, 0), |
74 | [DIV4_DU] = DIV4(4, 0x0ff0, 0), | |
75 | [DIV4_GA] = DIV4(8, 0x0030, 0), | |
76 | [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT), | |
77 | [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT), | |
78 | [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT), | |
79 | [DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT), | |
80 | [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT), | |
32351a28 PM |
81 | }; |
82 | ||
549b5e35 PM |
83 | #define MSTPCR0 0xffc80030 |
84 | #define MSTPCR1 0xffc80034 | |
85 | ||
5b10a27e MD |
86 | enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, |
87 | MSTP021, MSTP020, MSTP017, MSTP016, | |
88 | MSTP013, MSTP012, MSTP009, MSTP008, MSTP003, MSTP002, | |
89 | MSTP119, MSTP117, MSTP105, MSTP104, MSTP100, | |
90 | MSTP_NR }; | |
91 | ||
92 | static struct clk mstp_clks[MSTP_NR] = { | |
549b5e35 | 93 | /* MSTPCR0 */ |
c77a9c3e MD |
94 | [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), |
95 | [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), | |
96 | [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), | |
97 | [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), | |
98 | [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), | |
99 | [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), | |
100 | [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), | |
101 | [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0), | |
102 | [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0), | |
103 | [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), | |
104 | [MSTP013] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 13, 0), | |
105 | [MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0), | |
106 | [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), | |
107 | [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), | |
108 | [MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0), | |
109 | [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0), | |
549b5e35 PM |
110 | |
111 | /* MSTPCR1 */ | |
c77a9c3e MD |
112 | [MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0), |
113 | [MSTP117] = SH_CLK_MSTP32(NULL, MSTPCR1, 17, 0), | |
114 | [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0), | |
115 | [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0), | |
116 | [MSTP100] = SH_CLK_MSTP32(NULL, MSTPCR1, 0, 0), | |
549b5e35 PM |
117 | }; |
118 | ||
eb85dcaa MD |
119 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } |
120 | ||
c55fbdd3 | 121 | static struct clk_lookup lookups[] = { |
4a81fe62 MD |
122 | /* main clocks */ |
123 | CLKDEV_CON_ID("extal", &extal_clk), | |
124 | CLKDEV_CON_ID("pll_clk", &pll_clk), | |
125 | ||
956f7f44 MD |
126 | /* DIV4 clocks */ |
127 | CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), | |
128 | CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]), | |
129 | CLKDEV_CON_ID("ga_clk", &div4_clks[DIV4_GA]), | |
130 | CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]), | |
131 | CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), | |
132 | CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), | |
133 | CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), | |
134 | CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), | |
135 | ||
eb85dcaa MD |
136 | /* MSTP32 clocks */ |
137 | { | |
138 | /* SCIF5 */ | |
139 | .dev_id = "sh-sci.5", | |
140 | .con_id = "sci_fck", | |
141 | .clk = &mstp_clks[MSTP029], | |
142 | }, { | |
143 | /* SCIF4 */ | |
144 | .dev_id = "sh-sci.4", | |
145 | .con_id = "sci_fck", | |
146 | .clk = &mstp_clks[MSTP028], | |
147 | }, { | |
148 | /* SCIF3 */ | |
149 | .dev_id = "sh-sci.3", | |
150 | .con_id = "sci_fck", | |
151 | .clk = &mstp_clks[MSTP027], | |
152 | }, { | |
153 | /* SCIF2 */ | |
154 | .dev_id = "sh-sci.2", | |
155 | .con_id = "sci_fck", | |
156 | .clk = &mstp_clks[MSTP026], | |
157 | }, { | |
158 | /* SCIF1 */ | |
159 | .dev_id = "sh-sci.1", | |
160 | .con_id = "sci_fck", | |
161 | .clk = &mstp_clks[MSTP025], | |
162 | }, { | |
163 | /* SCIF0 */ | |
164 | .dev_id = "sh-sci.0", | |
165 | .con_id = "sci_fck", | |
166 | .clk = &mstp_clks[MSTP024], | |
167 | }, | |
168 | CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]), | |
169 | CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]), | |
170 | CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]), | |
171 | CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]), | |
172 | CLKDEV_CON_ID("mmcif_fck", &mstp_clks[MSTP013]), | |
173 | CLKDEV_CON_ID("flctl_fck", &mstp_clks[MSTP012]), | |
c55fbdd3 PM |
174 | { |
175 | /* TMU0 */ | |
176 | .dev_id = "sh_tmu.0", | |
177 | .con_id = "tmu_fck", | |
5b10a27e | 178 | .clk = &mstp_clks[MSTP008], |
c55fbdd3 PM |
179 | }, { |
180 | /* TMU1 */ | |
181 | .dev_id = "sh_tmu.1", | |
182 | .con_id = "tmu_fck", | |
5b10a27e | 183 | .clk = &mstp_clks[MSTP008], |
c55fbdd3 PM |
184 | }, { |
185 | /* TMU2 */ | |
186 | .dev_id = "sh_tmu.2", | |
187 | .con_id = "tmu_fck", | |
5b10a27e | 188 | .clk = &mstp_clks[MSTP008], |
c55fbdd3 PM |
189 | }, { |
190 | /* TMU3 */ | |
191 | .dev_id = "sh_tmu.3", | |
192 | .con_id = "tmu_fck", | |
5b10a27e | 193 | .clk = &mstp_clks[MSTP009], |
c55fbdd3 PM |
194 | }, { |
195 | /* TMU4 */ | |
196 | .dev_id = "sh_tmu.4", | |
197 | .con_id = "tmu_fck", | |
5b10a27e | 198 | .clk = &mstp_clks[MSTP009], |
c55fbdd3 PM |
199 | }, { |
200 | /* TMU5 */ | |
201 | .dev_id = "sh_tmu.5", | |
202 | .con_id = "tmu_fck", | |
5b10a27e | 203 | .clk = &mstp_clks[MSTP009], |
c55fbdd3 | 204 | }, |
eb85dcaa MD |
205 | CLKDEV_CON_ID("siof_fck", &mstp_clks[MSTP003]), |
206 | CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]), | |
207 | CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]), | |
208 | CLKDEV_CON_ID("ubc_fck", &mstp_clks[MSTP117]), | |
209 | CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]), | |
210 | CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]), | |
211 | CLKDEV_CON_ID("gdta_fck", &mstp_clks[MSTP100]), | |
c55fbdd3 PM |
212 | }; |
213 | ||
9fe5ee0e | 214 | int __init arch_clk_init(void) |
32351a28 | 215 | { |
f5c84cf5 | 216 | int i, ret = 0; |
32351a28 | 217 | |
a77b5ac0 PM |
218 | for (i = 0; i < ARRAY_SIZE(clks); i++) |
219 | ret |= clk_register(clks[i]); | |
c55fbdd3 PM |
220 | for (i = 0; i < ARRAY_SIZE(lookups); i++) |
221 | clkdev_add(&lookups[i]); | |
e89d53e6 | 222 | |
43909a93 MD |
223 | if (!ret) |
224 | ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), | |
225 | &div4_table); | |
e89d53e6 | 226 | if (!ret) |
5b10a27e | 227 | ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); |
32351a28 | 228 | |
f5c84cf5 | 229 | return ret; |
32351a28 | 230 | } |