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32351a28 PM |
1 | /* |
2 | * arch/sh/kernel/cpu/sh4a/clock-sh7785.c | |
3 | * | |
4 | * SH7785 support for the clock framework | |
5 | * | |
a77b5ac0 | 6 | * Copyright (C) 2007 - 2009 Paul Mundt |
32351a28 PM |
7 | * |
8 | * This file is subject to the terms and conditions of the GNU General Public | |
9 | * License. See the file "COPYING" in the main directory of this archive | |
10 | * for more details. | |
11 | */ | |
12 | #include <linux/init.h> | |
13 | #include <linux/kernel.h> | |
a77b5ac0 PM |
14 | #include <linux/clk.h> |
15 | #include <linux/io.h> | |
cc96eace | 16 | #include <linux/cpufreq.h> |
32351a28 PM |
17 | #include <asm/clock.h> |
18 | #include <asm/freq.h> | |
1823f6d5 | 19 | #include <cpu/sh7785.h> |
32351a28 | 20 | |
43909a93 MD |
21 | /* |
22 | * Default rate for the root input clock, reset this with clk_set_rate() | |
23 | * from the platform code. | |
24 | */ | |
25 | static struct clk extal_clk = { | |
26 | .name = "extal", | |
27 | .id = -1, | |
28 | .rate = 33333333, | |
32351a28 PM |
29 | }; |
30 | ||
c9904dd1 MD |
31 | static unsigned long pll_recalc(struct clk *clk) |
32 | { | |
1823f6d5 MD |
33 | int multiplier; |
34 | ||
0d4fdbb6 | 35 | multiplier = test_mode_pin(MODE_PIN4) ? 36 : 72; |
1823f6d5 MD |
36 | |
37 | return clk->parent->rate * multiplier; | |
c9904dd1 MD |
38 | } |
39 | ||
40 | static struct clk_ops pll_clk_ops = { | |
41 | .recalc = pll_recalc, | |
42 | }; | |
43 | ||
c9904dd1 MD |
44 | static struct clk pll_clk = { |
45 | .name = "pll_clk", | |
46 | .id = -1, | |
47 | .ops = &pll_clk_ops, | |
48 | .parent = &extal_clk, | |
49 | .flags = CLK_ENABLE_ON_INIT, | |
50 | }; | |
51 | ||
43909a93 MD |
52 | static struct clk *clks[] = { |
53 | &extal_clk, | |
54 | &pll_clk, | |
32351a28 PM |
55 | }; |
56 | ||
43909a93 MD |
57 | static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, |
58 | 24, 32, 36, 48 }; | |
32351a28 | 59 | |
43909a93 MD |
60 | static struct clk_div_mult_table div4_table = { |
61 | .divisors = div2, | |
62 | .nr_divisors = ARRAY_SIZE(div2), | |
a77b5ac0 | 63 | }; |
32351a28 | 64 | |
43909a93 MD |
65 | enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA, |
66 | DIV4_DU, DIV4_P, DIV4_NR }; | |
32351a28 | 67 | |
43909a93 MD |
68 | #define DIV4(_str, _bit, _mask, _flags) \ |
69 | SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags) | |
32351a28 | 70 | |
43909a93 MD |
71 | struct clk div4_clks[DIV4_NR] = { |
72 | [DIV4_P] = DIV4("peripheral_clk", 0, 0x0f80, 0), | |
73 | [DIV4_DU] = DIV4("du_clk", 4, 0x0ff0, 0), | |
74 | [DIV4_GA] = DIV4("ga_clk", 8, 0x0030, 0), | |
75 | [DIV4_DDR] = DIV4("ddr_clk", 12, 0x000c, CLK_ENABLE_ON_INIT), | |
76 | [DIV4_B] = DIV4("bus_clk", 16, 0x0fe0, CLK_ENABLE_ON_INIT), | |
77 | [DIV4_SH] = DIV4("shyway_clk", 20, 0x000c, CLK_ENABLE_ON_INIT), | |
78 | [DIV4_U] = DIV4("umem_clk", 24, 0x000c, CLK_ENABLE_ON_INIT), | |
79 | [DIV4_I] = DIV4("cpu_clk", 28, 0x000e, CLK_ENABLE_ON_INIT), | |
32351a28 PM |
80 | }; |
81 | ||
549b5e35 PM |
82 | #define MSTPCR0 0xffc80030 |
83 | #define MSTPCR1 0xffc80034 | |
84 | ||
e89d53e6 | 85 | static struct clk mstp_clks[] = { |
549b5e35 | 86 | /* MSTPCR0 */ |
43909a93 MD |
87 | SH_CLK_MSTP32("scif_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0), |
88 | SH_CLK_MSTP32("scif_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0), | |
89 | SH_CLK_MSTP32("scif_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0), | |
90 | SH_CLK_MSTP32("scif_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0), | |
91 | SH_CLK_MSTP32("scif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0), | |
92 | SH_CLK_MSTP32("scif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0), | |
93 | SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0), | |
94 | SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0), | |
95 | SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0), | |
96 | SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0), | |
97 | SH_CLK_MSTP32("mmcif_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 13, 0), | |
98 | SH_CLK_MSTP32("flctl_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 12, 0), | |
99 | SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0), | |
100 | SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0), | |
101 | SH_CLK_MSTP32("siof_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 3, 0), | |
102 | SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0), | |
549b5e35 PM |
103 | |
104 | /* MSTPCR1 */ | |
e89d53e6 MD |
105 | SH_CLK_MSTP32("hudi_fck", -1, NULL, MSTPCR1, 19, 0), |
106 | SH_CLK_MSTP32("ubc_fck", -1, NULL, MSTPCR1, 17, 0), | |
107 | SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0), | |
108 | SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0), | |
109 | SH_CLK_MSTP32("gdta_fck", -1, NULL, MSTPCR1, 0, 0), | |
549b5e35 PM |
110 | }; |
111 | ||
9fe5ee0e | 112 | int __init arch_clk_init(void) |
32351a28 | 113 | { |
f5c84cf5 | 114 | int i, ret = 0; |
32351a28 | 115 | |
a77b5ac0 PM |
116 | for (i = 0; i < ARRAY_SIZE(clks); i++) |
117 | ret |= clk_register(clks[i]); | |
e89d53e6 | 118 | |
43909a93 MD |
119 | if (!ret) |
120 | ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), | |
121 | &div4_table); | |
e89d53e6 MD |
122 | if (!ret) |
123 | ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); | |
32351a28 | 124 | |
f5c84cf5 | 125 | return ret; |
32351a28 | 126 | } |