Commit | Line | Data |
---|---|---|
36ddf31b | 1 | /* |
58862699 | 2 | * arch/sh/kernel/cpu/sh4a/clock-sh7780.c |
36ddf31b PM |
3 | * |
4 | * SH7780 support for the clock framework | |
5 | * | |
6 | * Copyright (C) 2005 Paul Mundt | |
7 | * | |
8 | * This file is subject to the terms and conditions of the GNU General Public | |
9 | * License. See the file "COPYING" in the main directory of this archive | |
10 | * for more details. | |
11 | */ | |
12 | #include <linux/init.h> | |
13 | #include <linux/kernel.h> | |
29497ec4 | 14 | #include <linux/io.h> |
6d803ba7 | 15 | #include <linux/clkdev.h> |
36ddf31b PM |
16 | #include <asm/clock.h> |
17 | #include <asm/freq.h> | |
18 | #include <asm/io.h> | |
19 | ||
20 | static int ifc_divisors[] = { 2, 4 }; | |
21 | static int bfc_divisors[] = { 1, 1, 1, 8, 12, 16, 24, 1 }; | |
22 | static int pfc_divisors[] = { 1, 24, 24, 1 }; | |
23 | static int cfc_divisors[] = { 1, 1, 4, 1, 6, 1, 1, 1 }; | |
24 | ||
25 | static void master_clk_init(struct clk *clk) | |
26 | { | |
9d56dd3b | 27 | clk->rate *= pfc_divisors[__raw_readl(FRQCR) & 0x0003]; |
36ddf31b PM |
28 | } |
29 | ||
30 | static struct clk_ops sh7780_master_clk_ops = { | |
31 | .init = master_clk_init, | |
32 | }; | |
33 | ||
b68d8201 | 34 | static unsigned long module_clk_recalc(struct clk *clk) |
36ddf31b | 35 | { |
9d56dd3b | 36 | int idx = (__raw_readl(FRQCR) & 0x0003); |
b68d8201 | 37 | return clk->parent->rate / pfc_divisors[idx]; |
36ddf31b PM |
38 | } |
39 | ||
40 | static struct clk_ops sh7780_module_clk_ops = { | |
41 | .recalc = module_clk_recalc, | |
42 | }; | |
43 | ||
b68d8201 | 44 | static unsigned long bus_clk_recalc(struct clk *clk) |
36ddf31b | 45 | { |
9d56dd3b | 46 | int idx = ((__raw_readl(FRQCR) >> 16) & 0x0007); |
b68d8201 | 47 | return clk->parent->rate / bfc_divisors[idx]; |
36ddf31b PM |
48 | } |
49 | ||
50 | static struct clk_ops sh7780_bus_clk_ops = { | |
51 | .recalc = bus_clk_recalc, | |
52 | }; | |
53 | ||
b68d8201 | 54 | static unsigned long cpu_clk_recalc(struct clk *clk) |
36ddf31b | 55 | { |
9d56dd3b | 56 | int idx = ((__raw_readl(FRQCR) >> 24) & 0x0001); |
b68d8201 | 57 | return clk->parent->rate / ifc_divisors[idx]; |
36ddf31b PM |
58 | } |
59 | ||
60 | static struct clk_ops sh7780_cpu_clk_ops = { | |
61 | .recalc = cpu_clk_recalc, | |
62 | }; | |
63 | ||
64 | static struct clk_ops *sh7780_clk_ops[] = { | |
65 | &sh7780_master_clk_ops, | |
66 | &sh7780_module_clk_ops, | |
67 | &sh7780_bus_clk_ops, | |
68 | &sh7780_cpu_clk_ops, | |
69 | }; | |
70 | ||
71 | void __init arch_init_clk_ops(struct clk_ops **ops, int idx) | |
72 | { | |
73 | if (idx < ARRAY_SIZE(sh7780_clk_ops)) | |
74 | *ops = sh7780_clk_ops[idx]; | |
75 | } | |
76 | ||
b68d8201 | 77 | static unsigned long shyway_clk_recalc(struct clk *clk) |
36ddf31b | 78 | { |
9d56dd3b | 79 | int idx = ((__raw_readl(FRQCR) >> 20) & 0x0007); |
b68d8201 | 80 | return clk->parent->rate / cfc_divisors[idx]; |
36ddf31b PM |
81 | } |
82 | ||
83 | static struct clk_ops sh7780_shyway_clk_ops = { | |
84 | .recalc = shyway_clk_recalc, | |
85 | }; | |
86 | ||
87 | static struct clk sh7780_shyway_clk = { | |
4ff29ff8 | 88 | .flags = CLK_ENABLE_ON_INIT, |
36ddf31b PM |
89 | .ops = &sh7780_shyway_clk_ops, |
90 | }; | |
91 | ||
92 | /* | |
93 | * Additional SH7780-specific on-chip clocks that aren't already part of the | |
94 | * clock framework | |
95 | */ | |
96 | static struct clk *sh7780_onchip_clocks[] = { | |
97 | &sh7780_shyway_clk, | |
98 | }; | |
99 | ||
29497ec4 MD |
100 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } |
101 | ||
102 | static struct clk_lookup lookups[] = { | |
103 | /* main clocks */ | |
104 | CLKDEV_CON_ID("shyway_clk", &sh7780_shyway_clk), | |
105 | }; | |
106 | ||
9fe5ee0e | 107 | int __init arch_clk_init(void) |
36ddf31b | 108 | { |
253b0887 | 109 | struct clk *clk; |
f5c84cf5 | 110 | int i, ret = 0; |
36ddf31b | 111 | |
253b0887 PM |
112 | cpg_clk_init(); |
113 | ||
114 | clk = clk_get(NULL, "master_clk"); | |
36ddf31b PM |
115 | for (i = 0; i < ARRAY_SIZE(sh7780_onchip_clocks); i++) { |
116 | struct clk *clkp = sh7780_onchip_clocks[i]; | |
117 | ||
118 | clkp->parent = clk; | |
f5c84cf5 | 119 | ret |= clk_register(clkp); |
36ddf31b PM |
120 | } |
121 | ||
36ddf31b PM |
122 | clk_put(clk); |
123 | ||
29497ec4 MD |
124 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); |
125 | ||
f5c84cf5 | 126 | return ret; |
36ddf31b | 127 | } |