Commit | Line | Data |
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c01f0f1a YS |
1 | /* |
2 | * arch/sh/kernel/cpu/sh4/clock-sh7757.c | |
3 | * | |
4 | * SH7757 support for the clock framework | |
5 | * | |
56c52986 | 6 | * Copyright (C) 2009-2010 Renesas Solutions Corp. |
c01f0f1a YS |
7 | * |
8 | * This file is subject to the terms and conditions of the GNU General Public | |
9 | * License. See the file "COPYING" in the main directory of this archive | |
10 | * for more details. | |
11 | */ | |
12 | #include <linux/init.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/io.h> | |
6d803ba7 | 15 | #include <linux/clkdev.h> |
c01f0f1a YS |
16 | #include <asm/clock.h> |
17 | #include <asm/freq.h> | |
18 | ||
56c52986 YS |
19 | /* |
20 | * Default rate for the root input clock, reset this with clk_set_rate() | |
21 | * from the platform code. | |
22 | */ | |
23 | static struct clk extal_clk = { | |
24 | .rate = 48000000, | |
25 | }; | |
c01f0f1a | 26 | |
56c52986 | 27 | static unsigned long pll_recalc(struct clk *clk) |
c01f0f1a | 28 | { |
56c52986 | 29 | int multiplier; |
c01f0f1a | 30 | |
56c52986 | 31 | multiplier = test_mode_pin(MODE_PIN0) ? 24 : 16; |
c01f0f1a | 32 | |
56c52986 | 33 | return clk->parent->rate * multiplier; |
c01f0f1a YS |
34 | } |
35 | ||
33cb61a4 | 36 | static struct sh_clk_ops pll_clk_ops = { |
56c52986 | 37 | .recalc = pll_recalc, |
c01f0f1a YS |
38 | }; |
39 | ||
56c52986 YS |
40 | static struct clk pll_clk = { |
41 | .ops = &pll_clk_ops, | |
42 | .parent = &extal_clk, | |
43 | .flags = CLK_ENABLE_ON_INIT, | |
44 | }; | |
c01f0f1a | 45 | |
56c52986 YS |
46 | static struct clk *clks[] = { |
47 | &extal_clk, | |
48 | &pll_clk, | |
c01f0f1a YS |
49 | }; |
50 | ||
56c52986 YS |
51 | static unsigned int div2[] = { 1, 1, 2, 1, 1, 4, 1, 6, |
52 | 1, 1, 1, 16, 1, 24, 1, 1 }; | |
c01f0f1a | 53 | |
56c52986 YS |
54 | static struct clk_div_mult_table div4_div_mult_table = { |
55 | .divisors = div2, | |
56 | .nr_divisors = ARRAY_SIZE(div2), | |
c01f0f1a YS |
57 | }; |
58 | ||
56c52986 YS |
59 | static struct clk_div4_table div4_table = { |
60 | .div_mult_table = &div4_div_mult_table, | |
c01f0f1a YS |
61 | }; |
62 | ||
56c52986 | 63 | enum { DIV4_I, DIV4_SH, DIV4_P, DIV4_NR }; |
c01f0f1a | 64 | |
56c52986 YS |
65 | #define DIV4(_bit, _mask, _flags) \ |
66 | SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags) | |
c01f0f1a | 67 | |
56c52986 YS |
68 | struct clk div4_clks[DIV4_NR] = { |
69 | /* | |
70 | * P clock is always enable, because some P clock modules is used | |
71 | * by Host PC. | |
72 | */ | |
73 | [DIV4_P] = DIV4(0, 0x2800, CLK_ENABLE_ON_INIT), | |
74 | [DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT), | |
75 | [DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT), | |
c01f0f1a YS |
76 | }; |
77 | ||
56c52986 YS |
78 | #define MSTPCR0 0xffc80030 |
79 | #define MSTPCR1 0xffc80034 | |
53bc18ef | 80 | #define MSTPCR2 0xffc10028 |
56c52986 | 81 | |
fb434065 | 82 | enum { MSTP004, MSTP000, MSTP127, MSTP114, MSTP113, MSTP112, |
53bc18ef | 83 | MSTP111, MSTP110, MSTP103, MSTP102, MSTP220, |
56c52986 YS |
84 | MSTP_NR }; |
85 | ||
86 | static struct clk mstp_clks[MSTP_NR] = { | |
87 | /* MSTPCR0 */ | |
88 | [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0), | |
89 | [MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0), | |
90 | ||
91 | /* MSTPCR1 */ | |
fb434065 | 92 | [MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 27, 0), |
56c52986 YS |
93 | [MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0), |
94 | [MSTP113] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 13, 0), | |
95 | [MSTP112] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 12, 0), | |
96 | [MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0), | |
97 | [MSTP110] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 10, 0), | |
98 | [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0), | |
99 | [MSTP102] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 2, 0), | |
53bc18ef YS |
100 | |
101 | /* MSTPCR2 */ | |
102 | [MSTP220] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 20, 0), | |
c01f0f1a YS |
103 | }; |
104 | ||
f0e7f902 MD |
105 | static struct clk_lookup lookups[] = { |
106 | /* main clocks */ | |
56c52986 YS |
107 | CLKDEV_CON_ID("extal", &extal_clk), |
108 | CLKDEV_CON_ID("pll_clk", &pll_clk), | |
109 | ||
110 | /* DIV4 clocks */ | |
111 | CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), | |
112 | CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), | |
113 | CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), | |
114 | ||
115 | /* MSTP32 clocks */ | |
a052d2c3 | 116 | CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP004]), |
5261b0a2 YS |
117 | CLKDEV_CON_ID("riic0", &mstp_clks[MSTP000]), |
118 | CLKDEV_CON_ID("riic1", &mstp_clks[MSTP000]), | |
119 | CLKDEV_CON_ID("riic2", &mstp_clks[MSTP000]), | |
120 | CLKDEV_CON_ID("riic3", &mstp_clks[MSTP000]), | |
121 | CLKDEV_CON_ID("riic4", &mstp_clks[MSTP000]), | |
122 | CLKDEV_CON_ID("riic5", &mstp_clks[MSTP000]), | |
123 | CLKDEV_CON_ID("riic6", &mstp_clks[MSTP000]), | |
124 | CLKDEV_CON_ID("riic7", &mstp_clks[MSTP000]), | |
9b417571 KM |
125 | |
126 | CLKDEV_ICK_ID("tmu_fck", "sh_tmu.0", &mstp_clks[MSTP113]), | |
127 | CLKDEV_ICK_ID("tmu_fck", "sh_tmu.1", &mstp_clks[MSTP114]), | |
128 | CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP112]), | |
129 | CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP111]), | |
130 | CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP110]), | |
131 | ||
5261b0a2 | 132 | CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP103]), |
1760e371 | 133 | CLKDEV_DEV_ID("renesas_usbhs.0", &mstp_clks[MSTP102]), |
53bc18ef | 134 | CLKDEV_CON_ID("mmc0", &mstp_clks[MSTP220]), |
fb434065 | 135 | CLKDEV_CON_ID("rspi2", &mstp_clks[MSTP127]), |
f0e7f902 MD |
136 | }; |
137 | ||
56c52986 | 138 | int __init arch_clk_init(void) |
c01f0f1a | 139 | { |
56c52986 | 140 | int i, ret = 0; |
c01f0f1a | 141 | |
56c52986 YS |
142 | for (i = 0; i < ARRAY_SIZE(clks); i++) |
143 | ret |= clk_register(clks[i]); | |
144 | for (i = 0; i < ARRAY_SIZE(lookups); i++) | |
145 | clkdev_add(&lookups[i]); | |
c01f0f1a | 146 | |
56c52986 YS |
147 | if (!ret) |
148 | ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), | |
149 | &div4_table); | |
150 | if (!ret) | |
ad3337cb | 151 | ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); |
c01f0f1a | 152 | |
56c52986 | 153 | return ret; |
c01f0f1a YS |
154 | } |
155 |