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c521dc02 MD |
1 | /* |
2 | * arch/sh/kernel/cpu/sh4a/clock-sh7723.c | |
3 | * | |
4 | * SH7723 clock framework support | |
5 | * | |
6 | * Copyright (C) 2009 Magnus Damm | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | #include <linux/init.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/io.h> | |
24 | #include <asm/clock.h> | |
2094e504 MD |
25 | #include <asm/hwblk.h> |
26 | #include <cpu/sh7723.h> | |
c521dc02 MD |
27 | |
28 | /* SH7723 registers */ | |
29 | #define FRQCR 0xa4150000 | |
30 | #define VCLKCR 0xa4150004 | |
31 | #define SCLKACR 0xa4150008 | |
32 | #define SCLKBCR 0xa415000c | |
33 | #define IRDACLKCR 0xa4150018 | |
34 | #define PLLCR 0xa4150024 | |
c521dc02 MD |
35 | #define DLLFRQ 0xa4150050 |
36 | ||
37 | /* Fixed 32 KHz root clock for RTC and Power Management purposes */ | |
38 | static struct clk r_clk = { | |
39 | .name = "rclk", | |
40 | .id = -1, | |
41 | .rate = 32768, | |
42 | }; | |
43 | ||
44 | /* | |
45 | * Default rate for the root input clock, reset this with clk_set_rate() | |
46 | * from the platform code. | |
47 | */ | |
48 | struct clk extal_clk = { | |
49 | .name = "extal", | |
50 | .id = -1, | |
51 | .rate = 33333333, | |
52 | }; | |
53 | ||
54 | /* The dll multiplies the 32khz r_clk, may be used instead of extal */ | |
55 | static unsigned long dll_recalc(struct clk *clk) | |
56 | { | |
57 | unsigned long mult; | |
58 | ||
59 | if (__raw_readl(PLLCR) & 0x1000) | |
60 | mult = __raw_readl(DLLFRQ); | |
61 | else | |
62 | mult = 0; | |
63 | ||
64 | return clk->parent->rate * mult; | |
65 | } | |
66 | ||
67 | static struct clk_ops dll_clk_ops = { | |
68 | .recalc = dll_recalc, | |
69 | }; | |
70 | ||
71 | static struct clk dll_clk = { | |
72 | .name = "dll_clk", | |
73 | .id = -1, | |
74 | .ops = &dll_clk_ops, | |
75 | .parent = &r_clk, | |
76 | .flags = CLK_ENABLE_ON_INIT, | |
77 | }; | |
78 | ||
79 | static unsigned long pll_recalc(struct clk *clk) | |
80 | { | |
81 | unsigned long mult = 1; | |
82 | unsigned long div = 1; | |
83 | ||
84 | if (__raw_readl(PLLCR) & 0x4000) | |
85 | mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); | |
86 | else | |
87 | div = 2; | |
88 | ||
89 | return (clk->parent->rate * mult) / div; | |
90 | } | |
91 | ||
92 | static struct clk_ops pll_clk_ops = { | |
93 | .recalc = pll_recalc, | |
94 | }; | |
95 | ||
96 | static struct clk pll_clk = { | |
97 | .name = "pll_clk", | |
98 | .id = -1, | |
99 | .ops = &pll_clk_ops, | |
100 | .flags = CLK_ENABLE_ON_INIT, | |
101 | }; | |
102 | ||
103 | struct clk *main_clks[] = { | |
104 | &r_clk, | |
105 | &extal_clk, | |
106 | &dll_clk, | |
107 | &pll_clk, | |
108 | }; | |
109 | ||
110 | static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; | |
111 | static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 }; | |
112 | ||
113 | static struct clk_div_mult_table div4_table = { | |
114 | .divisors = divisors, | |
115 | .nr_divisors = ARRAY_SIZE(divisors), | |
116 | .multipliers = multipliers, | |
117 | .nr_multipliers = ARRAY_SIZE(multipliers), | |
118 | }; | |
119 | ||
120 | enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, | |
121 | DIV4_SIUA, DIV4_SIUB, DIV4_IRDA, DIV4_NR }; | |
122 | ||
123 | #define DIV4(_str, _reg, _bit, _mask, _flags) \ | |
124 | SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) | |
125 | ||
126 | struct clk div4_clks[DIV4_NR] = { | |
127 | [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT), | |
128 | [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT), | |
129 | [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT), | |
130 | [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT), | |
131 | [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT), | |
132 | [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x0dbf, 0), | |
133 | [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x0dbf, 0), | |
134 | [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x0dbf, 0), | |
135 | [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x0dbf, 0), | |
136 | }; | |
137 | ||
138 | struct clk div6_clks[] = { | |
139 | SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0), | |
140 | }; | |
141 | ||
2094e504 MD |
142 | #define R_CLK (&r_clk) |
143 | #define P_CLK (&div4_clks[DIV4_P]) | |
144 | #define B_CLK (&div4_clks[DIV4_B]) | |
145 | #define U_CLK (&div4_clks[DIV4_U]) | |
146 | #define I_CLK (&div4_clks[DIV4_I]) | |
147 | #define SH_CLK (&div4_clks[DIV4_SH]) | |
c521dc02 MD |
148 | |
149 | static struct clk mstp_clks[] = { | |
150 | /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */ | |
2094e504 MD |
151 | SH_HWBLK_CLK("tlb0", -1, I_CLK, HWBLK_TLB, CLK_ENABLE_ON_INIT), |
152 | SH_HWBLK_CLK("ic0", -1, I_CLK, HWBLK_IC, CLK_ENABLE_ON_INIT), | |
153 | SH_HWBLK_CLK("oc0", -1, I_CLK, HWBLK_OC, CLK_ENABLE_ON_INIT), | |
154 | SH_HWBLK_CLK("l2c0", -1, SH_CLK, HWBLK_L2C, CLK_ENABLE_ON_INIT), | |
155 | SH_HWBLK_CLK("ilmem0", -1, I_CLK, HWBLK_ILMEM, CLK_ENABLE_ON_INIT), | |
156 | SH_HWBLK_CLK("fpu0", -1, I_CLK, HWBLK_FPU, CLK_ENABLE_ON_INIT), | |
157 | SH_HWBLK_CLK("intc0", -1, I_CLK, HWBLK_INTC, CLK_ENABLE_ON_INIT), | |
158 | SH_HWBLK_CLK("dmac0", -1, B_CLK, HWBLK_DMAC0, 0), | |
159 | SH_HWBLK_CLK("sh0", -1, SH_CLK, HWBLK_SHYWAY, CLK_ENABLE_ON_INIT), | |
160 | SH_HWBLK_CLK("hudi0", -1, P_CLK, HWBLK_HUDI, 0), | |
161 | SH_HWBLK_CLK("ubc0", -1, I_CLK, HWBLK_UBC, 0), | |
162 | SH_HWBLK_CLK("tmu0", -1, P_CLK, HWBLK_TMU0, 0), | |
163 | SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0), | |
164 | SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0), | |
165 | SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0), | |
166 | SH_HWBLK_CLK("tmu1", -1, P_CLK, HWBLK_TMU1, 0), | |
167 | SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0), | |
168 | SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0), | |
169 | SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0), | |
170 | SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0), | |
171 | SH_HWBLK_CLK("scif3", -1, B_CLK, HWBLK_SCIF3, 0), | |
172 | SH_HWBLK_CLK("scif4", -1, B_CLK, HWBLK_SCIF4, 0), | |
173 | SH_HWBLK_CLK("scif5", -1, B_CLK, HWBLK_SCIF5, 0), | |
174 | SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0), | |
175 | SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0), | |
176 | SH_HWBLK_CLK("meram0", -1, SH_CLK, HWBLK_MERAM, 0), | |
177 | ||
178 | SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC, 0), | |
179 | SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0), | |
180 | ||
181 | SH_HWBLK_CLK("atapi0", -1, SH_CLK, HWBLK_ATAPI, 0), | |
182 | SH_HWBLK_CLK("adc0", -1, P_CLK, HWBLK_ADC, 0), | |
183 | SH_HWBLK_CLK("tpu0", -1, B_CLK, HWBLK_TPU, 0), | |
184 | SH_HWBLK_CLK("irda0", -1, P_CLK, HWBLK_IRDA, 0), | |
185 | SH_HWBLK_CLK("tsif0", -1, B_CLK, HWBLK_TSIF, 0), | |
186 | SH_HWBLK_CLK("icb0", -1, B_CLK, HWBLK_ICB, CLK_ENABLE_ON_INIT), | |
187 | SH_HWBLK_CLK("sdhi0", -1, B_CLK, HWBLK_SDHI0, 0), | |
188 | SH_HWBLK_CLK("sdhi1", -1, B_CLK, HWBLK_SDHI1, 0), | |
189 | SH_HWBLK_CLK("keysc0", -1, R_CLK, HWBLK_KEYSC, 0), | |
190 | SH_HWBLK_CLK("usb0", -1, B_CLK, HWBLK_USB, 0), | |
191 | SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0), | |
192 | SH_HWBLK_CLK("siu0", -1, B_CLK, HWBLK_SIU, 0), | |
cc58f597 | 193 | SH_HWBLK_CLK("veu1", -1, B_CLK, HWBLK_VEU2H1, 0), |
2094e504 MD |
194 | SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0), |
195 | SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU, 0), | |
196 | SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU, 0), | |
cc58f597 MD |
197 | SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU2H0, 0), |
198 | SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0), | |
2094e504 | 199 | SH_HWBLK_CLK("lcdc0", -1, B_CLK, HWBLK_LCDC, 0), |
c521dc02 MD |
200 | }; |
201 | ||
202 | int __init arch_clk_init(void) | |
203 | { | |
204 | int k, ret = 0; | |
205 | ||
206 | /* autodetect extal or dll configuration */ | |
207 | if (__raw_readl(PLLCR) & 0x1000) | |
208 | pll_clk.parent = &dll_clk; | |
209 | else | |
210 | pll_clk.parent = &extal_clk; | |
211 | ||
212 | for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) | |
213 | ret = clk_register(main_clks[k]); | |
214 | ||
215 | if (!ret) | |
216 | ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); | |
217 | ||
218 | if (!ret) | |
219 | ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); | |
220 | ||
221 | if (!ret) | |
2094e504 | 222 | ret = sh_hwblk_clk_register(mstp_clks, ARRAY_SIZE(mstp_clks)); |
c521dc02 MD |
223 | |
224 | return ret; | |
225 | } |