[linux-2.6-block.git] / arch / sh / kernel / cpu / sh4a / clock-sh7366.c

/*
 * arch/sh/kernel/cpu/sh4a/clock-sh7366.c
 *
 * SH7366 clock framework support
 *
 * Copyright (C) 2009 Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <asm/clkdev.h>
#include <asm/clock.h>

/* SH7366 registers */
#define FRQCR		0xa4150000
#define VCLKCR		0xa4150004
#define SCLKACR		0xa4150008
#define SCLKBCR		0xa415000c
#define PLLCR		0xa4150024
#define MSTPCR0		0xa4150030
#define MSTPCR1		0xa4150034
#define MSTPCR2		0xa4150038
#define DLLFRQ		0xa4150050

/* Fixed 32 KHz root clock for RTC and Power Management purposes */
static struct clk r_clk = {
	.name           = "rclk",
	.id             = -1,
	.rate           = 32768,
};

/*
 * Default rate for the root input clock, reset this with clk_set_rate()
 * from the platform code.
 */
struct clk extal_clk = {
	.name		= "extal",
	.id		= -1,
	.rate		= 33333333,
};

/* The dll block multiplies the 32khz r_clk, may be used instead of extal */
static unsigned long dll_recalc(struct clk *clk)
{
	unsigned long mult;

	if (__raw_readl(PLLCR) & 0x1000)
		mult = __raw_readl(DLLFRQ);
	else
		mult = 0;

	return clk->parent->rate * mult;
}

static struct clk_ops dll_clk_ops = {
	.recalc		= dll_recalc,
};

static struct clk dll_clk = {
	.name           = "dll_clk",
	.id             = -1,
	.ops		= &dll_clk_ops,
	.parent		= &r_clk,
	.flags		= CLK_ENABLE_ON_INIT,
};

static unsigned long pll_recalc(struct clk *clk)
{
	unsigned long mult = 1;
	unsigned long div = 1;

	if (__raw_readl(PLLCR) & 0x4000)
		mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
	else
		div = 2;

	return (clk->parent->rate * mult) / div;
}

static struct clk_ops pll_clk_ops = {
	.recalc		= pll_recalc,
};

static struct clk pll_clk = {
	.name		= "pll_clk",
	.id		= -1,
	.ops		= &pll_clk_ops,
	.flags		= CLK_ENABLE_ON_INIT,
};

struct clk *main_clks[] = {
	&r_clk,
	&extal_clk,
	&dll_clk,
	&pll_clk,
};

static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };

static struct clk_div_mult_table div4_div_mult_table = {
	.divisors = divisors,
	.nr_divisors = ARRAY_SIZE(divisors),
	.multipliers = multipliers,
	.nr_multipliers = ARRAY_SIZE(multipliers),
};

static struct clk_div4_table div4_table = {
	.div_mult_table = &div4_div_mult_table,
};

enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
       DIV4_SIUA, DIV4_SIUB, DIV4_NR };

#define DIV4(_str, _reg, _bit, _mask, _flags) \
  SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)

struct clk div4_clks[DIV4_NR] = {
	[DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
	[DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
	[DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
	[DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
};

enum { DIV6_V, DIV6_NR };

struct clk div6_clks[DIV6_NR] = {
	[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
};

#define MSTP(_parent, _reg, _bit, _flags) \
  SH_CLK_MSTP32(_parent, _reg, _bit, _flags)

enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
       MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016,
       MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010,
       MSTP007, MSTP006, MSTP005, MSTP002, MSTP001,
       MSTP109, MSTP100,
       MSTP227, MSTP226, MSTP224, MSTP223, MSTP222, MSTP218, MSTP217,
       MSTP211, MSTP207, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
       MSTP_NR };

static struct clk mstp_clks[MSTP_NR] = {
	/* See page 52 of Datasheet V0.40: Overview -> Block Diagram */
	[MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
	[MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
	[MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
	[MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
	[MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
	[MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
	[MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
	[MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
	[MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
	[MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
	[MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
	[MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
	[MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
	[MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
	[MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
	[MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
	[MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
	[MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
	[MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
	[MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
	[MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),

	[MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),

	[MSTP227] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 27, 0),
	[MSTP226] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 26, 0),
	[MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
	[MSTP223] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 23, 0),
	[MSTP222] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 22, 0),
	[MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
	[MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
	[MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
	[MSTP207] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT),
	[MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
	[MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
	[MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
	[MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
	[MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
	[MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
};

#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }

static struct clk_lookup lookups[] = {
	/* DIV6 clocks */
	CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),

	/* MSTP32 clocks */
	CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]),
	CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]),
	CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]),
	CLKDEV_CON_ID("rsmem0", &mstp_clks[MSTP028]),
	CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
	CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
	CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
	CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
	CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
	CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]),
	CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP017]),
	CLKDEV_CON_ID("tmu_fck", &mstp_clks[MSTP015]),
	CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP014]),
	CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]),
	CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]),
	CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]),
	{
		/* SCIF0 */
		.dev_id		= "sh-sci.0",
		.con_id		= "sci_fck",
		.clk		= &mstp_clks[MSTP007],
	}, {
		/* SCIF1 */
		.dev_id		= "sh-sci.1",
		.con_id		= "sci_fck",
		.clk		= &mstp_clks[MSTP006],
	}, {
		/* SCIF2 */
		.dev_id		= "sh-sci.2",
		.con_id		= "sci_fck",
		.clk		= &mstp_clks[MSTP005],
	},
	CLKDEV_CON_ID("msiof0", &mstp_clks[MSTP002]),
	CLKDEV_CON_ID("sbr0", &mstp_clks[MSTP001]),
	CLKDEV_CON_ID("i2c0", &mstp_clks[MSTP109]),
	CLKDEV_CON_ID("icb0", &mstp_clks[MSTP227]),
	CLKDEV_CON_ID("meram0", &mstp_clks[MSTP226]),
	CLKDEV_CON_ID("dacy1", &mstp_clks[MSTP224]),
	CLKDEV_CON_ID("dacy0", &mstp_clks[MSTP223]),
	CLKDEV_CON_ID("tsif0", &mstp_clks[MSTP222]),
	CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]),
	CLKDEV_CON_ID("mmcif0", &mstp_clks[MSTP217]),
	CLKDEV_CON_ID("usbf0", &mstp_clks[MSTP211]),
	CLKDEV_CON_ID("veu1", &mstp_clks[MSTP207]),
	CLKDEV_CON_ID("vou0", &mstp_clks[MSTP205]),
	CLKDEV_CON_ID("beu0", &mstp_clks[MSTP204]),
	CLKDEV_CON_ID("ceu0", &mstp_clks[MSTP203]),
	CLKDEV_CON_ID("veu0", &mstp_clks[MSTP202]),
	CLKDEV_CON_ID("vpu0", &mstp_clks[MSTP201]),
	CLKDEV_CON_ID("lcdc0", &mstp_clks[MSTP200]),
};

int __init arch_clk_init(void)
{
	int k, ret = 0;

	/* autodetect extal or dll configuration */
	if (__raw_readl(PLLCR) & 0x1000)
		pll_clk.parent = &dll_clk;
	else
		pll_clk.parent = &extal_clk;

	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
		ret = clk_register(main_clks[k]);

	clkdev_add_table(lookups, ARRAY_SIZE(lookups));

	if (!ret)
		ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);

	if (!ret)
		ret = sh_clk_div6_register(div6_clks, DIV6_NR);

	if (!ret)
		ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);

	return ret;
}
Commit	Line	Data
4ed37394 MD	1	/*
	2	* arch/sh/kernel/cpu/sh4a/clock-sh7366.c
	3	*
	4	* SH7366 clock framework support
	5	*
	6	* Copyright (C) 2009 Magnus Damm
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
	21	#include <linux/init.h>
	22	#include <linux/kernel.h>
	23	#include <linux/io.h>
098ec49b	24	#include <asm/clkdev.h>
4ed37394 MD	25	#include <asm/clock.h>
	26
	27	/* SH7366 registers */
	28	#define FRQCR 0xa4150000
	29	#define VCLKCR 0xa4150004
	30	#define SCLKACR 0xa4150008
	31	#define SCLKBCR 0xa415000c
	32	#define PLLCR 0xa4150024
	33	#define MSTPCR0 0xa4150030
	34	#define MSTPCR1 0xa4150034
	35	#define MSTPCR2 0xa4150038
	36	#define DLLFRQ 0xa4150050
	37
	38	/* Fixed 32 KHz root clock for RTC and Power Management purposes */
	39	static struct clk r_clk = {
	40	.name = "rclk",
	41	.id = -1,
	42	.rate = 32768,
	43	};
	44
	45	/*
	46	* Default rate for the root input clock, reset this with clk_set_rate()
	47	* from the platform code.
	48	*/
	49	struct clk extal_clk = {
	50	.name = "extal",
	51	.id = -1,
	52	.rate = 33333333,
	53	};
	54
	55	/* The dll block multiplies the 32khz r_clk, may be used instead of extal */
	56	static unsigned long dll_recalc(struct clk *clk)
	57	{
	58	unsigned long mult;
	59
	60	if (__raw_readl(PLLCR) & 0x1000)
	61	mult = __raw_readl(DLLFRQ);
	62	else
	63	mult = 0;
	64
	65	return clk->parent->rate * mult;
	66	}
	67
	68	static struct clk_ops dll_clk_ops = {
	69	.recalc = dll_recalc,
	70	};
	71
	72	static struct clk dll_clk = {
	73	.name = "dll_clk",
	74	.id = -1,
	75	.ops = &dll_clk_ops,
	76	.parent = &r_clk,
	77	.flags = CLK_ENABLE_ON_INIT,
	78	};
	79
	80	static unsigned long pll_recalc(struct clk *clk)
	81	{
	82	unsigned long mult = 1;
	83	unsigned long div = 1;
	84
	85	if (__raw_readl(PLLCR) & 0x4000)
	86	mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
	87	else
	88	div = 2;
89
90	return (clk->parent->rate * mult) / div;
91	}
92
93	static struct clk_ops pll_clk_ops = {
94	.recalc = pll_recalc,
95	};
96
97	static struct clk pll_clk = {
98	.name = "pll_clk",
99	.id = -1,
100	.ops = &pll_clk_ops,
101	.flags = CLK_ENABLE_ON_INIT,
102	};
103
104	struct clk *main_clks[] = {
105	&r_clk,
106	&extal_clk,
107	&dll_clk,
108	&pll_clk,
109	};
110
111	static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
112	static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
113
0a5f337e	114	static struct clk_div_mult_table div4_div_mult_table = {
4ed37394 MD	115	.divisors = divisors,
	116	.nr_divisors = ARRAY_SIZE(divisors),
	117	.multipliers = multipliers,
	118	.nr_multipliers = ARRAY_SIZE(multipliers),
	119	};
	120
0a5f337e MD	121	static struct clk_div4_table div4_table = {
	122	.div_mult_table = &div4_div_mult_table,
	123	};
	124
4ed37394 MD	125	enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
	126	DIV4_SIUA, DIV4_SIUB, DIV4_NR };
	127
	128	#define DIV4(_str, _reg, _bit, _mask, _flags) \
	129	SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
	130
	131	struct clk div4_clks[DIV4_NR] = {
	132	[DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
	133	[DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
	134	[DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
	135	[DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
	136	[DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
	137	[DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
	138	[DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
	139	[DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
	140	};
	141
098ec49b MD	142	enum { DIV6_V, DIV6_NR };
	143
	144	struct clk div6_clks[DIV6_NR] = {
9e1985e1	145	[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
4ed37394 MD	146	};
4ed37394 MD	147
c77a9c3e MD	148	#define MSTP(_parent, _reg, _bit, _flags) \
c77a9c3e MD	149	SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
4ed37394	150
4780683a MD	151	enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
	152	MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016,
	153	MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010,
	154	MSTP007, MSTP006, MSTP005, MSTP002, MSTP001,
	155	MSTP109, MSTP100,
	156	MSTP227, MSTP226, MSTP224, MSTP223, MSTP222, MSTP218, MSTP217,
	157	MSTP211, MSTP207, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
	158	MSTP_NR };
	159
	160	static struct clk mstp_clks[MSTP_NR] = {
4ed37394	161	/* See page 52 of Datasheet V0.40: Overview -> Block Diagram */
c77a9c3e MD	162	[MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
	163	[MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
	164	[MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
	165	[MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
	166	[MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
	167	[MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
	168	[MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
	169	[MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
	170	[MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
	171	[MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
	172	[MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
	173	[MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
	174	[MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
	175	[MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
	176	[MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
	177	[MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
	178	[MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
	179	[MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
	180	[MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
	181	[MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
	182	[MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
	183
	184	[MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
	185
	186	[MSTP227] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 27, 0),
	187	[MSTP226] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 26, 0),
	188	[MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
	189	[MSTP223] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 23, 0),
	190	[MSTP222] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 22, 0),
	191	[MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
	192	[MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
	193	[MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
	194	[MSTP207] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT),
	195	[MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
	196	[MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
	197	[MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
	198	[MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
	199	[MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
	200	[MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
4ed37394 MD	201	};
4ed37394 MD	202
098ec49b MD	203	#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
	204
	205	static struct clk_lookup lookups[] = {
	206	/* DIV6 clocks */
	207	CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
b87cecef MD	208
	209	/* MSTP32 clocks */
	210	CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]),
	211	CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]),
	212	CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]),
	213	CLKDEV_CON_ID("rsmem0", &mstp_clks[MSTP028]),
	214	CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
	215	CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
	216	CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
	217	CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
	218	CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
	219	CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]),
	220	CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP017]),
	221	CLKDEV_CON_ID("tmu_fck", &mstp_clks[MSTP015]),
	222	CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP014]),
	223	CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]),
	224	CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]),
	225	CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]),
	226	{
	227	/* SCIF0 */
	228	.dev_id = "sh-sci.0",
	229	.con_id = "sci_fck",
	230	.clk = &mstp_clks[MSTP007],
	231	}, {
	232	/* SCIF1 */
	233	.dev_id = "sh-sci.1",
	234	.con_id = "sci_fck",
	235	.clk = &mstp_clks[MSTP006],
	236	}, {
	237	/* SCIF2 */
	238	.dev_id = "sh-sci.2",
	239	.con_id = "sci_fck",
	240	.clk = &mstp_clks[MSTP005],
	241	},
	242	CLKDEV_CON_ID("msiof0", &mstp_clks[MSTP002]),
	243	CLKDEV_CON_ID("sbr0", &mstp_clks[MSTP001]),
	244	CLKDEV_CON_ID("i2c0", &mstp_clks[MSTP109]),
	245	CLKDEV_CON_ID("icb0", &mstp_clks[MSTP227]),
	246	CLKDEV_CON_ID("meram0", &mstp_clks[MSTP226]),
	247	CLKDEV_CON_ID("dacy1", &mstp_clks[MSTP224]),
	248	CLKDEV_CON_ID("dacy0", &mstp_clks[MSTP223]),
	249	CLKDEV_CON_ID("tsif0", &mstp_clks[MSTP222]),
	250	CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]),
	251	CLKDEV_CON_ID("mmcif0", &mstp_clks[MSTP217]),
	252	CLKDEV_CON_ID("usbf0", &mstp_clks[MSTP211]),
	253	CLKDEV_CON_ID("veu1", &mstp_clks[MSTP207]),
	254	CLKDEV_CON_ID("vou0", &mstp_clks[MSTP205]),
	255	CLKDEV_CON_ID("beu0", &mstp_clks[MSTP204]),
	256	CLKDEV_CON_ID("ceu0", &mstp_clks[MSTP203]),
	257	CLKDEV_CON_ID("veu0", &mstp_clks[MSTP202]),
	258	CLKDEV_CON_ID("vpu0", &mstp_clks[MSTP201]),
	259	CLKDEV_CON_ID("lcdc0", &mstp_clks[MSTP200]),
098ec49b MD	260	};
098ec49b MD	261
4ed37394 MD	262	int __init arch_clk_init(void)
	263	{
	264	int k, ret = 0;
	265
	266	/* autodetect extal or dll configuration */
	267	if (__raw_readl(PLLCR) & 0x1000)
	268	pll_clk.parent = &dll_clk;
	269	else
	270	pll_clk.parent = &extal_clk;
	271
	272	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
	273	ret = clk_register(main_clks[k]);
	274
098ec49b MD	275	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
098ec49b MD	276
4ed37394 MD	277	if (!ret)
	278	ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
	279
	280	if (!ret)
098ec49b	281	ret = sh_clk_div6_register(div6_clks, DIV6_NR);
4ed37394 MD	282
4ed37394 MD	283	if (!ret)
4780683a	284	ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
4ed37394 MD	285
	286	return ret;
	287	}