[linux-2.6-block.git] / arch / sh / kernel / cpu / sh4a / clock-sh7366.c

/*
 * arch/sh/kernel/cpu/sh4a/clock-sh7366.c
 *
 * SH7366 clock framework support
 *
 * Copyright (C) 2009 Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/clkdev.h>
#include <asm/clock.h>

/* SH7366 registers */
#define FRQCR		0xa4150000
#define VCLKCR		0xa4150004
#define SCLKACR		0xa4150008
#define SCLKBCR		0xa415000c
#define PLLCR		0xa4150024
#define MSTPCR0		0xa4150030
#define MSTPCR1		0xa4150034
#define MSTPCR2		0xa4150038
#define DLLFRQ		0xa4150050

/* Fixed 32 KHz root clock for RTC and Power Management purposes */
static struct clk r_clk = {
	.rate           = 32768,
};

/*
 * Default rate for the root input clock, reset this with clk_set_rate()
 * from the platform code.
 */
struct clk extal_clk = {
	.rate		= 33333333,
};

/* The dll block multiplies the 32khz r_clk, may be used instead of extal */
static unsigned long dll_recalc(struct clk *clk)
{
	unsigned long mult;

	if (__raw_readl(PLLCR) & 0x1000)
		mult = __raw_readl(DLLFRQ);
	else
		mult = 0;

	return clk->parent->rate * mult;
}

static struct sh_clk_ops dll_clk_ops = {
	.recalc		= dll_recalc,
};

static struct clk dll_clk = {
	.ops		= &dll_clk_ops,
	.parent		= &r_clk,
	.flags		= CLK_ENABLE_ON_INIT,
};

static unsigned long pll_recalc(struct clk *clk)
{
	unsigned long mult = 1;
	unsigned long div = 1;

	if (__raw_readl(PLLCR) & 0x4000)
		mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
	else
		div = 2;

	return (clk->parent->rate * mult) / div;
}

static struct sh_clk_ops pll_clk_ops = {
	.recalc		= pll_recalc,
};

static struct clk pll_clk = {
	.ops		= &pll_clk_ops,
	.flags		= CLK_ENABLE_ON_INIT,
};

struct clk *main_clks[] = {
	&r_clk,
	&extal_clk,
	&dll_clk,
	&pll_clk,
};

static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };

static struct clk_div_mult_table div4_div_mult_table = {
	.divisors = divisors,
	.nr_divisors = ARRAY_SIZE(divisors),
	.multipliers = multipliers,
	.nr_multipliers = ARRAY_SIZE(multipliers),
};

static struct clk_div4_table div4_table = {
	.div_mult_table = &div4_div_mult_table,
};

enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
       DIV4_SIUA, DIV4_SIUB, DIV4_NR };

#define DIV4(_reg, _bit, _mask, _flags) \
  SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)

struct clk div4_clks[DIV4_NR] = {
	[DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
	[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
	[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
	[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
	[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
};

enum { DIV6_V, DIV6_NR };

struct clk div6_clks[DIV6_NR] = {
	[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
};

#define MSTP(_parent, _reg, _bit, _flags) \
  SH_CLK_MSTP32(_parent, _reg, _bit, _flags)

enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
       MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016,
       MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010,
       MSTP007, MSTP006, MSTP005, MSTP002, MSTP001,
       MSTP109, MSTP100,
       MSTP227, MSTP226, MSTP224, MSTP223, MSTP222, MSTP218, MSTP217,
       MSTP211, MSTP207, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
       MSTP_NR };

static struct clk mstp_clks[MSTP_NR] = {
	/* See page 52 of Datasheet V0.40: Overview -> Block Diagram */
	[MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
	[MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
	[MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
	[MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
	[MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
	[MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
	[MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
	[MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
	[MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
	[MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
	[MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
	[MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
	[MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
	[MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
	[MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
	[MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
	[MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
	[MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
	[MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
	[MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
	[MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),

	[MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),

	[MSTP227] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 27, 0),
	[MSTP226] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 26, 0),
	[MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
	[MSTP223] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 23, 0),
	[MSTP222] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 22, 0),
	[MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
	[MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
	[MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
	[MSTP207] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT),
	[MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
	[MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
	[MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
	[MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
	[MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
	[MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
};

static struct clk_lookup lookups[] = {
	/* main clocks */
	CLKDEV_CON_ID("rclk", &r_clk),
	CLKDEV_CON_ID("extal", &extal_clk),
	CLKDEV_CON_ID("dll_clk", &dll_clk),
	CLKDEV_CON_ID("pll_clk", &pll_clk),

	/* DIV4 clocks */
	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
	CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
	CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
	CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
	CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
	CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
	CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]),
	CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]),

	/* DIV6 clocks */
	CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),

	/* MSTP32 clocks */
	CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]),
	CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]),
	CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]),
	CLKDEV_CON_ID("rsmem0", &mstp_clks[MSTP028]),
	CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
	CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
	CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
	CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
	CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
	CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]),
	CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP017]),
	CLKDEV_CON_ID("tmu_fck", &mstp_clks[MSTP015]),
	CLKDEV_ICK_ID("fck", "sh-cmt-32.0", &mstp_clks[MSTP014]),
	CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]),
	CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]),
	CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]),

	CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP007]),
	CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP006]),
	CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP005]),

	CLKDEV_CON_ID("msiof0", &mstp_clks[MSTP002]),
	CLKDEV_CON_ID("sbr0", &mstp_clks[MSTP001]),
	CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP109]),
	CLKDEV_CON_ID("icb0", &mstp_clks[MSTP227]),
	CLKDEV_CON_ID("meram0", &mstp_clks[MSTP226]),
	CLKDEV_CON_ID("dacy1", &mstp_clks[MSTP224]),
	CLKDEV_CON_ID("dacy0", &mstp_clks[MSTP223]),
	CLKDEV_CON_ID("tsif0", &mstp_clks[MSTP222]),
	CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]),
	CLKDEV_CON_ID("mmcif0", &mstp_clks[MSTP217]),
	CLKDEV_CON_ID("usbf0", &mstp_clks[MSTP211]),
	CLKDEV_CON_ID("veu1", &mstp_clks[MSTP207]),
	CLKDEV_CON_ID("vou0", &mstp_clks[MSTP205]),
	CLKDEV_CON_ID("beu0", &mstp_clks[MSTP204]),
	CLKDEV_CON_ID("ceu0", &mstp_clks[MSTP203]),
	CLKDEV_CON_ID("veu0", &mstp_clks[MSTP202]),
	CLKDEV_CON_ID("vpu0", &mstp_clks[MSTP201]),
	CLKDEV_CON_ID("lcdc0", &mstp_clks[MSTP200]),
};

int __init arch_clk_init(void)
{
	int k, ret = 0;

	/* autodetect extal or dll configuration */
	if (__raw_readl(PLLCR) & 0x1000)
		pll_clk.parent = &dll_clk;
	else
		pll_clk.parent = &extal_clk;

	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
		ret = clk_register(main_clks[k]);

	clkdev_add_table(lookups, ARRAY_SIZE(lookups));

	if (!ret)
		ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);

	if (!ret)
		ret = sh_clk_div6_register(div6_clks, DIV6_NR);

	if (!ret)
		ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);

	return ret;
}
Commit	Line	Data
4ed37394 MD	1	/*
	2	* arch/sh/kernel/cpu/sh4a/clock-sh7366.c
	3	*
	4	* SH7366 clock framework support
	5	*
	6	* Copyright (C) 2009 Magnus Damm
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
	21	#include <linux/init.h>
	22	#include <linux/kernel.h>
	23	#include <linux/io.h>
6d803ba7	24	#include <linux/clkdev.h>
4ed37394 MD	25	#include <asm/clock.h>
	26
	27	/* SH7366 registers */
	28	#define FRQCR 0xa4150000
	29	#define VCLKCR 0xa4150004
	30	#define SCLKACR 0xa4150008
	31	#define SCLKBCR 0xa415000c
	32	#define PLLCR 0xa4150024
	33	#define MSTPCR0 0xa4150030
	34	#define MSTPCR1 0xa4150034
	35	#define MSTPCR2 0xa4150038
	36	#define DLLFRQ 0xa4150050
	37
	38	/* Fixed 32 KHz root clock for RTC and Power Management purposes */
	39	static struct clk r_clk = {
4ed37394 MD	40	.rate = 32768,
	41	};
	42
	43	/*
	44	* Default rate for the root input clock, reset this with clk_set_rate()
	45	* from the platform code.
	46	*/
	47	struct clk extal_clk = {
4ed37394 MD	48	.rate = 33333333,
	49	};
	50
	51	/* The dll block multiplies the 32khz r_clk, may be used instead of extal */
	52	static unsigned long dll_recalc(struct clk *clk)
	53	{
	54	unsigned long mult;
	55
	56	if (__raw_readl(PLLCR) & 0x1000)
	57	mult = __raw_readl(DLLFRQ);
	58	else
	59	mult = 0;
	60
	61	return clk->parent->rate * mult;
	62	}
	63
33cb61a4	64	static struct sh_clk_ops dll_clk_ops = {
4ed37394 MD	65	.recalc = dll_recalc,
	66	};
	67
	68	static struct clk dll_clk = {
4ed37394 MD	69	.ops = &dll_clk_ops,
	70	.parent = &r_clk,
	71	.flags = CLK_ENABLE_ON_INIT,
	72	};
	73
	74	static unsigned long pll_recalc(struct clk *clk)
	75	{
	76	unsigned long mult = 1;
	77	unsigned long div = 1;
	78
	79	if (__raw_readl(PLLCR) & 0x4000)
	80	mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
	81	else
	82	div = 2;
	83
	84	return (clk->parent->rate * mult) / div;
	85	}
	86
33cb61a4	87	static struct sh_clk_ops pll_clk_ops = {
4ed37394 MD	88	.recalc = pll_recalc,
	89	};
	90
	91	static struct clk pll_clk = {
4ed37394 MD	92	.ops = &pll_clk_ops,
	93	.flags = CLK_ENABLE_ON_INIT,
	94	};
	95
	96	struct clk *main_clks[] = {
	97	&r_clk,
	98	&extal_clk,
	99	&dll_clk,
	100	&pll_clk,
	101	};
	102
	103	static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
	104	static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
	105
0a5f337e	106	static struct clk_div_mult_table div4_div_mult_table = {
4ed37394 MD	107	.divisors = divisors,
	108	.nr_divisors = ARRAY_SIZE(divisors),
	109	.multipliers = multipliers,
	110	.nr_multipliers = ARRAY_SIZE(multipliers),
	111	};
	112
0a5f337e MD	113	static struct clk_div4_table div4_table = {
	114	.div_mult_table = &div4_div_mult_table,
	115	};
	116
4ed37394 MD	117	enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
	118	DIV4_SIUA, DIV4_SIUB, DIV4_NR };
	119
914ebf0b MD	120	#define DIV4(_reg, _bit, _mask, _flags) \
914ebf0b MD	121	SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
4ed37394 MD	122
4ed37394 MD	123	struct clk div4_clks[DIV4_NR] = {
914ebf0b MD	124	[DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
	125	[DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
	126	[DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
	127	[DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
	128	[DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
	129	[DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
	130	[DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
	131	[DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
4ed37394 MD	132	};
4ed37394 MD	133
098ec49b MD	134	enum { DIV6_V, DIV6_NR };
	135
	136	struct clk div6_clks[DIV6_NR] = {
9e1985e1	137	[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
4ed37394 MD	138	};
4ed37394 MD	139
c77a9c3e MD	140	#define MSTP(_parent, _reg, _bit, _flags) \
c77a9c3e MD	141	SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
4ed37394	142
4780683a MD	143	enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
	144	MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016,
	145	MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010,
	146	MSTP007, MSTP006, MSTP005, MSTP002, MSTP001,
	147	MSTP109, MSTP100,
	148	MSTP227, MSTP226, MSTP224, MSTP223, MSTP222, MSTP218, MSTP217,
	149	MSTP211, MSTP207, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
	150	MSTP_NR };
	151
	152	static struct clk mstp_clks[MSTP_NR] = {
4ed37394	153	/* See page 52 of Datasheet V0.40: Overview -> Block Diagram */
c77a9c3e MD	154	[MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
	155	[MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
	156	[MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
	157	[MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
	158	[MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
	159	[MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
	160	[MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
	161	[MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
	162	[MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
	163	[MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
	164	[MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
	165	[MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
	166	[MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
	167	[MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
	168	[MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
	169	[MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
	170	[MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
	171	[MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
	172	[MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
	173	[MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
	174	[MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
	175
	176	[MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
	177
	178	[MSTP227] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 27, 0),
	179	[MSTP226] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 26, 0),
	180	[MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
	181	[MSTP223] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 23, 0),
	182	[MSTP222] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 22, 0),
	183	[MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
	184	[MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
	185	[MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
	186	[MSTP207] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT),
	187	[MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
	188	[MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
	189	[MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
	190	[MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
	191	[MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
	192	[MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
4ed37394 MD	193	};
4ed37394 MD	194
098ec49b	195	static struct clk_lookup lookups[] = {
59aa69d9 MD	196	/* main clocks */
	197	CLKDEV_CON_ID("rclk", &r_clk),
	198	CLKDEV_CON_ID("extal", &extal_clk),
	199	CLKDEV_CON_ID("dll_clk", &dll_clk),
	200	CLKDEV_CON_ID("pll_clk", &pll_clk),
	201
40956e75 MD	202	/* DIV4 clocks */
	203	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
	204	CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
	205	CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
	206	CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
	207	CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
	208	CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
	209	CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]),
	210	CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]),
	211
098ec49b MD	212	/* DIV6 clocks */
098ec49b MD	213	CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
b87cecef MD	214
	215	/* MSTP32 clocks */
	216	CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]),
	217	CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]),
	218	CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]),
	219	CLKDEV_CON_ID("rsmem0", &mstp_clks[MSTP028]),
	220	CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
	221	CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
	222	CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
	223	CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
	224	CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
	225	CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]),
	226	CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP017]),
	227	CLKDEV_CON_ID("tmu_fck", &mstp_clks[MSTP015]),
9b17e48c	228	CLKDEV_ICK_ID("fck", "sh-cmt-32.0", &mstp_clks[MSTP014]),
b87cecef MD	229	CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]),
	230	CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]),
	231	CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]),
ee0c2eff KM	232
	233	CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP007]),
	234	CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP006]),
	235	CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP005]),
	236
b87cecef MD	237	CLKDEV_CON_ID("msiof0", &mstp_clks[MSTP002]),
b87cecef MD	238	CLKDEV_CON_ID("sbr0", &mstp_clks[MSTP001]),
54f7c116	239	CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP109]),
b87cecef MD	240	CLKDEV_CON_ID("icb0", &mstp_clks[MSTP227]),
	241	CLKDEV_CON_ID("meram0", &mstp_clks[MSTP226]),
	242	CLKDEV_CON_ID("dacy1", &mstp_clks[MSTP224]),
	243	CLKDEV_CON_ID("dacy0", &mstp_clks[MSTP223]),
	244	CLKDEV_CON_ID("tsif0", &mstp_clks[MSTP222]),
	245	CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]),
	246	CLKDEV_CON_ID("mmcif0", &mstp_clks[MSTP217]),
	247	CLKDEV_CON_ID("usbf0", &mstp_clks[MSTP211]),
	248	CLKDEV_CON_ID("veu1", &mstp_clks[MSTP207]),
	249	CLKDEV_CON_ID("vou0", &mstp_clks[MSTP205]),
	250	CLKDEV_CON_ID("beu0", &mstp_clks[MSTP204]),
	251	CLKDEV_CON_ID("ceu0", &mstp_clks[MSTP203]),
	252	CLKDEV_CON_ID("veu0", &mstp_clks[MSTP202]),
	253	CLKDEV_CON_ID("vpu0", &mstp_clks[MSTP201]),
	254	CLKDEV_CON_ID("lcdc0", &mstp_clks[MSTP200]),
098ec49b MD	255	};
098ec49b MD	256
4ed37394 MD	257	int __init arch_clk_init(void)
	258	{
	259	int k, ret = 0;
	260
	261	/* autodetect extal or dll configuration */
	262	if (__raw_readl(PLLCR) & 0x1000)
	263	pll_clk.parent = &dll_clk;
	264	else
	265	pll_clk.parent = &extal_clk;
	266
	267	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
	268	ret = clk_register(main_clks[k]);
	269
098ec49b MD	270	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
098ec49b MD	271
4ed37394 MD	272	if (!ret)
	273	ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
	274
	275	if (!ret)
098ec49b	276	ret = sh_clk_div6_register(div6_clks, DIV6_NR);
4ed37394 MD	277
4ed37394 MD	278	if (!ret)
ad3337cb	279	ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
4ed37394 MD	280
	281	return ret;
	282	}