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7dec62e9 PM |
1 | /* |
2 | * SH4-202 Setup | |
3 | * | |
4 | * Copyright (C) 2006 Paul Mundt | |
67d889bd | 5 | * Copyright (C) 2009 Magnus Damm |
7dec62e9 PM |
6 | * |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file "COPYING" in the main directory of this archive | |
9 | * for more details. | |
10 | */ | |
11 | #include <linux/platform_device.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/serial.h> | |
96de1a8f | 14 | #include <linux/serial_sci.h> |
5f8a29ba | 15 | #include <linux/sh_timer.h> |
67d889bd | 16 | #include <linux/io.h> |
7dec62e9 | 17 | |
cd5f1076 MD |
18 | static struct plat_sci_port scif0_platform_data = { |
19 | .mapbase = 0xffe80000, | |
20 | .flags = UPF_BOOT_AUTOCONF, | |
21 | .type = PORT_SCIF, | |
22 | .irqs = { 40, 41, 43, 42 }, | |
7dec62e9 PM |
23 | }; |
24 | ||
cd5f1076 | 25 | static struct platform_device scif0_device = { |
7dec62e9 | 26 | .name = "sh-sci", |
cd5f1076 | 27 | .id = 0, |
7dec62e9 | 28 | .dev = { |
cd5f1076 | 29 | .platform_data = &scif0_platform_data, |
7dec62e9 PM |
30 | }, |
31 | }; | |
32 | ||
5f8a29ba MD |
33 | static struct sh_timer_config tmu0_platform_data = { |
34 | .name = "TMU0", | |
35 | .channel_offset = 0x04, | |
36 | .timer_bit = 0, | |
af777ce4 | 37 | .clk = "peripheral_clk", |
5f8a29ba MD |
38 | .clockevent_rating = 200, |
39 | }; | |
40 | ||
41 | static struct resource tmu0_resources[] = { | |
42 | [0] = { | |
43 | .name = "TMU0", | |
44 | .start = 0xffd80008, | |
45 | .end = 0xffd80013, | |
46 | .flags = IORESOURCE_MEM, | |
47 | }, | |
48 | [1] = { | |
49 | .start = 16, | |
50 | .flags = IORESOURCE_IRQ, | |
51 | }, | |
52 | }; | |
53 | ||
54 | static struct platform_device tmu0_device = { | |
55 | .name = "sh_tmu", | |
56 | .id = 0, | |
57 | .dev = { | |
58 | .platform_data = &tmu0_platform_data, | |
59 | }, | |
60 | .resource = tmu0_resources, | |
61 | .num_resources = ARRAY_SIZE(tmu0_resources), | |
62 | }; | |
63 | ||
64 | static struct sh_timer_config tmu1_platform_data = { | |
65 | .name = "TMU1", | |
66 | .channel_offset = 0x10, | |
67 | .timer_bit = 1, | |
af777ce4 | 68 | .clk = "peripheral_clk", |
5f8a29ba MD |
69 | .clocksource_rating = 200, |
70 | }; | |
71 | ||
72 | static struct resource tmu1_resources[] = { | |
73 | [0] = { | |
74 | .name = "TMU1", | |
75 | .start = 0xffd80014, | |
76 | .end = 0xffd8001f, | |
77 | .flags = IORESOURCE_MEM, | |
78 | }, | |
79 | [1] = { | |
80 | .start = 17, | |
81 | .flags = IORESOURCE_IRQ, | |
82 | }, | |
83 | }; | |
84 | ||
85 | static struct platform_device tmu1_device = { | |
86 | .name = "sh_tmu", | |
87 | .id = 1, | |
88 | .dev = { | |
89 | .platform_data = &tmu1_platform_data, | |
90 | }, | |
91 | .resource = tmu1_resources, | |
92 | .num_resources = ARRAY_SIZE(tmu1_resources), | |
93 | }; | |
94 | ||
95 | static struct sh_timer_config tmu2_platform_data = { | |
96 | .name = "TMU2", | |
97 | .channel_offset = 0x1c, | |
98 | .timer_bit = 2, | |
af777ce4 | 99 | .clk = "peripheral_clk", |
5f8a29ba MD |
100 | }; |
101 | ||
102 | static struct resource tmu2_resources[] = { | |
103 | [0] = { | |
104 | .name = "TMU2", | |
105 | .start = 0xffd80020, | |
106 | .end = 0xffd8002f, | |
107 | .flags = IORESOURCE_MEM, | |
108 | }, | |
109 | [1] = { | |
110 | .start = 18, | |
111 | .flags = IORESOURCE_IRQ, | |
112 | }, | |
113 | }; | |
114 | ||
115 | static struct platform_device tmu2_device = { | |
116 | .name = "sh_tmu", | |
117 | .id = 2, | |
118 | .dev = { | |
119 | .platform_data = &tmu2_platform_data, | |
120 | }, | |
121 | .resource = tmu2_resources, | |
122 | .num_resources = ARRAY_SIZE(tmu2_resources), | |
123 | }; | |
124 | ||
7dec62e9 | 125 | static struct platform_device *sh4202_devices[] __initdata = { |
cd5f1076 | 126 | &scif0_device, |
5f8a29ba MD |
127 | &tmu0_device, |
128 | &tmu1_device, | |
129 | &tmu2_device, | |
7dec62e9 PM |
130 | }; |
131 | ||
132 | static int __init sh4202_devices_setup(void) | |
133 | { | |
134 | return platform_add_devices(sh4202_devices, | |
135 | ARRAY_SIZE(sh4202_devices)); | |
136 | } | |
ba9a6337 | 137 | arch_initcall(sh4202_devices_setup); |
b58d134c | 138 | |
5f8a29ba | 139 | static struct platform_device *sh4202_early_devices[] __initdata = { |
cd5f1076 | 140 | &scif0_device, |
5f8a29ba MD |
141 | &tmu0_device, |
142 | &tmu1_device, | |
143 | &tmu2_device, | |
144 | }; | |
145 | ||
146 | void __init plat_early_device_setup(void) | |
147 | { | |
148 | early_platform_add_devices(sh4202_early_devices, | |
149 | ARRAY_SIZE(sh4202_early_devices)); | |
150 | } | |
151 | ||
67d889bd MD |
152 | enum { |
153 | UNUSED = 0, | |
154 | ||
155 | /* interrupt sources */ | |
156 | IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */ | |
157 | HUDI, TMU0, TMU1, TMU2, RTC, SCIF, WDT, | |
158 | }; | |
159 | ||
160 | static struct intc_vect vectors[] __initdata = { | |
161 | INTC_VECT(HUDI, 0x600), | |
162 | INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), | |
163 | INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460), | |
164 | INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), | |
165 | INTC_VECT(RTC, 0x4c0), | |
166 | INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720), | |
167 | INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760), | |
168 | INTC_VECT(WDT, 0x560), | |
169 | }; | |
170 | ||
171 | static struct intc_prio_reg prio_registers[] __initdata = { | |
172 | { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, | |
173 | { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, 0, 0, 0 } }, | |
174 | { 0xffd0000c, 0, 16, 4, /* IPRC */ { 0, 0, SCIF, HUDI } }, | |
175 | { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, | |
176 | }; | |
177 | ||
178 | static DECLARE_INTC_DESC(intc_desc, "sh4-202", vectors, NULL, | |
179 | NULL, prio_registers, NULL); | |
180 | ||
181 | static struct intc_vect vectors_irlm[] __initdata = { | |
182 | INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), | |
183 | INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), | |
184 | }; | |
185 | ||
186 | static DECLARE_INTC_DESC(intc_desc_irlm, "sh4-202_irlm", vectors_irlm, NULL, | |
187 | NULL, prio_registers, NULL); | |
188 | ||
b58d134c MD |
189 | void __init plat_irq_setup(void) |
190 | { | |
67d889bd MD |
191 | register_intc_controller(&intc_desc); |
192 | } | |
193 | ||
194 | #define INTC_ICR 0xffd00000UL | |
195 | #define INTC_ICR_IRLM (1<<7) | |
196 | ||
197 | void __init plat_irq_setup_pins(int mode) | |
198 | { | |
199 | switch (mode) { | |
200 | case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */ | |
201 | ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); | |
202 | register_intc_controller(&intc_desc_irlm); | |
203 | break; | |
204 | default: | |
205 | BUG(); | |
206 | } | |
b58d134c | 207 | } |