Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * arch/sh/kernel/cpu/sh4/probe.c | |
3 | * | |
4 | * CPU Subtype Probing for SH-4. | |
5 | * | |
26fad19d | 6 | * Copyright (C) 2001 - 2007 Paul Mundt |
1da177e4 LT |
7 | * Copyright (C) 2003 Richard Curnow |
8 | * | |
9 | * This file is subject to the terms and conditions of the GNU General Public | |
10 | * License. See the file "COPYING" in the main directory of this archive | |
11 | * for more details. | |
12 | */ | |
1da177e4 | 13 | #include <linux/init.h> |
11c19656 | 14 | #include <linux/io.h> |
1da177e4 LT |
15 | #include <asm/processor.h> |
16 | #include <asm/cache.h> | |
1da177e4 LT |
17 | |
18 | int __init detect_cpu_and_cache_system(void) | |
19 | { | |
20 | unsigned long pvr, prr, cvr; | |
21 | unsigned long size; | |
22 | ||
23 | static unsigned long sizes[16] = { | |
24 | [1] = (1 << 12), | |
25 | [2] = (1 << 13), | |
26 | [4] = (1 << 14), | |
27 | [8] = (1 << 15), | |
28 | [9] = (1 << 16) | |
29 | }; | |
30 | ||
72c35543 | 31 | pvr = (ctrl_inl(CCN_PVR) >> 8) & 0xffffff; |
1da177e4 LT |
32 | prr = (ctrl_inl(CCN_PRR) >> 4) & 0xff; |
33 | cvr = (ctrl_inl(CCN_CVR)); | |
34 | ||
35 | /* | |
36 | * Setup some sane SH-4 defaults for the icache | |
37 | */ | |
cb7af21f PM |
38 | boot_cpu_data.icache.way_incr = (1 << 13); |
39 | boot_cpu_data.icache.entry_shift = 5; | |
40 | boot_cpu_data.icache.sets = 256; | |
41 | boot_cpu_data.icache.ways = 1; | |
42 | boot_cpu_data.icache.linesz = L1_CACHE_BYTES; | |
1da177e4 LT |
43 | |
44 | /* | |
45 | * And again for the dcache .. | |
46 | */ | |
cb7af21f PM |
47 | boot_cpu_data.dcache.way_incr = (1 << 14); |
48 | boot_cpu_data.dcache.entry_shift = 5; | |
49 | boot_cpu_data.dcache.sets = 512; | |
50 | boot_cpu_data.dcache.ways = 1; | |
51 | boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; | |
1da177e4 | 52 | |
72c35543 | 53 | /* |
26fad19d | 54 | * Setup some generic flags we can probe on SH-4A parts |
72c35543 PM |
55 | */ |
56 | if (((pvr >> 16) & 0xff) == 0x10) { | |
72c35543 | 57 | if ((cvr & 0x10000000) == 0) |
cb7af21f | 58 | boot_cpu_data.flags |= CPU_HAS_DSP; |
72c35543 | 59 | |
cb7af21f | 60 | boot_cpu_data.flags |= CPU_HAS_LLSC; |
72c35543 PM |
61 | } |
62 | ||
63 | /* FPU detection works for everyone */ | |
64 | if ((cvr & 0x20000000) == 1) | |
cb7af21f | 65 | boot_cpu_data.flags |= CPU_HAS_FPU; |
72c35543 PM |
66 | |
67 | /* Mask off the upper chip ID */ | |
68 | pvr &= 0xffff; | |
69 | ||
1da177e4 LT |
70 | /* |
71 | * Probe the underlying processor version/revision and | |
72 | * adjust cpu_data setup accordingly. | |
73 | */ | |
74 | switch (pvr) { | |
75 | case 0x205: | |
cb7af21f PM |
76 | boot_cpu_data.type = CPU_SH7750; |
77 | boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU | | |
9b3a53ab | 78 | CPU_HAS_PERF_COUNTER; |
1da177e4 LT |
79 | break; |
80 | case 0x206: | |
cb7af21f PM |
81 | boot_cpu_data.type = CPU_SH7750S; |
82 | boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU | | |
9b3a53ab | 83 | CPU_HAS_PERF_COUNTER; |
1da177e4 LT |
84 | break; |
85 | case 0x1100: | |
cb7af21f PM |
86 | boot_cpu_data.type = CPU_SH7751; |
87 | boot_cpu_data.flags |= CPU_HAS_FPU; | |
1da177e4 | 88 | break; |
5b19c908 PM |
89 | case 0x2001: |
90 | case 0x2004: | |
cb7af21f PM |
91 | boot_cpu_data.type = CPU_SH7770; |
92 | boot_cpu_data.icache.ways = 4; | |
93 | boot_cpu_data.dcache.ways = 4; | |
749cf486 | 94 | |
cb7af21f | 95 | boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_LLSC; |
5b19c908 PM |
96 | break; |
97 | case 0x2006: | |
98 | case 0x200A: | |
99 | if (prr == 0x61) | |
cb7af21f | 100 | boot_cpu_data.type = CPU_SH7781; |
7d740a06 YS |
101 | else if (prr == 0xa1) |
102 | boot_cpu_data.type = CPU_SH7763; | |
5b19c908 | 103 | else |
cb7af21f | 104 | boot_cpu_data.type = CPU_SH7780; |
749cf486 | 105 | |
cb7af21f PM |
106 | boot_cpu_data.icache.ways = 4; |
107 | boot_cpu_data.dcache.ways = 4; | |
749cf486 | 108 | |
cb7af21f | 109 | boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER | |
315bb968 | 110 | CPU_HAS_LLSC; |
5b19c908 | 111 | break; |
e5723e0e PM |
112 | case 0x3000: |
113 | case 0x3003: | |
41504c39 | 114 | case 0x3009: |
cb7af21f PM |
115 | boot_cpu_data.type = CPU_SH7343; |
116 | boot_cpu_data.icache.ways = 4; | |
117 | boot_cpu_data.dcache.ways = 4; | |
118 | boot_cpu_data.flags |= CPU_HAS_LLSC; | |
e5723e0e | 119 | break; |
32351a28 PM |
120 | case 0x3004: |
121 | case 0x3007: | |
cb7af21f PM |
122 | boot_cpu_data.type = CPU_SH7785; |
123 | boot_cpu_data.icache.ways = 4; | |
124 | boot_cpu_data.dcache.ways = 4; | |
125 | boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER | | |
32351a28 PM |
126 | CPU_HAS_LLSC; |
127 | break; | |
41504c39 | 128 | case 0x3008: |
178dd0cd PM |
129 | boot_cpu_data.icache.ways = 4; |
130 | boot_cpu_data.dcache.ways = 4; | |
131 | boot_cpu_data.flags |= CPU_HAS_LLSC; | |
132 | ||
133 | switch (prr) { | |
134 | case 0x50: | |
135 | boot_cpu_data.type = CPU_SH7723; | |
136 | boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_L2_CACHE; | |
137 | break; | |
138 | case 0x70: | |
9109a30e | 139 | boot_cpu_data.type = CPU_SH7366; |
178dd0cd PM |
140 | break; |
141 | case 0xa0: | |
142 | case 0xa1: | |
143 | boot_cpu_data.type = CPU_SH7722; | |
144 | break; | |
9109a30e | 145 | } |
41504c39 | 146 | break; |
2b1bd1ac PM |
147 | case 0x4000: /* 1st cut */ |
148 | case 0x4001: /* 2nd cut */ | |
cb7af21f PM |
149 | boot_cpu_data.type = CPU_SHX3; |
150 | boot_cpu_data.icache.ways = 4; | |
151 | boot_cpu_data.dcache.ways = 4; | |
152 | boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER | | |
2b1bd1ac PM |
153 | CPU_HAS_LLSC; |
154 | break; | |
1da177e4 | 155 | case 0x700: |
cb7af21f PM |
156 | boot_cpu_data.type = CPU_SH4_501; |
157 | boot_cpu_data.icache.ways = 2; | |
158 | boot_cpu_data.dcache.ways = 2; | |
1da177e4 LT |
159 | break; |
160 | case 0x600: | |
cb7af21f PM |
161 | boot_cpu_data.type = CPU_SH4_202; |
162 | boot_cpu_data.icache.ways = 2; | |
163 | boot_cpu_data.dcache.ways = 2; | |
164 | boot_cpu_data.flags |= CPU_HAS_FPU; | |
1da177e4 LT |
165 | break; |
166 | case 0x500 ... 0x501: | |
167 | switch (prr) { | |
73388cc7 | 168 | case 0x10: |
cb7af21f | 169 | boot_cpu_data.type = CPU_SH7750R; |
73388cc7 PM |
170 | break; |
171 | case 0x11: | |
cb7af21f | 172 | boot_cpu_data.type = CPU_SH7751R; |
73388cc7 PM |
173 | break; |
174 | case 0x50 ... 0x5f: | |
cb7af21f | 175 | boot_cpu_data.type = CPU_SH7760; |
73388cc7 | 176 | break; |
1da177e4 LT |
177 | } |
178 | ||
cb7af21f PM |
179 | boot_cpu_data.icache.ways = 2; |
180 | boot_cpu_data.dcache.ways = 2; | |
1da177e4 | 181 | |
cb7af21f | 182 | boot_cpu_data.flags |= CPU_HAS_FPU; |
749cf486 | 183 | |
1da177e4 LT |
184 | break; |
185 | default: | |
cb7af21f | 186 | boot_cpu_data.type = CPU_SH_NONE; |
1da177e4 LT |
187 | break; |
188 | } | |
189 | ||
b638d0b9 | 190 | #ifdef CONFIG_SH_DIRECT_MAPPED |
cb7af21f PM |
191 | boot_cpu_data.icache.ways = 1; |
192 | boot_cpu_data.dcache.ways = 1; | |
11c19656 PM |
193 | #endif |
194 | ||
195 | #ifdef CONFIG_CPU_HAS_PTEA | |
cb7af21f | 196 | boot_cpu_data.flags |= CPU_HAS_PTEA; |
b638d0b9 RC |
197 | #endif |
198 | ||
1da177e4 LT |
199 | /* |
200 | * On anything that's not a direct-mapped cache, look to the CVR | |
201 | * for I/D-cache specifics. | |
202 | */ | |
cb7af21f | 203 | if (boot_cpu_data.icache.ways > 1) { |
1da177e4 | 204 | size = sizes[(cvr >> 20) & 0xf]; |
cb7af21f PM |
205 | boot_cpu_data.icache.way_incr = (size >> 1); |
206 | boot_cpu_data.icache.sets = (size >> 6); | |
d15f4560 | 207 | |
1da177e4 LT |
208 | } |
209 | ||
d15f4560 | 210 | /* And the rest of the D-cache */ |
cb7af21f | 211 | if (boot_cpu_data.dcache.ways > 1) { |
1da177e4 | 212 | size = sizes[(cvr >> 16) & 0xf]; |
cb7af21f PM |
213 | boot_cpu_data.dcache.way_incr = (size >> 1); |
214 | boot_cpu_data.dcache.sets = (size >> 6); | |
1da177e4 LT |
215 | } |
216 | ||
72c35543 PM |
217 | /* |
218 | * Setup the L2 cache desc | |
219 | * | |
220 | * SH-4A's have an optional PIPT L2. | |
221 | */ | |
cb7af21f | 222 | if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) { |
72c35543 PM |
223 | /* |
224 | * Size calculation is much more sensible | |
225 | * than it is for the L1. | |
226 | * | |
227 | * Sizes are 128KB, 258KB, 512KB, and 1MB. | |
228 | */ | |
229 | size = (cvr & 0xf) << 17; | |
230 | ||
231 | BUG_ON(!size); | |
232 | ||
cb7af21f PM |
233 | boot_cpu_data.scache.way_incr = (1 << 16); |
234 | boot_cpu_data.scache.entry_shift = 5; | |
235 | boot_cpu_data.scache.ways = 4; | |
236 | boot_cpu_data.scache.linesz = L1_CACHE_BYTES; | |
11c19656 | 237 | |
cb7af21f PM |
238 | boot_cpu_data.scache.entry_mask = |
239 | (boot_cpu_data.scache.way_incr - | |
240 | boot_cpu_data.scache.linesz); | |
11c19656 | 241 | |
cb7af21f PM |
242 | boot_cpu_data.scache.sets = size / |
243 | (boot_cpu_data.scache.linesz * | |
244 | boot_cpu_data.scache.ways); | |
11c19656 | 245 | |
cb7af21f PM |
246 | boot_cpu_data.scache.way_size = |
247 | (boot_cpu_data.scache.sets * | |
248 | boot_cpu_data.scache.linesz); | |
72c35543 PM |
249 | } |
250 | ||
1da177e4 LT |
251 | return 0; |
252 | } |