[linux-block.git] / arch / sh / kernel / cpu / irq / intc.c

/*
 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
 *
 * Copyright (C) 2007 Magnus Damm
 *
 * Based on intc2.c and ipr.c
 *
 * Copyright (C) 1999  Niibe Yutaka & Takeshi Yaegashi
 * Copyright (C) 2000  Kazumoto Kojima
 * Copyright (C) 2001  David J. Mckay (david.mckay@st.com)
 * Copyright (C) 2003  Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
 * Copyright (C) 2005, 2006  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/bootmem.h>

#define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
	((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
	 ((addr_e) << 16) | ((addr_d << 24)))

#define _INTC_SHIFT(h) (h & 0x1f)
#define _INTC_WIDTH(h) ((h >> 5) & 0xf)
#define _INTC_FN(h) ((h >> 9) & 0xf)
#define _INTC_MODE(h) ((h >> 13) & 0x7)
#define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
#define _INTC_ADDR_D(h) ((h >> 24) & 0xff)

struct intc_handle_int {
	unsigned int irq;
	unsigned long handle;
};

struct intc_desc_int {
	unsigned long *reg;
#ifdef CONFIG_SMP
	unsigned long *smp;
#endif
	unsigned int nr_reg;
	struct intc_handle_int *prio;
	unsigned int nr_prio;
	struct intc_handle_int *sense;
	unsigned int nr_sense;
	struct irq_chip chip;
};

#ifdef CONFIG_SMP
#define IS_SMP(x) x.smp
#define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
#define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
#else
#define IS_SMP(x) 0
#define INTC_REG(d, x, c) (d->reg[(x)])
#define SMP_NR(d, x) 1
#endif

static unsigned int intc_prio_level[NR_IRQS]; /* for now */

static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
{
	struct irq_chip *chip = get_irq_chip(irq);
	return (void *)((char *)chip - offsetof(struct intc_desc_int, chip));
}

static inline unsigned int set_field(unsigned int value,
				     unsigned int field_value,
				     unsigned int handle)
{
	unsigned int width = _INTC_WIDTH(handle);
	unsigned int shift = _INTC_SHIFT(handle);

	value &= ~(((1 << width) - 1) << shift);
	value |= field_value << shift;
	return value;
}

static void write_8(unsigned long addr, unsigned long h, unsigned long data)
{
	ctrl_outb(set_field(0, data, h), addr);
}

static void write_16(unsigned long addr, unsigned long h, unsigned long data)
{
	ctrl_outw(set_field(0, data, h), addr);
}

static void write_32(unsigned long addr, unsigned long h, unsigned long data)
{
	ctrl_outl(set_field(0, data, h), addr);
}

static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
{
	ctrl_outb(set_field(ctrl_inb(addr), data, h), addr);
}

static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
{
	ctrl_outw(set_field(ctrl_inw(addr), data, h), addr);
}

static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
{
	ctrl_outl(set_field(ctrl_inl(addr), data, h), addr);
}

enum {	REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };

static void (*intc_reg_fns[])(unsigned long addr,
			      unsigned long h,
			      unsigned long data) = {
	[REG_FN_WRITE_BASE + 0] = write_8,
	[REG_FN_WRITE_BASE + 1] = write_16,
	[REG_FN_WRITE_BASE + 3] = write_32,
	[REG_FN_MODIFY_BASE + 0] = modify_8,
	[REG_FN_MODIFY_BASE + 1] = modify_16,
	[REG_FN_MODIFY_BASE + 3] = modify_32,
};

enum {	MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
	MODE_MASK_REG,       /* Bit(s) set -> interrupt disabled */
	MODE_DUAL_REG,       /* Two registers, set bit to enable / disable */
	MODE_PRIO_REG,       /* Priority value written to enable interrupt */
	MODE_PCLR_REG,       /* Above plus all bits set to disable interrupt */
};

static void intc_mode_field(unsigned long addr,
			    unsigned long handle,
			    void (*fn)(unsigned long,
				       unsigned long,
				       unsigned long),
			    unsigned int irq)
{
	fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
}

static void intc_mode_zero(unsigned long addr,
			   unsigned long handle,
			   void (*fn)(unsigned long,
				       unsigned long,
				       unsigned long),
			   unsigned int irq)
{
	fn(addr, handle, 0);
}

static void intc_mode_prio(unsigned long addr,
			   unsigned long handle,
			   void (*fn)(unsigned long,
				       unsigned long,
				       unsigned long),
			   unsigned int irq)
{
	fn(addr, handle, intc_prio_level[irq]);
}

static void (*intc_enable_fns[])(unsigned long addr,
				 unsigned long handle,
				 void (*fn)(unsigned long,
					    unsigned long,
					    unsigned long),
				 unsigned int irq) = {
	[MODE_ENABLE_REG] = intc_mode_field,
	[MODE_MASK_REG] = intc_mode_zero,
	[MODE_DUAL_REG] = intc_mode_field,
	[MODE_PRIO_REG] = intc_mode_prio,
	[MODE_PCLR_REG] = intc_mode_prio,
};

static void (*intc_disable_fns[])(unsigned long addr,
				  unsigned long handle,
				  void (*fn)(unsigned long,
					     unsigned long,
					     unsigned long),
				  unsigned int irq) = {
	[MODE_ENABLE_REG] = intc_mode_zero,
	[MODE_MASK_REG] = intc_mode_field,
	[MODE_DUAL_REG] = intc_mode_field,
	[MODE_PRIO_REG] = intc_mode_zero,
	[MODE_PCLR_REG] = intc_mode_field,
};

static inline void _intc_enable(unsigned int irq, unsigned long handle)
{
	struct intc_desc_int *d = get_intc_desc(irq);
	unsigned long addr;
	unsigned int cpu;

	for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
		addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
		intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\
						    [_INTC_FN(handle)], irq);
	}
}

static void intc_enable(unsigned int irq)
{
	_intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
}

static void intc_disable(unsigned int irq)
{
	struct intc_desc_int *d = get_intc_desc(irq);
	unsigned long handle = (unsigned long) get_irq_chip_data(irq);
	unsigned long addr;
	unsigned int cpu;

	for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
		addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
		intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\
						     [_INTC_FN(handle)], irq);
	}
}

static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
					     unsigned int nr_hp,
					     unsigned int irq)
{
	int i;

	/* this doesn't scale well, but...
	 *
	 * this function should only be used for cerain uncommon
	 * operations such as intc_set_priority() and intc_set_sense()
	 * and in those rare cases performance doesn't matter that much.
	 * keeping the memory footprint low is more important.
	 *
	 * one rather simple way to speed this up and still keep the
	 * memory footprint down is to make sure the array is sorted
	 * and then perform a bisect to lookup the irq.
	 */

	for (i = 0; i < nr_hp; i++) {
		if ((hp + i)->irq != irq)
			continue;

		return hp + i;
	}

	return NULL;
}

int intc_set_priority(unsigned int irq, unsigned int prio)
{
	struct intc_desc_int *d = get_intc_desc(irq);
	struct intc_handle_int *ihp;

	if (!intc_prio_level[irq] || prio <= 1)
		return -EINVAL;

	ihp = intc_find_irq(d->prio, d->nr_prio, irq);
	if (ihp) {
		if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
			return -EINVAL;

		intc_prio_level[irq] = prio;

		/*
		 * only set secondary masking method directly
		 * primary masking method is using intc_prio_level[irq]
		 * priority level will be set during next enable()
		 */

		if (_INTC_FN(ihp->handle) != REG_FN_ERR)
			_intc_enable(irq, ihp->handle);
	}
	return 0;
}

#define VALID(x) (x | 0x80)

static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
	[IRQ_TYPE_EDGE_FALLING] = VALID(0),
	[IRQ_TYPE_EDGE_RISING] = VALID(1),
	[IRQ_TYPE_LEVEL_LOW] = VALID(2),
	[IRQ_TYPE_LEVEL_HIGH] = VALID(3),
};

static int intc_set_sense(unsigned int irq, unsigned int type)
{
	struct intc_desc_int *d = get_intc_desc(irq);
	unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
	struct intc_handle_int *ihp;
	unsigned long addr;

	if (!value)
		return -EINVAL;

	ihp = intc_find_irq(d->sense, d->nr_sense, irq);
	if (ihp) {
		addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
		intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
	}
	return 0;
}

static unsigned int __init intc_get_reg(struct intc_desc_int *d,
				 unsigned long address)
{
	unsigned int k;

	for (k = 0; k < d->nr_reg; k++) {
		if (d->reg[k] == address)
			return k;
	}

	BUG();
	return 0;
}

static intc_enum __init intc_grp_id(struct intc_desc *desc,
				    intc_enum enum_id)
{
	struct intc_group *g = desc->groups;
	unsigned int i, j;

	for (i = 0; g && enum_id && i < desc->nr_groups; i++) {
		g = desc->groups + i;

		for (j = 0; g->enum_ids[j]; j++) {
			if (g->enum_ids[j] != enum_id)
				continue;

			return g->enum_id;
		}
	}

	return 0;
}

static unsigned int __init intc_prio_value(struct intc_desc *desc,
					   intc_enum enum_id, int do_grps)
{
	struct intc_prio *p = desc->priorities;
	unsigned int i;

	for (i = 0; p && enum_id && i < desc->nr_priorities; i++) {
		p = desc->priorities + i;

		if (p->enum_id != enum_id)
			continue;

		return p->priority;
	}

	if (do_grps)
		return intc_prio_value(desc, intc_grp_id(desc, enum_id), 0);

	/* default to the lowest priority possible if no priority is set
	 * - this needs to be at least 2 for 5-bit priorities on 7780
	 */

	return 2;
}

static unsigned int __init intc_mask_data(struct intc_desc *desc,
					  struct intc_desc_int *d,
					  intc_enum enum_id, int do_grps)
{
	struct intc_mask_reg *mr = desc->mask_regs;
	unsigned int i, j, fn, mode;
	unsigned long reg_e, reg_d;

	for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
		mr = desc->mask_regs + i;

		for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
			if (mr->enum_ids[j] != enum_id)
				continue;

			if (mr->set_reg && mr->clr_reg) {
				fn = REG_FN_WRITE_BASE;
				mode = MODE_DUAL_REG;
				reg_e = mr->clr_reg;
				reg_d = mr->set_reg;
			} else {
				fn = REG_FN_MODIFY_BASE;
				if (mr->set_reg) {
					mode = MODE_ENABLE_REG;
					reg_e = mr->set_reg;
					reg_d = mr->set_reg;
				} else {
					mode = MODE_MASK_REG;
					reg_e = mr->clr_reg;
					reg_d = mr->clr_reg;
				}
			}

			fn += (mr->reg_width >> 3) - 1;
			return _INTC_MK(fn, mode,
					intc_get_reg(d, reg_e),
					intc_get_reg(d, reg_d),
					1,
					(mr->reg_width - 1) - j);
		}
	}

	if (do_grps)
		return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);

	return 0;
}

static unsigned int __init intc_prio_data(struct intc_desc *desc,
					  struct intc_desc_int *d,
					  intc_enum enum_id, int do_grps)
{
	struct intc_prio_reg *pr = desc->prio_regs;
	unsigned int i, j, fn, mode, bit;
	unsigned long reg_e, reg_d;

	for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
		pr = desc->prio_regs + i;

		for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
			if (pr->enum_ids[j] != enum_id)
				continue;

			if (pr->set_reg && pr->clr_reg) {
				fn = REG_FN_WRITE_BASE;
				mode = MODE_PCLR_REG;
				reg_e = pr->set_reg;
				reg_d = pr->clr_reg;
			} else {
				fn = REG_FN_MODIFY_BASE;
				mode = MODE_PRIO_REG;
				if (!pr->set_reg)
					BUG();
				reg_e = pr->set_reg;
				reg_d = pr->set_reg;
			}

			fn += (pr->reg_width >> 3) - 1;
			bit = pr->reg_width - ((j + 1) * pr->field_width);

			BUG_ON(bit < 0);

			return _INTC_MK(fn, mode,
					intc_get_reg(d, reg_e),
					intc_get_reg(d, reg_d),
					pr->field_width, bit);
		}
	}

	if (do_grps)
		return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);

	return 0;
}

static unsigned int __init intc_sense_data(struct intc_desc *desc,
					   struct intc_desc_int *d,
					   intc_enum enum_id)
{
	struct intc_sense_reg *sr = desc->sense_regs;
	unsigned int i, j, fn, bit;

	for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) {
		sr = desc->sense_regs + i;

		for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
			if (sr->enum_ids[j] != enum_id)
				continue;

			fn = REG_FN_MODIFY_BASE;
			fn += (sr->reg_width >> 3) - 1;
			bit = sr->reg_width - ((j + 1) * sr->field_width);

			BUG_ON(bit < 0);

			return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
					0, sr->field_width, bit);
		}
	}

	return 0;
}

static void __init intc_register_irq(struct intc_desc *desc,
				     struct intc_desc_int *d,
				     intc_enum enum_id,
				     unsigned int irq)
{
	struct intc_handle_int *hp;
	unsigned int data[2], primary;

	/* Prefer single interrupt source bitmap over other combinations:
	 * 1. bitmap, single interrupt source
	 * 2. priority, single interrupt source
	 * 3. bitmap, multiple interrupt sources (groups)
	 * 4. priority, multiple interrupt sources (groups)
	 */

	data[0] = intc_mask_data(desc, d, enum_id, 0);
	data[1] = intc_prio_data(desc, d, enum_id, 0);

	primary = 0;
	if (!data[0] && data[1])
		primary = 1;

	data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
	data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);

	if (!data[primary])
		primary ^= 1;

	BUG_ON(!data[primary]); /* must have primary masking method */

	disable_irq_nosync(irq);
	set_irq_chip_and_handler_name(irq, &d->chip,
				      handle_level_irq, "level");
	set_irq_chip_data(irq, (void *)data[primary]);

	/* record the desired priority level */
	intc_prio_level[irq] = intc_prio_value(desc, enum_id, 1);

	/* enable secondary masking method if present */
	if (data[!primary])
		_intc_enable(irq, data[!primary]);

	/* add irq to d->prio list if priority is available */
	if (data[1]) {
		hp = d->prio + d->nr_prio;
		hp->irq = irq;
		hp->handle = data[1];

		if (primary) {
			/*
			 * only secondary priority should access registers, so
			 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
			 */

			hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
			hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
		}
		d->nr_prio++;
	}

	/* add irq to d->sense list if sense is available */
	data[0] = intc_sense_data(desc, d, enum_id);
	if (data[0]) {
		(d->sense + d->nr_sense)->irq = irq;
		(d->sense + d->nr_sense)->handle = data[0];
		d->nr_sense++;
	}

	/* irq should be disabled by default */
	d->chip.mask(irq);
}

static unsigned int __init save_reg(struct intc_desc_int *d,
				    unsigned int cnt,
				    unsigned long value,
				    unsigned int smp)
{
	if (value) {
		d->reg[cnt] = value;
#ifdef CONFIG_SMP
		d->smp[cnt] = smp;
#endif
		return 1;
	}

	return 0;
}


void __init register_intc_controller(struct intc_desc *desc)
{
	unsigned int i, k, smp;
	struct intc_desc_int *d;

	d = alloc_bootmem(sizeof(*d));

	d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0;
	d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
	d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;

	d->reg = alloc_bootmem(d->nr_reg * sizeof(*d->reg));
#ifdef CONFIG_SMP
	d->smp = alloc_bootmem(d->nr_reg * sizeof(*d->smp));
#endif
	k = 0;

	if (desc->mask_regs) {
		for (i = 0; i < desc->nr_mask_regs; i++) {
			smp = IS_SMP(desc->mask_regs[i]);
			k += save_reg(d, k, desc->mask_regs[i].set_reg, smp);
			k += save_reg(d, k, desc->mask_regs[i].clr_reg, smp);
		}
	}

	if (desc->prio_regs) {
		d->prio = alloc_bootmem(desc->nr_vectors * sizeof(*d->prio));

		for (i = 0; i < desc->nr_prio_regs; i++) {
			smp = IS_SMP(desc->prio_regs[i]);
			k += save_reg(d, k, desc->prio_regs[i].set_reg, smp);
			k += save_reg(d, k, desc->prio_regs[i].clr_reg, smp);
		}
	}

	if (desc->sense_regs) {
		d->sense = alloc_bootmem(desc->nr_vectors * sizeof(*d->sense));

		for (i = 0; i < desc->nr_sense_regs; i++) {
			k += save_reg(d, k, desc->sense_regs[i].reg, 0);
		}
	}

	BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */

	d->chip.name = desc->name;
	d->chip.mask = intc_disable;
	d->chip.unmask = intc_enable;
	d->chip.mask_ack = intc_disable;
	d->chip.set_type = intc_set_sense;

	for (i = 0; i < desc->nr_vectors; i++) {
		struct intc_vect *vect = desc->vectors + i;

		intc_register_irq(desc, d, vect->enum_id, evt2irq(vect->vect));
	}
}
Commit	Line	Data
02ab3f70 MD	1	/*
	2	* Shared interrupt handling code for IPR and INTC2 types of IRQs.
	3	*
	4	* Copyright (C) 2007 Magnus Damm
	5	*
	6	* Based on intc2.c and ipr.c
	7	*
	8	* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
	9	* Copyright (C) 2000 Kazumoto Kojima
	10	* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
	11	* Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
	12	* Copyright (C) 2005, 2006 Paul Mundt
	13	*
	14	* This file is subject to the terms and conditions of the GNU General Public
	15	* License. See the file "COPYING" in the main directory of this archive
	16	* for more details.
	17	*/
	18	#include <linux/init.h>
	19	#include <linux/irq.h>
	20	#include <linux/module.h>
	21	#include <linux/io.h>
	22	#include <linux/interrupt.h>
73505b44 MD	23	#include <linux/bootmem.h>
	24
	25	#define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
	26	((shift) \| ((width) << 5) \| ((fn) << 9) \| ((mode) << 13) \| \
	27	((addr_e) << 16) \| ((addr_d << 24)))
	28
	29	#define _INTC_SHIFT(h) (h & 0x1f)
	30	#define _INTC_WIDTH(h) ((h >> 5) & 0xf)
	31	#define _INTC_FN(h) ((h >> 9) & 0xf)
	32	#define _INTC_MODE(h) ((h >> 13) & 0x7)
	33	#define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
	34	#define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
	35
	36	struct intc_handle_int {
	37	unsigned int irq;
	38	unsigned long handle;
	39	};
02ab3f70	40
73505b44 MD	41	struct intc_desc_int {
73505b44 MD	42	unsigned long *reg;
f18d533e MD	43	#ifdef CONFIG_SMP
	44	unsigned long *smp;
	45	#endif
73505b44 MD	46	unsigned int nr_reg;
	47	struct intc_handle_int *prio;
	48	unsigned int nr_prio;
	49	struct intc_handle_int *sense;
	50	unsigned int nr_sense;
	51	struct irq_chip chip;
	52	};
02ab3f70	53
f18d533e MD	54	#ifdef CONFIG_SMP
	55	#define IS_SMP(x) x.smp
	56	#define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
	57	#define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
	58	#else
	59	#define IS_SMP(x) 0
	60	#define INTC_REG(d, x, c) (d->reg[(x)])
	61	#define SMP_NR(d, x) 1
	62	#endif
	63
73505b44	64	static unsigned int intc_prio_level[NR_IRQS]; /* for now */
02ab3f70	65
73505b44	66	static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
02ab3f70 MD	67	{
02ab3f70 MD	68	struct irq_chip *chip = get_irq_chip(irq);
73505b44	69	return (void )((char )chip - offsetof(struct intc_desc_int, chip));
02ab3f70 MD	70	}
	71
	72	static inline unsigned int set_field(unsigned int value,
	73	unsigned int field_value,
73505b44	74	unsigned int handle)
02ab3f70	75	{
73505b44 MD	76	unsigned int width = _INTC_WIDTH(handle);
	77	unsigned int shift = _INTC_SHIFT(handle);
	78
02ab3f70 MD	79	value &= ~(((1 << width) - 1) << shift);
	80	value \|= field_value << shift;
	81	return value;
	82	}
	83
73505b44	84	static void write_8(unsigned long addr, unsigned long h, unsigned long data)
02ab3f70	85	{
73505b44	86	ctrl_outb(set_field(0, data, h), addr);
02ab3f70 MD	87	}
02ab3f70 MD	88
73505b44	89	static void write_16(unsigned long addr, unsigned long h, unsigned long data)
02ab3f70	90	{
73505b44	91	ctrl_outw(set_field(0, data, h), addr);
02ab3f70 MD	92	}
02ab3f70 MD	93
73505b44	94	static void write_32(unsigned long addr, unsigned long h, unsigned long data)
02ab3f70	95	{
73505b44	96	ctrl_outl(set_field(0, data, h), addr);
02ab3f70 MD	97	}
02ab3f70 MD	98
73505b44	99	static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
02ab3f70	100	{
73505b44	101	ctrl_outb(set_field(ctrl_inb(addr), data, h), addr);
02ab3f70 MD	102	}
02ab3f70 MD	103
73505b44	104	static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
02ab3f70	105	{
73505b44	106	ctrl_outw(set_field(ctrl_inw(addr), data, h), addr);
02ab3f70 MD	107	}
02ab3f70 MD	108
73505b44	109	static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
02ab3f70	110	{
73505b44	111	ctrl_outl(set_field(ctrl_inl(addr), data, h), addr);
02ab3f70 MD	112	}
02ab3f70 MD	113
73505b44 MD	114	enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
	115
	116	static void (*intc_reg_fns[])(unsigned long addr,
	117	unsigned long h,
	118	unsigned long data) = {
	119	[REG_FN_WRITE_BASE + 0] = write_8,
	120	[REG_FN_WRITE_BASE + 1] = write_16,
	121	[REG_FN_WRITE_BASE + 3] = write_32,
	122	[REG_FN_MODIFY_BASE + 0] = modify_8,
	123	[REG_FN_MODIFY_BASE + 1] = modify_16,
	124	[REG_FN_MODIFY_BASE + 3] = modify_32,
	125	};
02ab3f70	126
73505b44 MD	127	enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
	128	MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
	129	MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
	130	MODE_PRIO_REG, /* Priority value written to enable interrupt */
	131	MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
	132	};
02ab3f70	133
73505b44 MD	134	static void intc_mode_field(unsigned long addr,
	135	unsigned long handle,
	136	void (*fn)(unsigned long,
	137	unsigned long,
	138	unsigned long),
	139	unsigned int irq)
02ab3f70	140	{
73505b44	141	fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
02ab3f70 MD	142	}
02ab3f70 MD	143
73505b44 MD	144	static void intc_mode_zero(unsigned long addr,
	145	unsigned long handle,
	146	void (*fn)(unsigned long,
	147	unsigned long,
	148	unsigned long),
	149	unsigned int irq)
51da6426	150	{
73505b44	151	fn(addr, handle, 0);
51da6426 MD	152	}
51da6426 MD	153
73505b44 MD	154	static void intc_mode_prio(unsigned long addr,
	155	unsigned long handle,
	156	void (*fn)(unsigned long,
	157	unsigned long,
	158	unsigned long),
	159	unsigned int irq)
51da6426	160	{
73505b44	161	fn(addr, handle, intc_prio_level[irq]);
51da6426 MD	162	}
51da6426 MD	163
73505b44 MD	164	static void (*intc_enable_fns[])(unsigned long addr,
	165	unsigned long handle,
	166	void (*fn)(unsigned long,
	167	unsigned long,
	168	unsigned long),
	169	unsigned int irq) = {
	170	[MODE_ENABLE_REG] = intc_mode_field,
	171	[MODE_MASK_REG] = intc_mode_zero,
	172	[MODE_DUAL_REG] = intc_mode_field,
	173	[MODE_PRIO_REG] = intc_mode_prio,
	174	[MODE_PCLR_REG] = intc_mode_prio,
	175	};
51da6426	176
73505b44 MD	177	static void (*intc_disable_fns[])(unsigned long addr,
	178	unsigned long handle,
	179	void (*fn)(unsigned long,
	180	unsigned long,
	181	unsigned long),
	182	unsigned int irq) = {
	183	[MODE_ENABLE_REG] = intc_mode_zero,
	184	[MODE_MASK_REG] = intc_mode_field,
	185	[MODE_DUAL_REG] = intc_mode_field,
	186	[MODE_PRIO_REG] = intc_mode_zero,
	187	[MODE_PCLR_REG] = intc_mode_field,
	188	};
51da6426	189
73505b44	190	static inline void _intc_enable(unsigned int irq, unsigned long handle)
51da6426	191	{
73505b44	192	struct intc_desc_int *d = get_intc_desc(irq);
f18d533e MD	193	unsigned long addr;
f18d533e MD	194	unsigned int cpu;
51da6426	195
f18d533e MD	196	for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
	197	addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
	198	intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\
	199	[_INTC_FN(handle)], irq);
	200	}
51da6426 MD	201	}
51da6426 MD	202
02ab3f70 MD	203	static void intc_enable(unsigned int irq)
02ab3f70 MD	204	{
73505b44	205	_intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
02ab3f70 MD	206	}
	207
	208	static void intc_disable(unsigned int irq)
	209	{
f18d533e	210	struct intc_desc_int *d = get_intc_desc(irq);
73505b44	211	unsigned long handle = (unsigned long) get_irq_chip_data(irq);
f18d533e MD	212	unsigned long addr;
f18d533e MD	213	unsigned int cpu;
02ab3f70	214
f18d533e MD	215	for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
	216	addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
	217	intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\
	218	[_INTC_FN(handle)], irq);
	219	}
02ab3f70 MD	220	}
02ab3f70 MD	221
73505b44 MD	222	static struct intc_handle_int intc_find_irq(struct intc_handle_int hp,
	223	unsigned int nr_hp,
	224	unsigned int irq)
02ab3f70	225	{
73505b44 MD	226	int i;
73505b44 MD	227
3d37d94e MD	228	/* this doesn't scale well, but...
	229	*
	230	* this function should only be used for cerain uncommon
	231	* operations such as intc_set_priority() and intc_set_sense()
	232	* and in those rare cases performance doesn't matter that much.
	233	* keeping the memory footprint low is more important.
	234	*
	235	* one rather simple way to speed this up and still keep the
	236	* memory footprint down is to make sure the array is sorted
	237	* and then perform a bisect to lookup the irq.
	238	*/
	239
73505b44 MD	240	for (i = 0; i < nr_hp; i++) {
	241	if ((hp + i)->irq != irq)
	242	continue;
	243
	244	return hp + i;
	245	}
02ab3f70	246
73505b44	247	return NULL;
02ab3f70 MD	248	}
02ab3f70 MD	249
73505b44	250	int intc_set_priority(unsigned int irq, unsigned int prio)
02ab3f70	251	{
73505b44 MD	252	struct intc_desc_int *d = get_intc_desc(irq);
	253	struct intc_handle_int *ihp;
	254
	255	if (!intc_prio_level[irq] \|\| prio <= 1)
	256	return -EINVAL;
	257
	258	ihp = intc_find_irq(d->prio, d->nr_prio, irq);
	259	if (ihp) {
3d37d94e	260	if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
73505b44	261	return -EINVAL;
02ab3f70	262
73505b44 MD	263	intc_prio_level[irq] = prio;
	264
	265	/*
	266	* only set secondary masking method directly
	267	* primary masking method is using intc_prio_level[irq]
	268	* priority level will be set during next enable()
	269	*/
	270
3d37d94e	271	if (_INTC_FN(ihp->handle) != REG_FN_ERR)
73505b44 MD	272	_intc_enable(irq, ihp->handle);
	273	}
	274	return 0;
02ab3f70 MD	275	}
	276
	277	#define VALID(x) (x \| 0x80)
	278
	279	static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
	280	[IRQ_TYPE_EDGE_FALLING] = VALID(0),
	281	[IRQ_TYPE_EDGE_RISING] = VALID(1),
	282	[IRQ_TYPE_LEVEL_LOW] = VALID(2),
	283	[IRQ_TYPE_LEVEL_HIGH] = VALID(3),
	284	};
	285
	286	static int intc_set_sense(unsigned int irq, unsigned int type)
	287	{
73505b44	288	struct intc_desc_int *d = get_intc_desc(irq);
02ab3f70	289	unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
73505b44 MD	290	struct intc_handle_int *ihp;
73505b44 MD	291	unsigned long addr;
02ab3f70	292
73505b44	293	if (!value)
02ab3f70 MD	294	return -EINVAL;
02ab3f70 MD	295
73505b44 MD	296	ihp = intc_find_irq(d->sense, d->nr_sense, irq);
73505b44 MD	297	if (ihp) {
f18d533e	298	addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
73505b44	299	intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
02ab3f70	300	}
73505b44	301	return 0;
02ab3f70 MD	302	}
02ab3f70 MD	303
73505b44 MD	304	static unsigned int __init intc_get_reg(struct intc_desc_int *d,
73505b44 MD	305	unsigned long address)
02ab3f70	306	{
73505b44	307	unsigned int k;
02ab3f70	308
73505b44 MD	309	for (k = 0; k < d->nr_reg; k++) {
	310	if (d->reg[k] == address)
	311	return k;
51da6426 MD	312	}
	313
	314	BUG();
73505b44	315	return 0;
51da6426 MD	316	}
51da6426 MD	317
73505b44 MD	318	static intc_enum __init intc_grp_id(struct intc_desc *desc,
73505b44 MD	319	intc_enum enum_id)
680c4598 MD	320	{
	321	struct intc_group *g = desc->groups;
	322	unsigned int i, j;
	323
	324	for (i = 0; g && enum_id && i < desc->nr_groups; i++) {
	325	g = desc->groups + i;
	326
	327	for (j = 0; g->enum_ids[j]; j++) {
	328	if (g->enum_ids[j] != enum_id)
	329	continue;
	330
	331	return g->enum_id;
	332	}
	333	}
	334
	335	return 0;
	336	}
	337
02ab3f70	338	static unsigned int __init intc_prio_value(struct intc_desc *desc,
680c4598	339	intc_enum enum_id, int do_grps)
02ab3f70	340	{
680c4598	341	struct intc_prio *p = desc->priorities;
02ab3f70 MD	342	unsigned int i;
02ab3f70 MD	343
680c4598 MD	344	for (i = 0; p && enum_id && i < desc->nr_priorities; i++) {
680c4598 MD	345	p = desc->priorities + i;
02ab3f70 MD	346
	347	if (p->enum_id != enum_id)
	348	continue;
	349
	350	return p->priority;
	351	}
	352
680c4598 MD	353	if (do_grps)
	354	return intc_prio_value(desc, intc_grp_id(desc, enum_id), 0);
	355
	356	/* default to the lowest priority possible if no priority is set
	357	* - this needs to be at least 2 for 5-bit priorities on 7780
	358	*/
	359
	360	return 2;
02ab3f70 MD	361	}
	362
	363	static unsigned int __init intc_mask_data(struct intc_desc *desc,
73505b44	364	struct intc_desc_int *d,
680c4598	365	intc_enum enum_id, int do_grps)
02ab3f70	366	{
680c4598	367	struct intc_mask_reg *mr = desc->mask_regs;
73505b44 MD	368	unsigned int i, j, fn, mode;
73505b44 MD	369	unsigned long reg_e, reg_d;
02ab3f70	370
680c4598 MD	371	for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
680c4598 MD	372	mr = desc->mask_regs + i;
02ab3f70 MD	373
	374	for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
	375	if (mr->enum_ids[j] != enum_id)
	376	continue;
	377
73505b44 MD	378	if (mr->set_reg && mr->clr_reg) {
	379	fn = REG_FN_WRITE_BASE;
	380	mode = MODE_DUAL_REG;
	381	reg_e = mr->clr_reg;
	382	reg_d = mr->set_reg;
	383	} else {
	384	fn = REG_FN_MODIFY_BASE;
	385	if (mr->set_reg) {
	386	mode = MODE_ENABLE_REG;
	387	reg_e = mr->set_reg;
	388	reg_d = mr->set_reg;
	389	} else {
	390	mode = MODE_MASK_REG;
	391	reg_e = mr->clr_reg;
	392	reg_d = mr->clr_reg;
	393	}
51da6426 MD	394	}
51da6426 MD	395
73505b44 MD	396	fn += (mr->reg_width >> 3) - 1;
	397	return _INTC_MK(fn, mode,
	398	intc_get_reg(d, reg_e),
	399	intc_get_reg(d, reg_d),
	400	1,
	401	(mr->reg_width - 1) - j);
02ab3f70 MD	402	}
	403	}
	404
680c4598	405	if (do_grps)
73505b44	406	return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
680c4598	407
02ab3f70 MD	408	return 0;
	409	}
	410
	411	static unsigned int __init intc_prio_data(struct intc_desc *desc,
73505b44	412	struct intc_desc_int *d,
680c4598	413	intc_enum enum_id, int do_grps)
02ab3f70	414	{
680c4598	415	struct intc_prio_reg *pr = desc->prio_regs;
73505b44 MD	416	unsigned int i, j, fn, mode, bit;
73505b44 MD	417	unsigned long reg_e, reg_d;
02ab3f70	418
680c4598 MD	419	for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
680c4598 MD	420	pr = desc->prio_regs + i;
02ab3f70 MD	421
	422	for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
	423	if (pr->enum_ids[j] != enum_id)
	424	continue;
	425
73505b44 MD	426	if (pr->set_reg && pr->clr_reg) {
	427	fn = REG_FN_WRITE_BASE;
	428	mode = MODE_PCLR_REG;
	429	reg_e = pr->set_reg;
	430	reg_d = pr->clr_reg;
	431	} else {
	432	fn = REG_FN_MODIFY_BASE;
	433	mode = MODE_PRIO_REG;
	434	if (!pr->set_reg)
	435	BUG();
	436	reg_e = pr->set_reg;
	437	reg_d = pr->set_reg;
	438	}
02ab3f70	439
73505b44	440	fn += (pr->reg_width >> 3) - 1;
02ab3f70 MD	441	bit = pr->reg_width - ((j + 1) * pr->field_width);
	442
	443	BUG_ON(bit < 0);
	444
73505b44 MD	445	return _INTC_MK(fn, mode,
	446	intc_get_reg(d, reg_e),
	447	intc_get_reg(d, reg_d),
	448	pr->field_width, bit);
02ab3f70 MD	449	}
	450	}
	451
680c4598	452	if (do_grps)
73505b44 MD	453	return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
	454
	455	return 0;
	456	}
	457
	458	static unsigned int __init intc_sense_data(struct intc_desc *desc,
	459	struct intc_desc_int *d,
	460	intc_enum enum_id)
	461	{
	462	struct intc_sense_reg *sr = desc->sense_regs;
	463	unsigned int i, j, fn, bit;
	464
	465	for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) {
	466	sr = desc->sense_regs + i;
	467
	468	for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
	469	if (sr->enum_ids[j] != enum_id)
	470	continue;
	471
	472	fn = REG_FN_MODIFY_BASE;
	473	fn += (sr->reg_width >> 3) - 1;
	474	bit = sr->reg_width - ((j + 1) * sr->field_width);
	475
	476	BUG_ON(bit < 0);
	477
	478	return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
	479	0, sr->field_width, bit);
	480	}
	481	}
680c4598	482
02ab3f70 MD	483	return 0;
	484	}
	485
73505b44 MD	486	static void __init intc_register_irq(struct intc_desc *desc,
	487	struct intc_desc_int *d,
	488	intc_enum enum_id,
02ab3f70 MD	489	unsigned int irq)
02ab3f70 MD	490	{
3d37d94e	491	struct intc_handle_int *hp;
680c4598 MD	492	unsigned int data[2], primary;
	493
	494	/* Prefer single interrupt source bitmap over other combinations:
	495	* 1. bitmap, single interrupt source
	496	* 2. priority, single interrupt source
	497	* 3. bitmap, multiple interrupt sources (groups)
	498	* 4. priority, multiple interrupt sources (groups)
	499	*/
02ab3f70	500
73505b44 MD	501	data[0] = intc_mask_data(desc, d, enum_id, 0);
73505b44 MD	502	data[1] = intc_prio_data(desc, d, enum_id, 0);
680c4598 MD	503
	504	primary = 0;
	505	if (!data[0] && data[1])
	506	primary = 1;
	507
73505b44 MD	508	data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
73505b44 MD	509	data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
680c4598 MD	510
	511	if (!data[primary])
	512	primary ^= 1;
	513
	514	BUG_ON(!data[primary]); /* must have primary masking method */
02ab3f70 MD	515
02ab3f70 MD	516	disable_irq_nosync(irq);
73505b44	517	set_irq_chip_and_handler_name(irq, &d->chip,
02ab3f70	518	handle_level_irq, "level");
680c4598	519	set_irq_chip_data(irq, (void *)data[primary]);
02ab3f70	520
73505b44 MD	521	/* record the desired priority level */
	522	intc_prio_level[irq] = intc_prio_value(desc, enum_id, 1);
	523
680c4598 MD	524	/* enable secondary masking method if present */
680c4598 MD	525	if (data[!primary])
73505b44 MD	526	_intc_enable(irq, data[!primary]);
	527
	528	/* add irq to d->prio list if priority is available */
	529	if (data[1]) {
3d37d94e MD	530	hp = d->prio + d->nr_prio;
	531	hp->irq = irq;
	532	hp->handle = data[1];
	533
	534	if (primary) {
	535	/*
	536	* only secondary priority should access registers, so
	537	* set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
	538	*/
	539
	540	hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
	541	hp->handle \|= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
	542	}
73505b44 MD	543	d->nr_prio++;
	544	}
	545
	546	/* add irq to d->sense list if sense is available */
	547	data[0] = intc_sense_data(desc, d, enum_id);
	548	if (data[0]) {
	549	(d->sense + d->nr_sense)->irq = irq;
	550	(d->sense + d->nr_sense)->handle = data[0];
	551	d->nr_sense++;
	552	}
02ab3f70 MD	553
02ab3f70 MD	554	/* irq should be disabled by default */
73505b44	555	d->chip.mask(irq);
02ab3f70 MD	556	}
02ab3f70 MD	557
f18d533e MD	558	static unsigned int __init save_reg(struct intc_desc_int *d,
	559	unsigned int cnt,
	560	unsigned long value,
	561	unsigned int smp)
	562	{
	563	if (value) {
	564	d->reg[cnt] = value;
	565	#ifdef CONFIG_SMP
	566	d->smp[cnt] = smp;
	567	#endif
	568	return 1;
	569	}
	570
	571	return 0;
	572	}
	573
	574
02ab3f70 MD	575	void __init register_intc_controller(struct intc_desc *desc)
02ab3f70 MD	576	{
f18d533e	577	unsigned int i, k, smp;
73505b44 MD	578	struct intc_desc_int *d;
	579
	580	d = alloc_bootmem(sizeof(*d));
	581
	582	d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0;
	583	d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
	584	d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;
	585
	586	d->reg = alloc_bootmem(d->nr_reg * sizeof(*d->reg));
f18d533e MD	587	#ifdef CONFIG_SMP
	588	d->smp = alloc_bootmem(d->nr_reg * sizeof(*d->smp));
	589	#endif
73505b44 MD	590	k = 0;
	591
	592	if (desc->mask_regs) {
	593	for (i = 0; i < desc->nr_mask_regs; i++) {
f18d533e MD	594	smp = IS_SMP(desc->mask_regs[i]);
	595	k += save_reg(d, k, desc->mask_regs[i].set_reg, smp);
	596	k += save_reg(d, k, desc->mask_regs[i].clr_reg, smp);
73505b44 MD	597	}
	598	}
	599
	600	if (desc->prio_regs) {
	601	d->prio = alloc_bootmem(desc->nr_vectors * sizeof(*d->prio));
	602
	603	for (i = 0; i < desc->nr_prio_regs; i++) {
f18d533e MD	604	smp = IS_SMP(desc->prio_regs[i]);
	605	k += save_reg(d, k, desc->prio_regs[i].set_reg, smp);
	606	k += save_reg(d, k, desc->prio_regs[i].clr_reg, smp);
73505b44 MD	607	}
	608	}
	609
	610	if (desc->sense_regs) {
	611	d->sense = alloc_bootmem(desc->nr_vectors * sizeof(*d->sense));
	612
	613	for (i = 0; i < desc->nr_sense_regs; i++) {
f18d533e	614	k += save_reg(d, k, desc->sense_regs[i].reg, 0);
73505b44 MD	615	}
	616	}
	617
	618	BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
02ab3f70	619
73505b44 MD	620	d->chip.name = desc->name;
	621	d->chip.mask = intc_disable;
	622	d->chip.unmask = intc_enable;
	623	d->chip.mask_ack = intc_disable;
	624	d->chip.set_type = intc_set_sense;
02ab3f70 MD	625
	626	for (i = 0; i < desc->nr_vectors; i++) {
	627	struct intc_vect *vect = desc->vectors + i;
	628
73505b44	629	intc_register_irq(desc, d, vect->enum_id, evt2irq(vect->vect));
02ab3f70 MD	630	}
02ab3f70 MD	631	}